mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
32x: drc: ARM implementation, start unification with SVP (untested)
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@821 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
f4bb5d6b2c
commit
65c75cb07d
8 changed files with 237 additions and 95 deletions
|
|
@ -35,7 +35,7 @@ void ssp_drc_next_patch(void){}
|
|||
void ssp_drc_end(void){}
|
||||
#endif
|
||||
|
||||
#include "gen_arm.c"
|
||||
#include "../../../cpu/drc/emit_arm.c"
|
||||
|
||||
// -----------------------------------------------------
|
||||
|
||||
|
|
@ -285,11 +285,11 @@ static void tr_flush_dirty_prs(void)
|
|||
int i, ror = 0, reg;
|
||||
int dirty = dirty_regb >> 8;
|
||||
if ((dirty&7) == 7) {
|
||||
emit_mov_const(A_COND_AL, 8, known_regs.r[0]|(known_regs.r[1]<<8)|(known_regs.r[2]<<16));
|
||||
emith_move_r_imm(8, known_regs.r[0]|(known_regs.r[1]<<8)|(known_regs.r[2]<<16));
|
||||
dirty &= ~7;
|
||||
}
|
||||
if ((dirty&0x70) == 0x70) {
|
||||
emit_mov_const(A_COND_AL, 9, known_regs.r[4]|(known_regs.r[5]<<8)|(known_regs.r[6]<<16));
|
||||
emith_move_r_imm(9, known_regs.r[4]|(known_regs.r[5]<<8)|(known_regs.r[6]<<16));
|
||||
dirty &= ~0x70;
|
||||
}
|
||||
/* r0-r7 */
|
||||
|
|
@ -348,14 +348,14 @@ static void tr_make_dirty_ST(void)
|
|||
static void tr_mov16(int r, int val)
|
||||
{
|
||||
if (hostreg_r[r] != val) {
|
||||
emit_mov_const(A_COND_AL, r, val);
|
||||
emith_move_r_imm(r, val);
|
||||
hostreg_r[r] = val;
|
||||
}
|
||||
}
|
||||
|
||||
static void tr_mov16_cond(int cond, int r, int val)
|
||||
{
|
||||
emit_mov_const(cond, r, val);
|
||||
emith_op_imm(cond, A_OP_MOV, r, val);
|
||||
hostreg_r[r] = -1;
|
||||
}
|
||||
|
||||
|
|
@ -367,7 +367,7 @@ static void tr_flush_dirty_pmcrs(void)
|
|||
|
||||
if (dirty_regb & KRREG_PMC) {
|
||||
val = known_regs.pmc.v;
|
||||
emit_mov_const(A_COND_AL, 1, val);
|
||||
emith_move_r_imm(1, val);
|
||||
EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
|
||||
|
||||
if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) {
|
||||
|
|
@ -380,14 +380,14 @@ static void tr_flush_dirty_pmcrs(void)
|
|||
if (dirty_regb & (1 << (20+i))) {
|
||||
if (val != known_regs.pmac_read[i]) {
|
||||
val = known_regs.pmac_read[i];
|
||||
emit_mov_const(A_COND_AL, 1, val);
|
||||
emith_move_r_imm(1, val);
|
||||
}
|
||||
EOP_STR_IMM(1,7,0x454+i*4); // pmac_read
|
||||
}
|
||||
if (dirty_regb & (1 << (25+i))) {
|
||||
if (val != known_regs.pmac_write[i]) {
|
||||
val = known_regs.pmac_write[i];
|
||||
emit_mov_const(A_COND_AL, 1, val);
|
||||
emith_move_r_imm(1, val);
|
||||
}
|
||||
EOP_STR_IMM(1,7,0x46c+i*4); // pmac_write
|
||||
}
|
||||
|
|
@ -792,7 +792,7 @@ static void tr_PMX_to_r0(int reg)
|
|||
if ((mode & 0xfff0) == 0x0800)
|
||||
{
|
||||
EOP_LDR_IMM(1,7,0x488); // rom_ptr
|
||||
emit_mov_const(A_COND_AL, 0, (pmcv&0xfffff)<<1);
|
||||
emith_move_r_imm(0, (pmcv&0xfffff)<<1);
|
||||
EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
|
||||
known_regs.pmac_read[reg] += 1;
|
||||
}
|
||||
|
|
@ -800,7 +800,7 @@ static void tr_PMX_to_r0(int reg)
|
|||
{
|
||||
int inc = get_inc(mode);
|
||||
EOP_LDR_IMM(1,7,0x490); // dram_ptr
|
||||
emit_mov_const(A_COND_AL, 0, (pmcv&0xffff)<<1);
|
||||
emith_move_r_imm(0, (pmcv&0xffff)<<1);
|
||||
EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
|
||||
if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection
|
||||
{
|
||||
|
|
@ -835,7 +835,7 @@ static void tr_PMX_to_r0(int reg)
|
|||
tr_flush_dirty_ST();
|
||||
//tr_flush_dirty_pmcrs();
|
||||
tr_mov16(0, reg);
|
||||
emit_call(A_COND_AL, ssp_pm_read);
|
||||
emith_call(ssp_pm_read);
|
||||
hostreg_clear();
|
||||
}
|
||||
|
||||
|
|
@ -1034,7 +1034,7 @@ static void tr_r0_to_PMX(int reg)
|
|||
int inc = get_inc(mode);
|
||||
if (mode & 0x0400) tr_unhandled();
|
||||
EOP_LDR_IMM(1,7,0x490); // dram_ptr
|
||||
emit_mov_const(A_COND_AL, 2, addr<<1);
|
||||
emith_move_r_imm(2, addr << 1);
|
||||
EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
|
||||
known_regs.pmac_write[reg] += inc;
|
||||
}
|
||||
|
|
@ -1042,7 +1042,7 @@ static void tr_r0_to_PMX(int reg)
|
|||
{
|
||||
if (mode & 0x0400) tr_unhandled();
|
||||
EOP_LDR_IMM(1,7,0x490); // dram_ptr
|
||||
emit_mov_const(A_COND_AL, 2, addr<<1);
|
||||
emith_move_r_imm(2, addr << 1);
|
||||
EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
|
||||
known_regs.pmac_write[reg] += (addr&1) ? 31 : 1;
|
||||
}
|
||||
|
|
@ -1050,7 +1050,7 @@ static void tr_r0_to_PMX(int reg)
|
|||
{
|
||||
int inc = get_inc(mode);
|
||||
EOP_LDR_IMM(1,7,0x48c); // iram_ptr
|
||||
emit_mov_const(A_COND_AL, 2, (addr&0x3ff)<<1);
|
||||
emith_move_r_imm(2, (addr&0x3ff) << 1);
|
||||
EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
|
||||
EOP_MOV_IMM(1,0,1);
|
||||
EOP_STR_IMM(1,7,0x494); // iram_dirty
|
||||
|
|
@ -1076,7 +1076,7 @@ static void tr_r0_to_PMX(int reg)
|
|||
tr_flush_dirty_ST();
|
||||
//tr_flush_dirty_pmcrs();
|
||||
tr_mov16(1, reg);
|
||||
emit_call(A_COND_AL, ssp_pm_write);
|
||||
emith_call(ssp_pm_write);
|
||||
hostreg_clear();
|
||||
}
|
||||
|
||||
|
|
@ -1117,7 +1117,7 @@ static void tr_r0_to_PMC(int const_val)
|
|||
{
|
||||
tr_flush_dirty_ST();
|
||||
if (known_regb & KRREG_PMC) {
|
||||
emit_mov_const(A_COND_AL, 1, known_regs.pmc.v);
|
||||
emith_move_r_imm(1, known_regs.pmc.v);
|
||||
EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
|
||||
known_regb &= ~KRREG_PMC;
|
||||
dirty_regb &= ~KRREG_PMC;
|
||||
|
|
@ -1666,7 +1666,7 @@ static void emit_block_prologue(void)
|
|||
// check if there are enough cycles..
|
||||
// note: r0 must contain PC of current block
|
||||
EOP_CMP_IMM(11,0,0); // cmp r11, #0
|
||||
emit_jump(A_COND_LE, ssp_drc_end);
|
||||
emith_jump_cond(A_COND_LE, ssp_drc_end);
|
||||
}
|
||||
|
||||
/* cond:
|
||||
|
|
@ -1680,16 +1680,16 @@ static void emit_block_epilogue(int cycles, int cond, int pc, int end_pc)
|
|||
|
||||
if (cond < 0 || (end_pc >= 0x400 && pc < 0x400)) {
|
||||
// indirect jump, or rom -> iram jump, must use dispatcher
|
||||
emit_jump(A_COND_AL, ssp_drc_next);
|
||||
emith_jump(ssp_drc_next);
|
||||
}
|
||||
else if (cond == A_COND_AL) {
|
||||
u32 *target = (pc < 0x400) ?
|
||||
ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + pc] :
|
||||
ssp_block_table[pc];
|
||||
if (target != NULL)
|
||||
emit_jump(A_COND_AL, target);
|
||||
emith_jump(target);
|
||||
else {
|
||||
int ops = emit_jump(A_COND_AL, ssp_drc_next);
|
||||
int ops = emith_jump(ssp_drc_next);
|
||||
// cause the next block to be emitted over jump instruction
|
||||
tcache_ptr -= ops;
|
||||
}
|
||||
|
|
@ -1702,19 +1702,19 @@ static void emit_block_epilogue(int cycles, int cond, int pc, int end_pc)
|
|||
ssp_block_table_iram[ssp->drc.iram_context * SSP_BLOCKTAB_IRAM_ONE + end_pc] :
|
||||
ssp_block_table[end_pc];
|
||||
if (target1 != NULL)
|
||||
emit_jump(cond, target1);
|
||||
emith_jump_cond(cond, target1);
|
||||
if (target2 != NULL)
|
||||
emit_jump(tr_neg_cond(cond), target2); // neg_cond, to be able to swap jumps if needed
|
||||
emith_jump_cond(tr_neg_cond(cond), target2); // neg_cond, to be able to swap jumps if needed
|
||||
#ifndef __EPOC32__
|
||||
// emit patchable branches
|
||||
if (target1 == NULL)
|
||||
emit_call(cond, ssp_drc_next_patch);
|
||||
emith_call_cond(cond, ssp_drc_next_patch);
|
||||
if (target2 == NULL)
|
||||
emit_call(tr_neg_cond(cond), ssp_drc_next_patch);
|
||||
emith_call_cond(tr_neg_cond(cond), ssp_drc_next_patch);
|
||||
#else
|
||||
// won't patch indirect jumps
|
||||
if (target1 == NULL || target2 == NULL)
|
||||
emit_jump(A_COND_AL, ssp_drc_next);
|
||||
emith_jump(ssp_drc_next);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
|
@ -1758,7 +1758,7 @@ void *ssp_translate_block(int pc)
|
|||
if (ccount >= 100) {
|
||||
end_cond = A_COND_AL;
|
||||
jump_pc = pc;
|
||||
emit_mov_const(A_COND_AL, 0, pc);
|
||||
emith_move_r_imm(0, pc);
|
||||
}
|
||||
|
||||
tr_flush_dirty_prs();
|
||||
|
|
|
|||
|
|
@ -1,234 +0,0 @@
|
|||
// Basic macros to emit ARM instructions and some utils
|
||||
|
||||
// (c) Copyright 2008, Grazvydas "notaz" Ignotas
|
||||
// Free for non-commercial use.
|
||||
|
||||
#define EMIT(x) *tcache_ptr++ = x
|
||||
|
||||
#define A_R4M (1 << 4)
|
||||
#define A_R5M (1 << 5)
|
||||
#define A_R6M (1 << 6)
|
||||
#define A_R7M (1 << 7)
|
||||
#define A_R8M (1 << 8)
|
||||
#define A_R9M (1 << 9)
|
||||
#define A_R10M (1 << 10)
|
||||
#define A_R11M (1 << 11)
|
||||
#define A_R14M (1 << 14)
|
||||
|
||||
#define A_COND_AL 0xe
|
||||
#define A_COND_EQ 0x0
|
||||
#define A_COND_NE 0x1
|
||||
#define A_COND_MI 0x4
|
||||
#define A_COND_PL 0x5
|
||||
#define A_COND_LE 0xd
|
||||
|
||||
/* addressing mode 1 */
|
||||
#define A_AM1_LSL 0
|
||||
#define A_AM1_LSR 1
|
||||
#define A_AM1_ASR 2
|
||||
#define A_AM1_ROR 3
|
||||
|
||||
#define A_AM1_IMM(ror2,imm8) (((ror2)<<8) | (imm8) | 0x02000000)
|
||||
#define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm))
|
||||
#define A_AM1_REG_XREG(rs,shift_op,rm) (((rs)<<8) | ((shift_op)<<5) | 0x10 | (rm))
|
||||
|
||||
/* data processing op */
|
||||
#define A_OP_AND 0x0
|
||||
#define A_OP_EOR 0x1
|
||||
#define A_OP_SUB 0x2
|
||||
#define A_OP_RSB 0x3
|
||||
#define A_OP_ADD 0x4
|
||||
#define A_OP_TST 0x8
|
||||
#define A_OP_CMP 0xa
|
||||
#define A_OP_ORR 0xc
|
||||
#define A_OP_MOV 0xd
|
||||
#define A_OP_BIC 0xe
|
||||
|
||||
#define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
|
||||
EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))
|
||||
|
||||
#define EOP_C_DOP_IMM( cond,op,s,rn,rd,ror2,imm8) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
|
||||
#define EOP_C_DOP_REG_XIMM(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
|
||||
#define EOP_C_DOP_REG_XREG(cond,op,s,rn,rd,rs, shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XREG(rs, shift_op,rm))
|
||||
|
||||
#define EOP_MOV_IMM(rd, ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
|
||||
#define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
|
||||
#define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
|
||||
#define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8)
|
||||
#define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
|
||||
#define EOP_SUB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_SUB,0,rn,rd,ror2,imm8)
|
||||
#define EOP_TST_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_TST,1,rn, 0,ror2,imm8)
|
||||
#define EOP_CMP_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_CMP,1,rn, 0,ror2,imm8)
|
||||
#define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8)
|
||||
|
||||
#define EOP_MOV_REG(s, rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
|
||||
#define EOP_ORR_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
|
||||
#define EOP_ADD_REG(s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
|
||||
#define EOP_TST_REG( rn, shift_imm,shift_op,rm) EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)
|
||||
|
||||
#define EOP_MOV_REG2(s, rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm)
|
||||
#define EOP_ADD_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm)
|
||||
#define EOP_SUB_REG2(s,rn,rd,rs,shift_op,rm) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm)
|
||||
|
||||
#define EOP_MOV_REG_SIMPLE(rd,rm) EOP_MOV_REG(0,rd,0,A_AM1_LSL,rm)
|
||||
#define EOP_MOV_REG_LSL(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSL,rm)
|
||||
#define EOP_MOV_REG_LSR(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_LSR,rm)
|
||||
#define EOP_MOV_REG_ASR(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ASR,rm)
|
||||
#define EOP_MOV_REG_ROR(rd, rm,shift_imm) EOP_MOV_REG(0,rd,shift_imm,A_AM1_ROR,rm)
|
||||
|
||||
#define EOP_ORR_REG_SIMPLE(rd,rm) EOP_ORR_REG(0,rd,rd,0,A_AM1_LSL,rm)
|
||||
#define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
|
||||
#define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
|
||||
#define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ASR,rm)
|
||||
#define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(0,rn,rd,shift_imm,A_AM1_ROR,rm)
|
||||
|
||||
#define EOP_ADD_REG_SIMPLE(rd,rm) EOP_ADD_REG(0,rd,rd,0,A_AM1_LSL,rm)
|
||||
#define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSL,rm)
|
||||
#define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(0,rn,rd,shift_imm,A_AM1_LSR,rm)
|
||||
|
||||
#define EOP_TST_REG_SIMPLE(rn,rm) EOP_TST_REG( rn, 0,A_AM1_LSL,rm)
|
||||
|
||||
#define EOP_MOV_REG2_LSL(rd, rm,rs) EOP_MOV_REG2(0, rd,rs,A_AM1_LSL,rm)
|
||||
#define EOP_MOV_REG2_ROR(rd, rm,rs) EOP_MOV_REG2(0, rd,rs,A_AM1_ROR,rm)
|
||||
#define EOP_ADD_REG2_LSL(rd,rn,rm,rs) EOP_ADD_REG2(0,rn,rd,rs,A_AM1_LSL,rm)
|
||||
#define EOP_SUB_REG2_LSL(rd,rn,rm,rs) EOP_SUB_REG2(0,rn,rd,rs,A_AM1_LSL,rm)
|
||||
|
||||
/* addressing mode 2 */
|
||||
#define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
|
||||
EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))
|
||||
|
||||
/* addressing mode 3 */
|
||||
#define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \
|
||||
EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
|
||||
((s)<<6) | ((h)<<5) | (immed_reg))
|
||||
|
||||
#define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) EOP_C_AM3(cond,u,1,l,rn,rd,s,h,(((offset_8)&0xf0)<<4)|((offset_8)&0xf))
|
||||
|
||||
#define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm) EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
|
||||
|
||||
/* ldr and str */
|
||||
#define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
|
||||
#define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
|
||||
#define EOP_LDR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
|
||||
#define EOP_STR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
|
||||
#define EOP_STR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
|
||||
|
||||
#define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
|
||||
#define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
|
||||
#define EOP_LDRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
|
||||
#define EOP_STRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
|
||||
#define EOP_STRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
|
||||
#define EOP_STRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,0,rn,rd,0,1,rm)
|
||||
|
||||
/* ldm and stm */
|
||||
#define EOP_XXM(cond,p,u,s,w,l,rn,list) \
|
||||
EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list))
|
||||
|
||||
#define EOP_STMFD_ST(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list)
|
||||
#define EOP_LDMFD_ST(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list)
|
||||
|
||||
/* branches */
|
||||
#define EOP_C_BX(cond,rm) \
|
||||
EMIT(((cond)<<28) | 0x012fff10 | (rm))
|
||||
|
||||
#define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)
|
||||
|
||||
#define EOP_C_B(cond,l,signed_immed_24) \
|
||||
EMIT(((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
|
||||
|
||||
#define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
|
||||
#define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
|
||||
|
||||
/* misc */
|
||||
#define EOP_C_MUL(cond,s,rd,rs,rm) \
|
||||
EMIT(((cond)<<28) | ((s)<<20) | ((rd)<<16) | ((rs)<<8) | 0x90 | (rm))
|
||||
|
||||
#define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm
|
||||
|
||||
#define EOP_C_MRS(cond,rd) \
|
||||
EMIT(((cond)<<28) | 0x010f0000 | ((rd)<<12))
|
||||
|
||||
#define EOP_C_MSR_IMM(cond,ror2,imm) \
|
||||
EMIT(((cond)<<28) | 0x0328f000 | ((ror2)<<8) | (imm)) // cpsr_f
|
||||
|
||||
#define EOP_C_MSR_REG(cond,rm) \
|
||||
EMIT(((cond)<<28) | 0x0128f000 | (rm)) // cpsr_f
|
||||
|
||||
#define EOP_MRS(rd) EOP_C_MRS(A_COND_AL,rd)
|
||||
#define EOP_MSR_IMM(ror2,imm) EOP_C_MSR_IMM(A_COND_AL,ror2,imm)
|
||||
#define EOP_MSR_REG(rm) EOP_C_MSR_REG(A_COND_AL,rm)
|
||||
|
||||
|
||||
static void emit_mov_const(int cond, int d, unsigned int val)
|
||||
{
|
||||
int need_or = 0;
|
||||
if (val & 0xff000000) {
|
||||
EOP_C_DOP_IMM(cond, A_OP_MOV, 0, 0, d, 8/2, (val>>24)&0xff);
|
||||
need_or = 1;
|
||||
}
|
||||
if (val & 0x00ff0000) {
|
||||
EOP_C_DOP_IMM(cond, need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 16/2, (val>>16)&0xff);
|
||||
need_or = 1;
|
||||
}
|
||||
if (val & 0x0000ff00) {
|
||||
EOP_C_DOP_IMM(cond, need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 24/2, (val>>8)&0xff);
|
||||
need_or = 1;
|
||||
}
|
||||
if ((val &0x000000ff) || !need_or)
|
||||
EOP_C_DOP_IMM(cond, need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 0, val&0xff);
|
||||
}
|
||||
|
||||
static int is_offset_24(int val)
|
||||
{
|
||||
if (val >= (int)0xff000000 && val <= 0x00ffffff) return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int emit_xbranch(int cond, void *target, int is_call)
|
||||
{
|
||||
int val = (unsigned int *)target - tcache_ptr - 2;
|
||||
int direct = is_offset_24(val);
|
||||
u32 *start_ptr = tcache_ptr;
|
||||
|
||||
if (direct)
|
||||
{
|
||||
EOP_C_B(cond,is_call,val & 0xffffff); // b, bl target
|
||||
}
|
||||
else
|
||||
{
|
||||
#ifdef __EPOC32__
|
||||
// elprintf(EL_SVP, "emitting indirect jmp %08x->%08x", tcache_ptr, target);
|
||||
if (is_call)
|
||||
EOP_ADD_IMM(14,15,0,8); // add lr,pc,#8
|
||||
EOP_C_AM2_IMM(cond,1,0,1,15,15,0); // ldrcc pc,[pc]
|
||||
EOP_MOV_REG_SIMPLE(15,15); // mov pc, pc
|
||||
EMIT((u32)target);
|
||||
#else
|
||||
// should never happen
|
||||
elprintf(EL_STATUS|EL_SVP|EL_ANOMALY, "indirect jmp %08x->%08x", target, tcache_ptr);
|
||||
exit(1);
|
||||
#endif
|
||||
}
|
||||
|
||||
return tcache_ptr - start_ptr;
|
||||
}
|
||||
|
||||
static int emit_call(int cond, void *target)
|
||||
{
|
||||
return emit_xbranch(cond, target, 1);
|
||||
}
|
||||
|
||||
static int emit_jump(int cond, void *target)
|
||||
{
|
||||
return emit_xbranch(cond, target, 0);
|
||||
}
|
||||
|
||||
static void handle_caches(void)
|
||||
{
|
||||
#ifdef ARM
|
||||
extern void cache_flush_d_inval_i(const void *start_addr, const void *end_addr);
|
||||
cache_flush_d_inval_i(tcache, tcache_ptr);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue