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svp..
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@325 be3aeb3a-fb24-0410-a615-afba39da0efa
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notaz
parent
d26dc685a4
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1 changed files with 91 additions and 19 deletions
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@ -149,6 +149,8 @@
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* mod cond, op
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* mod cond, shr does arithmetic shift
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*
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* 'ld -, AL' and probably 'ld AL, -' are for dummy assigns
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*
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* memory map:
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* 000000 - 1fffff ROM, accessable by both
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* 200000 - 2fffff unused?
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@ -162,6 +164,12 @@
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* 30fe06 - also sync related.
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* 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
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*
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* TODO:
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* + figure out if 'op A, P' is 32bit (nearly sure it is)
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* * what exactly is AL?
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* * does mld, mpya load their operands into X and Y?
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* * OP simm
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*
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* misc:
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* pressing all buttons while resetting game will kick into test mode
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*
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@ -225,6 +233,11 @@
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// it seems SVP code never checks for L and OV, so we leave them out.
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// rST |= (t>>4)&SSP_FLAG_L;
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#define UPD_LZVN \
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rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
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if (!rA32) rST |= SSP_FLAG_Z; \
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else rST |= (rA32>>16)&SSP_FLAG_N;
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#define UPD_t_LZVN \
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rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
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if (!t) rST |= SSP_FLAG_Z; \
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@ -246,35 +259,75 @@
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#define OP_LDA(x) \
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ssp->gr[SSP_A].h = x
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#define OP_LDA32(x) \
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ssp->gr[SSP_A].v = x
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#define OP_SUBA(x) { \
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u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
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UPD_t_LZVN \
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ssp->gr[SSP_A].h = t; \
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}
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#define OP_SUBA32(x) { \
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ssp->gr[SSP_A].v -= (x); \
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UPD_LZVN \
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}
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#define OP_CMPA(x) { \
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u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
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UPD_t_LZVN \
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}
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#define OP_CMPA32(x) { \
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u32 t = ssp->gr[SSP_A].v - (x); \
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rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
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if (!t) rST |= SSP_FLAG_Z; \
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else rST |= (t>>16)&SSP_FLAG_N; \
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}
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#define OP_ADDA(x) { \
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u32 t = (ssp->gr[SSP_A].v >> 16) + (x); \
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UPD_t_LZVN \
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ssp->gr[SSP_A].h = t; \
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}
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#define OP_ADDA32(x) { \
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ssp->gr[SSP_A].v += (x); \
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UPD_LZVN \
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}
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#define OP_ANDA(x) \
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ssp->gr[SSP_A].v &= (x) << 16; \
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UPD_ACC_ZN
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#define OP_ANDA32(x) \
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ssp->gr[SSP_A].v &= (x); \
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UPD_ACC_ZN
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#define OP_ORA(x) \
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ssp->gr[SSP_A].v |= (x) << 16; \
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UPD_ACC_ZN
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#define OP_ORA32(x) \
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ssp->gr[SSP_A].v |= (x); \
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UPD_ACC_ZN
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#define OP_EORA(x) \
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ssp->gr[SSP_A].v ^= (x) << 16; \
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UPD_ACC_ZN
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#define OP_EORA32(x) \
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ssp->gr[SSP_A].v ^= (x); \
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UPD_ACC_ZN
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#define OP_CHECK32(OP) \
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if ((op & 0x0f) == SSP_P) { /* A <- P */ \
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read_P(); /* update P */ \
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OP(ssp->gr[SSP_P].v); \
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break; \
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}
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static ssp1601_t *ssp = NULL;
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static unsigned short *PC;
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@ -374,7 +427,15 @@ static void debug_dump2file(const char *fname, void *mem, int len);
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static u32 pm_io(int reg, int write, u32 d)
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{
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if (ssp->emu_status & SSP_PMC_SET) {
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if (ssp->emu_status & SSP_PMC_SET)
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{
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// this MUST be blind r or w
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if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
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elprintf(EL_SVP|EL_ANOMALY, "FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
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reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
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ssp->emu_status &= ~SSP_PMC_SET;
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return 0;
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}
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elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
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ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
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ssp->emu_status &= ~SSP_PMC_SET;
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@ -401,7 +462,11 @@ static u32 pm_io(int reg, int write, u32 d)
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}
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// just in case
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ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
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if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
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elprintf(EL_SVP|EL_ANOMALY, "FIXME: PM%i (%c) with only addr set @ %04x",
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reg, write ? 'w' : 'r', GET_PPC_OFFS());
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ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
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}
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// if (ssp->pmac_read[reg] != 0)
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if (reg == 4 || (rST & 0x60))
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@ -414,23 +479,23 @@ static u32 pm_io(int reg, int write, u32 d)
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int mode = ssp->pmac_write[reg]&0xffff;
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int addr = ssp->pmac_write[reg]>>16;
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switch (mode) {
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case 0x0018: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x", CADDR, d);
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case 0x0018: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x", reg, CADDR, d);
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dram[addr] = d;
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break;
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case 0x0418: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (overwr)", CADDR, d);
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case 0x0418: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (overwr)", reg, CADDR, d);
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overwite_write(dram[addr], d);
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break;
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case 0x0818: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (inc 1)", CADDR, d);
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case 0x0818: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc 1)", reg, CADDR, d);
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dram[addr] = d;
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ssp->pmac_write[reg] += 1<<16;
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break;
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case 0x081c: iram_write(addr, d, reg, 1); break; // checked: used by code @ 0902
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case 0x101c: iram_write(addr, d, reg, 2); break; // checked: used by code @ 3b7c
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case 0x4018: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (cell inc)", CADDR, d);
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case 0x4018: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc)", reg, CADDR, d);
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dram[addr] = d;
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ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
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break;
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case 0x4418: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (overwr, cell inc)", CADDR, d);
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case 0x4418: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (overwr, cell inc)", reg, CADDR, d);
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overwite_write(dram[addr], d);
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ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
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break;
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@ -454,7 +519,7 @@ static u32 pm_io(int reg, int write, u32 d)
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case 0x0018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x", CADDR, dram[addr]);
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d = dram[addr]; // checked
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break;
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case 0x0818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 1)", CADDR, dram[addr]);
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case 0x0818: elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc 1)", reg, CADDR, dram[addr]);
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ssp->pmac_read[reg] += 1<<16;
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d = dram[addr];
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break;
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@ -492,8 +557,7 @@ static u32 read_PM0(void)
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{
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u32 d = pm_io(0, 0, 0);
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if (d != (u32)-1) return d;
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if (GET_PPC_OFFS() != 0x800 || rPM0 != 0) // debug
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elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
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elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
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d = rPM0;
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if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
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ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
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@ -598,15 +662,16 @@ static void write_PM4(u32 d)
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// 14
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static u32 read_PMC(void)
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{
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elprintf(EL_SVP, "PMC r %08x @ %04x", rPMC.v, GET_PPC_OFFS());
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if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
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if (ssp->emu_status & SSP_PMC_SET)
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elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
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ssp->emu_status |= SSP_PMC_SET;
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ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
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elprintf(EL_SVP, "PMC r m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
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return rPMC.l;
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} else {
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ssp->emu_status |= SSP_PMC_HAVE_ADDR;
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elprintf(EL_SVP, "PMC r a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
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return rPMC.h;
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}
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}
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@ -619,9 +684,11 @@ static void write_PMC(u32 d)
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ssp->emu_status |= SSP_PMC_SET;
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ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
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rPMC.l = d;
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elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
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} else {
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ssp->emu_status |= SSP_PMC_HAVE_ADDR;
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rPMC.h = d;
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elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
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}
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}
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@ -629,13 +696,18 @@ static void write_PMC(u32 d)
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static u32 read_AL(void)
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{
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// TODO: figure out what's up with those blind reads..
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if (*(PC-1) == 0x000f)
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elprintf(EL_SVP|EL_ANOMALY, "ssp unhandled AL blind read..");
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if (*(PC-1) == 0x000f) {
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elprintf(EL_SVP|EL_ANOMALY, "ssp dummy PM assign %08x, ST=%04x @ %04x", rPMC.v, rST, GET_PPC_OFFS());
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ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
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} else {
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//elprintf(EL_SVP, "ssp AL read, ST=%04x @ %04x", rST, GET_PPC_OFFS());
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}
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return rAL;
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}
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static void write_AL(u32 d)
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{
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//elprintf(EL_SVP, "ssp AL write %04x, ST=%04x @ %04x", d, rST, GET_PPC_OFFS());
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rAL = d;
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}
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@ -1065,12 +1137,12 @@ void ssp1601_run(int cycles)
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break;
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// OP a, s
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case 0x10: tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
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case 0x30: tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
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case 0x40: tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
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case 0x50: tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
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case 0x60: tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
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case 0x70: tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
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case 0x10: OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
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case 0x30: OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
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case 0x40: OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
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case 0x50: OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
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case 0x60: OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
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case 0x70: OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
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// OP a, (ri)
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case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
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