mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
32x: interpreter-wrap drc works (demos only). SVP drc refactoring.
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@812 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
98da48e418
commit
679af8a3f4
19 changed files with 1505 additions and 46 deletions
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@ -5,12 +5,7 @@
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#include "cmn.h"
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#ifndef ARM
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unsigned int tcache[SSP_TCACHE_SIZE/4];
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unsigned int *ssp_block_table[0x5090/2];
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unsigned int *ssp_block_table_iram[15][0x800/2];
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char ssp_align[SSP_BLOCKTAB_ALIGN_SIZE];
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#endif
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u32 tcache[DRC_TCACHE_SIZE/4];
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void drc_cmn_init(void)
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@ -18,7 +13,7 @@ void drc_cmn_init(void)
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#if defined(__linux__) && defined(ARM)
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void *tmp;
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tmp = mmap(tcache, SSP_DRC_SIZE, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_SHARED|MAP_ANONYMOUS, -1, 0);
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tmp = mmap(tcache, DRC_TCACHE_SIZE, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_SHARED|MAP_ANONYMOUS, -1, 0);
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printf("mmap tcache: %p, asked %p\n", tmp, tcache);
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#endif
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@ -29,7 +24,7 @@ void drc_cmn_cleanup(void)
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{
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#if defined(__linux__) && defined(ARM)
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int ret;
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ret = munmap(tcache, SSP_DRC_SIZE);
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ret = munmap(tcache, DRC_TCACHE_SIZE);
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printf("munmap tcache: %i\n", ret);
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#endif
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}
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@ -1,12 +1,10 @@
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#define SSP_TCACHE_SIZE (512*1024)
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#define SSP_BLOCKTAB_SIZE (0x5090/2*4)
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#define SSP_BLOCKTAB_IRAM_SIZE (15*0x800/2*4)
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#define SSP_BLOCKTAB_ALIGN_SIZE 3808
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#define SSP_DRC_SIZE (SSP_TCACHE_SIZE + SSP_BLOCKTAB_SIZE + SSP_BLOCKTAB_IRAM_SIZE + SSP_BLOCKTAB_ALIGN_SIZE)
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typedef unsigned char u8;
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typedef unsigned short u16;
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typedef unsigned int u32;
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extern unsigned int tcache[SSP_TCACHE_SIZE/4];
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extern unsigned int *ssp_block_table[SSP_BLOCKTAB_SIZE/4];
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extern unsigned int *ssp_block_table_iram[15][0x800/2];
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#define DRC_TCACHE_SIZE (512*1024)
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extern u32 tcache[DRC_TCACHE_SIZE/4];
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void drc_cmn_init(void);
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void drc_cmn_cleanup(void);
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120
cpu/drc/emit_x86.c
Normal file
120
cpu/drc/emit_x86.c
Normal file
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@ -0,0 +1,120 @@
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#include <stdarg.h>
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// TODO: move
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static int reg_map_g2h[] = {
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-1, -1, -1, -1,
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-1, -1, -1, -1,
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-1, -1, -1, -1,
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-1, -1, -1, -1,
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-1, -1, -1, -1,
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-1, -1, -1, -1,
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};
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enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define EMIT_PTR(ptr, val, type) \
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*(type *)(ptr) = val
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#define EMIT(val, type) { \
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EMIT_PTR(tcache_ptr, val, type); \
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tcache_ptr = (char *)tcache_ptr + sizeof(type); \
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}
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#define EMIT_MODRM(mod,r,rm) \
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EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)
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#define EMIT_OP_MODRM(op,mod,r,rm) { \
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EMIT(op, u8); \
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EMIT_MODRM(mod, r, rm); \
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}
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#define emith_move_r_r(dst, src) \
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EMIT_OP_MODRM(0x8b, 3, dst, src)
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#define emith_move_r_imm(r, imm) { \
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EMIT(0xb8 + (r), u8); \
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EMIT(imm, u32); \
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}
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#define emith_add_r_imm(r, imm) { \
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EMIT_OP_MODRM(0x81, 3, 0, r); \
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EMIT(imm, u32); \
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}
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#define emith_sub_r_imm(r, imm) { \
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EMIT_OP_MODRM(0x81, 3, 5, r); \
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EMIT(imm, u32); \
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}
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// XXX: offs is 8bit only
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#define emith_ctx_read(r, offs) { \
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EMIT_OP_MODRM(0x8b, 1, r, 5); \
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EMIT(offs, u8); /* mov tmp, [ebp+#offs] */ \
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}
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#define emith_ctx_write(r, offs) { \
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EMIT_OP_MODRM(0x89, 1, r, 5); \
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EMIT(offs, u8); /* mov [ebp+#offs], tmp */ \
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}
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#define emith_ctx_sub(val, offs) { \
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EMIT_OP_MODRM(0x81, 1, 5, 5); \
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EMIT(offs, u8); \
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EMIT(val, u32); /* sub [ebp+#offs], dword val */ \
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}
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#define emith_test_t() { \
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if (reg_map_g2h[SHR_SR] == -1) { \
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EMIT(0xf6, u8); \
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EMIT_MODRM(1, 0, 5); \
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EMIT(SHR_SR * 4, u8); \
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EMIT(0x01, u8); /* test [ebp+SHR_SR], byte 1 */ \
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} else { \
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EMIT(0xf7, u8); \
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EMIT_MODRM(3, 0, reg_map_g2h[SHR_SR]); \
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EMIT(0x01, u16); /* test <reg>, word 1 */ \
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} \
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}
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#define emith_jump(ptr) { \
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u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
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EMIT(0xe9, u8); \
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EMIT(disp, u32); \
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}
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#define emith_call(ptr) { \
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u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
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EMIT(0xe8, u8); \
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EMIT(disp, u32); \
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}
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#define EMIT_CONDITIONAL(code, is_nonzero) { \
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char *ptr = tcache_ptr; \
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tcache_ptr = (char *)tcache_ptr + 2; \
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code; \
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EMIT_PTR(ptr, ((is_nonzero) ? 0x75 : 0x74), u8); \
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EMIT_PTR(ptr + 1, ((char *)tcache_ptr - (ptr + 2)), u8); \
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}
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static void emith_pass_arg(int count, ...)
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{
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va_list vl;
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int i;
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va_start(vl, count);
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for (i = 0; i < count; i++) {
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long av = va_arg(vl, long);
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int r = 7;
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switch (i) {
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case 0: r = xAX; break;
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case 1: r = xDX; break;
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case 2: r = xCX; break;
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}
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emith_move_r_imm(r, av);
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}
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va_end(vl);
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}
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@ -1,10 +1,398 @@
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#include "../sh2.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <assert.h>
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#include "sh2.h"
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#include "compiler.h"
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#include "../drc/cmn.h"
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#define BLOCK_CYCLE_LIMIT 100
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typedef enum {
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SHR_R0 = 0, SHR_R15 = 15,
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SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
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SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
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} sh2_reg_e;
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typedef struct block_desc_ {
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u32 addr; // SH2 PC address
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void *tcache_ptr; // translated block for above PC
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struct block_desc_ *next; // next block with the same PC hash
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} block_desc;
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#define MAX_BLOCK_COUNT 1024
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static block_desc *block_table;
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static int block_count;
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#define MAX_HASH_ENTRIES 1024
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#define HASH_MASK (MAX_HASH_ENTRIES - 1)
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#ifdef DRC_DEBUG
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#include "mame/sh2dasm.h"
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#include <platform/linux/host_dasm.h>
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static void *tcache_dsm_ptr = tcache;
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#endif
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static void *tcache_ptr;
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#include "../drc/emit_x86.c"
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extern void sh2_drc_entry(SH2 *sh2, void *block);
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extern void sh2_drc_exit(void);
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// tmp
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extern void __attribute__((regparm(2))) sh2_do_op(SH2 *sh2, int opcode);
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static void *dr_find_block(block_desc *tab, u32 addr)
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{
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for (tab = tab->next; tab != NULL; tab = tab->next)
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if (tab->addr == addr)
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break;
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if (tab != NULL)
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return tab->tcache_ptr;
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printf("block miss for %08x\n", addr);
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return NULL;
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}
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static block_desc *dr_add_block(u32 addr, void *tcache_ptr)
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{
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block_desc *bd;
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if (block_count == MAX_BLOCK_COUNT) {
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// FIXME: flush cache instead
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printf("block descriptor overflow\n");
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exit(1);
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}
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bd = &block_table[block_count];
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bd->addr = addr;
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bd->tcache_ptr = tcache_ptr;
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block_count++;
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return bd;
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}
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#define HASH_FUNC(hash_tab, addr) \
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((block_desc **)(hash_tab))[(addr) & HASH_MASK]
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// ---------------------------------------------------------------
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static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
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{
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int host_dst = reg_map_g2h[dst];
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int tmp = 0;
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if (host_dst != -1)
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tmp = host_dst;
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emith_move_r_imm(tmp, imm);
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if (host_dst == -1)
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emith_ctx_write(tmp, dst * 4);
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}
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static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
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{
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int host_dst = reg_map_g2h[dst], host_src = reg_map_g2h[src];
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int tmp = 0;
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if (host_dst != -1 && host_src != -1) {
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emith_move_r_r(host_dst, host_src);
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return;
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}
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if (host_src != -1)
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tmp = host_src;
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if (host_dst != -1)
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tmp = host_dst;
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if (host_src == -1)
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emith_ctx_read(tmp, src * 4);
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if (host_dst == -1)
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emith_ctx_write(tmp, dst * 4);
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}
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static void emit_braf(sh2_reg_e reg, u32 pc)
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{
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int host_reg = reg_map_g2h[reg];
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if (host_reg == -1) {
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emith_ctx_read(0, reg * 4);
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} else
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emith_move_r_r(0, host_reg);
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emith_add_r_imm(0, pc);
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emith_ctx_write(0, SHR_PC * 4);
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}
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// FIXME: this is broken, delayed insn shouldn't affect branch
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#define DELAYED_OP \
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if (delayed_op < 0) { \
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delayed_op = op; \
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goto next_op; \
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} \
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delayed_op = -1; \
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pc -= 2 /* adjust back */
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/*
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static int sh2_translate_op4(int op)
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{
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switch (op & 0x000f)
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{
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case 0x0b:
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default:
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emith_pass_arg(2, sh2, op);
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emith_call(sh2_do_op);
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break;
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}
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return 0;
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}
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*/
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static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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{
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void *block_entry = tcache_ptr;
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block_desc *this_block;
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unsigned int pc = sh2->pc;
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int op, delayed_op = -1;
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int cycles = 0;
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u32 tmp;
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this_block = dr_add_block(pc, block_entry);
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if (other_block != NULL) {
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printf("hash collision between %08x and %08x\n", pc, other_block->addr);
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this_block->next = other_block;
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}
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HASH_FUNC(sh2->pc_hashtab, pc) = this_block;
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#ifdef DRC_DEBUG
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printf("== %csh2 block #%d %08x %p\n", sh2->is_slave ? 's' : 'm',
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block_count, pc, block_entry);
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#endif
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while (cycles < BLOCK_CYCLE_LIMIT)
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{
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if (delayed_op >= 0)
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op = delayed_op;
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else {
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next_op:
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op = p32x_sh2_read16(pc, sh2->is_slave);
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#ifdef DRC_DEBUG
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{
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char buff[64];
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DasmSH2(buff, pc, op);
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printf("%08x %04x %s\n", pc, op, buff);
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}
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#endif
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}
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pc += 2;
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cycles++;
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switch ((op >> 12) & 0x0f)
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{
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case 0x00:
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// RTS 0000000000001011
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if (op == 0x000b) {
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DELAYED_OP;
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emit_move_r_r(SHR_PC, SHR_PR);
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cycles++;
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goto end_block;
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}
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// RTE 0000000000101011
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if (op == 0x002b) {
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DELAYED_OP;
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cycles++;
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//emit_move_r_r(SHR_PC, SHR_PR);
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emit_move_r_imm32(SHR_PC, pc - 4);
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emith_pass_arg(2, sh2, op);
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emith_call(sh2_do_op);
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goto end_block;
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}
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// BRAF Rm 0000mmmm00100011
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if (op == 0x0023) {
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DELAYED_OP;
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cycles++;
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emit_braf((op >> 8) & 0x0f, pc);
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goto end_block;
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}
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// BSRF Rm 0000mmmm00000011
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if (op == 0x0003) {
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DELAYED_OP;
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emit_move_r_imm32(SHR_PR, pc);
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emit_braf((op >> 8) & 0x0f, pc);
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cycles++;
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goto end_block;
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}
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goto default_;
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case 0x04:
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// JMP @Rm 0100mmmm00101011
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if ((op & 0xff) == 0x2b) {
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DELAYED_OP;
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emit_move_r_r(SHR_PC, (op >> 8) & 0x0f);
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cycles++;
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goto end_block;
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}
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// JSR @Rm 0100mmmm00001011
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if ((op & 0xff) == 0x0b) {
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DELAYED_OP;
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emit_move_r_imm32(SHR_PR, pc);
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emit_move_r_r(SHR_PC, (op >> 8) & 0x0f);
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cycles++;
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goto end_block;
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}
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goto default_;
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case 0x08: {
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int adj = 2;
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switch (op & 0x0f00) {
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// BT/S label 10001101dddddddd
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case 0x0d00:
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// BF/S label 10001111dddddddd
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case 0x0f00:
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DELAYED_OP;
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cycles--;
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adj = 0;
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// fallthrough
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// BT label 10001001dddddddd
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case 0x0900:
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// BF label 10001011dddddddd
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case 0x0b00:
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cycles += 2;
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emit_move_r_imm32(SHR_PC, pc);
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emith_test_t();
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tmp = ((signed int)(op << 24) >> 23);
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EMIT_CONDITIONAL(emit_move_r_imm32(SHR_PC, pc + tmp + adj), (op & 0x0200) ? 1 : 0);
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goto end_block;
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}
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goto default_;
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}
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case 0x0a:
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// BRA label 1010dddddddddddd
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DELAYED_OP;
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do_bra:
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tmp = ((signed int)(op << 20) >> 19);
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emit_move_r_imm32(SHR_PC, pc + tmp);
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cycles++;
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goto end_block;
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case 0x0b:
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// BSR label 1011dddddddddddd
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DELAYED_OP;
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emit_move_r_imm32(SHR_PR, pc);
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goto do_bra;
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default:
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default_:
|
||||
emit_move_r_imm32(SHR_PC, pc - 2);
|
||||
emith_pass_arg(2, sh2, op);
|
||||
emith_call(sh2_do_op);
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef DRC_DEBUG
|
||||
host_dasm(tcache_dsm_ptr, (char *)tcache_ptr - (char *)tcache_dsm_ptr);
|
||||
tcache_dsm_ptr = tcache_ptr;
|
||||
#endif
|
||||
}
|
||||
|
||||
end_block:
|
||||
if ((char *)tcache_ptr - (char *)tcache > DRC_TCACHE_SIZE) {
|
||||
printf("tcache overflow!\n");
|
||||
fflush(stdout);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
if (reg_map_g2h[SHR_SR] == -1) {
|
||||
emith_ctx_sub(cycles << 12, SHR_SR * 4);
|
||||
} else
|
||||
emith_sub_r_imm(reg_map_g2h[SHR_SR], cycles << 12);
|
||||
emith_jump(sh2_drc_exit);
|
||||
|
||||
#ifdef DRC_DEBUG
|
||||
host_dasm(tcache_dsm_ptr, (char *)tcache_ptr - (char *)tcache_dsm_ptr);
|
||||
tcache_dsm_ptr = tcache_ptr;
|
||||
#endif
|
||||
return block_entry;
|
||||
|
||||
unimplemented:
|
||||
// last op
|
||||
#ifdef DRC_DEBUG
|
||||
host_dasm(tcache_dsm_ptr, (char *)tcache_ptr - (char *)tcache_dsm_ptr);
|
||||
tcache_dsm_ptr = tcache_ptr;
|
||||
#endif
|
||||
exit(1);
|
||||
}
|
||||
|
||||
void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2)
|
||||
{
|
||||
while (((signed int)sh2->sr >> 12) > 0)
|
||||
{
|
||||
block_desc *bd = HASH_FUNC(sh2->pc_hashtab, sh2->pc);
|
||||
void *block = NULL;
|
||||
|
||||
if (bd != NULL) {
|
||||
if (bd->addr == sh2->pc)
|
||||
block = bd->tcache_ptr;
|
||||
else
|
||||
block = dr_find_block(bd, sh2->pc);
|
||||
}
|
||||
|
||||
if (block == NULL)
|
||||
block = sh2_translate(sh2, bd);
|
||||
|
||||
#ifdef DRC_DEBUG
|
||||
printf("= %csh2 enter %08x %p\n", sh2->is_slave ? 's' : 'm', sh2->pc, block);
|
||||
#endif
|
||||
sh2_drc_entry(sh2, block);
|
||||
}
|
||||
}
|
||||
|
||||
void sh2_execute(SH2 *sh2, int cycles)
|
||||
{
|
||||
unsigned int pc = sh2->pc;
|
||||
int op;
|
||||
sh2->cycles_aim += cycles;
|
||||
cycles = sh2->cycles_aim - sh2->cycles_done;
|
||||
|
||||
op = p32x_sh2_read16(pc);
|
||||
// cycles are kept in SHR_SR unused bits (upper 20)
|
||||
sh2->sr &= 0x3f3;
|
||||
sh2->sr |= cycles << 12;
|
||||
sh2_drc_dispatcher(sh2);
|
||||
|
||||
sh2->cycles_done += cycles - ((signed int)sh2->sr >> 12);
|
||||
}
|
||||
|
||||
|
||||
static int cmn_init_done;
|
||||
|
||||
static int common_init(void)
|
||||
{
|
||||
block_count = 0;
|
||||
block_table = calloc(MAX_BLOCK_COUNT, sizeof(*block_table));
|
||||
if (block_table == NULL)
|
||||
return -1;
|
||||
|
||||
tcache_ptr = tcache;
|
||||
|
||||
cmn_init_done = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int sh2_drc_init(SH2 *sh2)
|
||||
{
|
||||
if (!cmn_init_done) {
|
||||
int ret = common_init();
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
assert(sh2->pc_hashtab == NULL);
|
||||
sh2->pc_hashtab = calloc(sizeof(sh2->pc_hashtab[0]), MAX_HASH_ENTRIES);
|
||||
if (sh2->pc_hashtab == NULL)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
2
cpu/sh2/compiler.h
Normal file
2
cpu/sh2/compiler.h
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
|
||||
int sh2_drc_init(SH2 *sh2);
|
||||
654
cpu/sh2/mame/sh2dasm.c
Normal file
654
cpu/sh2/mame/sh2dasm.c
Normal file
|
|
@ -0,0 +1,654 @@
|
|||
#include <stdio.h>
|
||||
#include "sh2dasm.h"
|
||||
|
||||
typedef int INT32;
|
||||
typedef unsigned int UINT32;
|
||||
typedef unsigned short UINT16;
|
||||
typedef unsigned char UINT8;
|
||||
|
||||
#define DASMFLAG_STEP_OUT 0
|
||||
#define DASMFLAG_STEP_OVER 0
|
||||
#define DASMFLAG_STEP_OVER_EXTRA(x) 0
|
||||
|
||||
#define SIGNX8(x) (((INT32)(x) << 24) >> 24)
|
||||
#define SIGNX12(x) (((INT32)(x) << 20) >> 20)
|
||||
|
||||
#define Rn ((opcode >> 8) & 15)
|
||||
#define Rm ((opcode >> 4) & 15)
|
||||
|
||||
static const char *const regname[16] = {
|
||||
"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
|
||||
"R8", "R9", "R10","R11","R12","R13","R14","SP"
|
||||
};
|
||||
|
||||
static UINT32 op0000(char *buffer, UINT32 pc, UINT16 opcode)
|
||||
{
|
||||
UINT32 flags = 0;
|
||||
switch(opcode & 0x3f)
|
||||
{
|
||||
case 0x02:
|
||||
sprintf(buffer,"STC SR,%s", regname[Rn]);
|
||||
break;
|
||||
case 0x03:
|
||||
sprintf(buffer,"BSRF %s", regname[Rn]);
|
||||
break;
|
||||
case 0x08:
|
||||
sprintf(buffer,"CLRT");
|
||||
break;
|
||||
case 0x09:
|
||||
sprintf(buffer,"NOP");
|
||||
break;
|
||||
case 0x0A:
|
||||
sprintf(buffer,"STS MACH,%s", regname[Rn]);
|
||||
break;
|
||||
case 0x0B:
|
||||
sprintf(buffer,"RTS");
|
||||
flags = DASMFLAG_STEP_OUT;
|
||||
break;
|
||||
case 0x12:
|
||||
sprintf(buffer,"STS GBR,%s", regname[Rn]);
|
||||
break;
|
||||
case 0x18:
|
||||
sprintf(buffer,"SETT");
|
||||
break;
|
||||
case 0x19:
|
||||
sprintf(buffer,"DIV0U");
|
||||
break;
|
||||
case 0x1A:
|
||||
sprintf(buffer,"STS MACL,%s", regname[Rn]);
|
||||
break;
|
||||
case 0x1B:
|
||||
sprintf(buffer,"SLEEP");
|
||||
break;
|
||||
case 0x22:
|
||||
sprintf(buffer,"STC VBR,%s", regname[Rn]);
|
||||
break;
|
||||
case 0x23:
|
||||
sprintf(buffer,"BRAF %s", regname[Rn]);
|
||||
break;
|
||||
case 0x28:
|
||||
sprintf(buffer,"CLRMAC");
|
||||
break;
|
||||
case 0x29:
|
||||
sprintf(buffer,"MOVT %s", regname[Rn]);
|
||||
break;
|
||||
case 0x2A:
|
||||
sprintf(buffer,"STS PR,%s", regname[Rn]);
|
||||
break;
|
||||
case 0x2B:
|
||||
sprintf(buffer,"RTE");
|
||||
flags = DASMFLAG_STEP_OUT;
|
||||
break;
|
||||
default:
|
||||
switch(opcode & 15)
|
||||
{
|
||||
case 0:
|
||||
sprintf(buffer, "?????? $%04X", opcode);
|
||||
break;
|
||||
case 1:
|
||||
sprintf(buffer, "?????? $%04X", opcode);
|
||||
break;
|
||||
case 2:
|
||||
sprintf(buffer, "?????? $%04X", opcode);
|
||||
break;
|
||||
case 3:
|
||||
sprintf(buffer, "?????? $%04X", opcode);
|
||||
break;
|
||||
case 4:
|
||||
sprintf(buffer, "MOV.B %s,@(R0,%s)", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 5:
|
||||
sprintf(buffer, "MOV.W %s,@(R0,%s)", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 6:
|
||||
sprintf(buffer, "MOV.L %s,@(R0,%s)", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 7:
|
||||
sprintf(buffer, "MUL.L %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 8:
|
||||
sprintf(buffer, "?????? $%04X", opcode);
|
||||
break;
|
||||
case 9:
|
||||
sprintf(buffer, "?????? $%04X", opcode);
|
||||
break;
|
||||
case 10:
|
||||
sprintf(buffer, "?????? $%04X", opcode);
|
||||
break;
|
||||
case 11:
|
||||
sprintf(buffer, "?????? $%04X", opcode);
|
||||
break;
|
||||
case 12:
|
||||
sprintf(buffer, "MOV.B @(R0,%s),%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 13:
|
||||
sprintf(buffer, "MOV.W @(R0,%s),%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 14:
|
||||
sprintf(buffer, "MOV.L @(R0,%s),%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 15:
|
||||
sprintf(buffer, "MAC.L @%s+,@%s+", regname[Rn], regname[Rm]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
return flags;
|
||||
}
|
||||
|
||||
static UINT32 op0001(char *buffer, UINT32 pc, UINT16 opcode)
|
||||
{
|
||||
sprintf(buffer, "MOV.L %s,@($%02X,%s)", regname[Rm], (opcode & 15) * 4, regname[Rn]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static UINT32 op0010(char *buffer, UINT32 pc, UINT16 opcode)
|
||||
{
|
||||
switch (opcode & 15)
|
||||
{
|
||||
case 0:
|
||||
sprintf(buffer, "MOV.B %s,@%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 1:
|
||||
sprintf(buffer, "MOV.W %s,@%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 2:
|
||||
sprintf(buffer, "MOV.L %s,@%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 3:
|
||||
sprintf(buffer, "?????? $%04X", opcode);
|
||||
break;
|
||||
case 4:
|
||||
sprintf(buffer, "MOV.B %s,@-%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 5:
|
||||
sprintf(buffer, "MOV.W %s,@-%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 6:
|
||||
sprintf(buffer, "MOV.L %s,@-%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 7:
|
||||
sprintf(buffer, "DIV0S %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 8:
|
||||
sprintf(buffer, "TST %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 9:
|
||||
sprintf(buffer, "AND %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 10:
|
||||
sprintf(buffer, "XOR %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 11:
|
||||
sprintf(buffer, "OR %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 12:
|
||||
sprintf(buffer, "CMP/STR %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 13:
|
||||
sprintf(buffer, "XTRCT %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 14:
|
||||
sprintf(buffer, "MULU.W %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 15:
|
||||
sprintf(buffer, "MULS.W %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static UINT32 op0011(char *buffer, UINT32 pc, UINT16 opcode)
|
||||
{
|
||||
switch (opcode & 15)
|
||||
{
|
||||
case 0:
|
||||
sprintf(buffer, "CMP/EQ %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 1:
|
||||
sprintf(buffer, "?????? %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 2:
|
||||
sprintf(buffer, "CMP/HS %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 3:
|
||||
sprintf(buffer, "CMP/GE %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 4:
|
||||
sprintf(buffer, "DIV1 %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 5:
|
||||
sprintf(buffer, "DMULU.L %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 6:
|
||||
sprintf(buffer, "CMP/HI %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 7:
|
||||
sprintf(buffer, "CMP/GT %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 8:
|
||||
sprintf(buffer, "SUB %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 9:
|
||||
sprintf(buffer, "?????? %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 10:
|
||||
sprintf(buffer, "SUBC %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 11:
|
||||
sprintf(buffer, "SUBV %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 12:
|
||||
sprintf(buffer, "ADD %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 13:
|
||||
sprintf(buffer, "DMULS.L %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 14:
|
||||
sprintf(buffer, "ADDC %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 15:
|
||||
sprintf(buffer, "ADDV %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static UINT32 op0100(char *buffer, UINT32 pc, UINT16 opcode)
|
||||
{
|
||||
UINT32 flags = 0;
|
||||
switch(opcode & 0x3F)
|
||||
{
|
||||
case 0x00:
|
||||
sprintf(buffer, "SHLL %s", regname[Rn]);
|
||||
break;
|
||||
case 0x01:
|
||||
sprintf(buffer, "SHLR %s", regname[Rn]);
|
||||
break;
|
||||
case 0x02:
|
||||
sprintf(buffer, "STS.L MACH,@-%s", regname[Rn]);
|
||||
break;
|
||||
case 0x03:
|
||||
sprintf(buffer, "STC.L SR,@-%s", regname[Rn]);
|
||||
break;
|
||||
case 0x04:
|
||||
sprintf(buffer, "ROTL %s", regname[Rn]);
|
||||
break;
|
||||
case 0x05:
|
||||
sprintf(buffer, "ROTR %s", regname[Rn]);
|
||||
break;
|
||||
case 0x06:
|
||||
sprintf(buffer, "LDS.L @%s+,MACH", regname[Rn]);
|
||||
break;
|
||||
case 0x07:
|
||||
sprintf(buffer, "LDC.L @%s+,SR", regname[Rn]);
|
||||
break;
|
||||
case 0x08:
|
||||
sprintf(buffer, "SHLL2 %s", regname[Rn]);
|
||||
break;
|
||||
case 0x09:
|
||||
sprintf(buffer, "SHLR2 %s", regname[Rn]);
|
||||
break;
|
||||
case 0x0a:
|
||||
sprintf(buffer, "LDS %s,MACH", regname[Rn]);
|
||||
break;
|
||||
case 0x0b:
|
||||
sprintf(buffer, "JSR %s", regname[Rn]);
|
||||
flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1);
|
||||
break;
|
||||
case 0x0e:
|
||||
sprintf(buffer, "LDC %s,SR", regname[Rn]);
|
||||
break;
|
||||
case 0x10:
|
||||
sprintf(buffer, "DT %s", regname[Rn]);
|
||||
break;
|
||||
case 0x11:
|
||||
sprintf(buffer, "CMP/PZ %s", regname[Rn]);
|
||||
break;
|
||||
case 0x12:
|
||||
sprintf(buffer, "STS.L MACL,@-%s", regname[Rn]);
|
||||
break;
|
||||
case 0x13:
|
||||
sprintf(buffer, "STC.L GBR,@-%s", regname[Rn]);
|
||||
break;
|
||||
case 0x15:
|
||||
sprintf(buffer, "CMP/PL %s", regname[Rn]);
|
||||
break;
|
||||
case 0x16:
|
||||
sprintf(buffer, "LDS.L @%s+,MACL", regname[Rn]);
|
||||
break;
|
||||
case 0x17:
|
||||
sprintf(buffer, "LDC.L @%s+,GBR", regname[Rn]);
|
||||
break;
|
||||
case 0x18:
|
||||
sprintf(buffer, "SHLL8 %s", regname[Rn]);
|
||||
break;
|
||||
case 0x19:
|
||||
sprintf(buffer, "SHLR8 %s", regname[Rn]);
|
||||
break;
|
||||
case 0x1a:
|
||||
sprintf(buffer, "LDS %s,MACL", regname[Rn]);
|
||||
break;
|
||||
case 0x1b:
|
||||
sprintf(buffer, "TAS %s", regname[Rn]);
|
||||
break;
|
||||
case 0x1e:
|
||||
sprintf(buffer, "LDC %s,GBR", regname[Rn]);
|
||||
break;
|
||||
case 0x20:
|
||||
sprintf(buffer, "SHAL %s", regname[Rn]);
|
||||
break;
|
||||
case 0x21:
|
||||
sprintf(buffer, "SHAR %s", regname[Rn]);
|
||||
break;
|
||||
case 0x22:
|
||||
sprintf(buffer, "STS.L PR,@-%s", regname[Rn]);
|
||||
break;
|
||||
case 0x23:
|
||||
sprintf(buffer, "STC.L VBR,@-%s", regname[Rn]);
|
||||
break;
|
||||
case 0x24:
|
||||
sprintf(buffer, "ROTCL %s", regname[Rn]);
|
||||
break;
|
||||
case 0x25:
|
||||
sprintf(buffer, "ROTCR %s", regname[Rn]);
|
||||
break;
|
||||
case 0x26:
|
||||
sprintf(buffer, "LDS.L @%s+,PR", regname[Rn]);
|
||||
break;
|
||||
case 0x27:
|
||||
sprintf(buffer, "LDC.L @%s+,VBR", regname[Rn]);
|
||||
break;
|
||||
case 0x28:
|
||||
sprintf(buffer, "SHLL16 %s", regname[Rn]);
|
||||
break;
|
||||
case 0x29:
|
||||
sprintf(buffer, "SHLR16 %s", regname[Rn]);
|
||||
break;
|
||||
case 0x2a:
|
||||
sprintf(buffer, "LDS %s,PR", regname[Rn]);
|
||||
break;
|
||||
case 0x2b:
|
||||
sprintf(buffer, "JMP %s", regname[Rn]);
|
||||
break;
|
||||
case 0x2e:
|
||||
sprintf(buffer, "LDC %s,VBR", regname[Rn]);
|
||||
break;
|
||||
default:
|
||||
if ((opcode & 15) == 15)
|
||||
sprintf(buffer, "MAC.W @%s+,@%s+", regname[Rm], regname[Rn]);
|
||||
else
|
||||
sprintf(buffer, "?????? $%04X", opcode);
|
||||
}
|
||||
return flags;
|
||||
}
|
||||
|
||||
static UINT32 op0101(char *buffer, UINT32 pc, UINT16 opcode)
|
||||
{
|
||||
sprintf(buffer, "MOV.L @($%02X,%s),%s", (opcode & 15) * 4, regname[Rm], regname[Rn]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static UINT32 op0110(char *buffer, UINT32 pc, UINT16 opcode)
|
||||
|
||||
{
|
||||
switch(opcode & 0xF)
|
||||
{
|
||||
case 0x00:
|
||||
sprintf(buffer, "MOV.B @%s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 0x01:
|
||||
sprintf(buffer, "MOV.W @%s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 0x02:
|
||||
sprintf(buffer, "MOV.L @%s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 0x03:
|
||||
sprintf(buffer, "MOV %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 0x04:
|
||||
sprintf(buffer, "MOV.B @%s+,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 0x05:
|
||||
sprintf(buffer, "MOV.W @%s+,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 0x06:
|
||||
sprintf(buffer, "MOV.L @%s+,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 0x07:
|
||||
sprintf(buffer, "NOT %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 0x08:
|
||||
sprintf(buffer, "SWAP.B %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 0x09:
|
||||
sprintf(buffer, "SWAP.W %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 0x0a:
|
||||
sprintf(buffer, "NEGC %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 0x0b:
|
||||
sprintf(buffer, "NEG %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 0x0c:
|
||||
sprintf(buffer, "EXTU.B %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 0x0d:
|
||||
sprintf(buffer, "EXTU.W %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 0x0e:
|
||||
sprintf(buffer, "EXTS.B %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
case 0x0f:
|
||||
sprintf(buffer, "EXTS.W %s,%s", regname[Rm], regname[Rn]);
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static UINT32 op0111(char *buffer, UINT32 pc, UINT16 opcode)
|
||||
{
|
||||
sprintf(buffer, "ADD #$%02X,%s", opcode & 0xff, regname[Rn]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static UINT32 op1000(char *buffer, UINT32 pc, UINT16 opcode)
|
||||
{
|
||||
switch((opcode >> 8) & 15)
|
||||
{
|
||||
case 0:
|
||||
sprintf(buffer, "MOV.B R0,@($%02X,%s)", (opcode & 15), regname[Rm]);
|
||||
break;
|
||||
case 1:
|
||||
sprintf(buffer, "MOV.W R0,@($%02X,%s)", (opcode & 15) * 2, regname[Rm]);
|
||||
break;
|
||||
case 4:
|
||||
sprintf(buffer, "MOV.B @($%02X,%s),R0", (opcode & 15), regname[Rm]);
|
||||
break;
|
||||
case 5:
|
||||
sprintf(buffer, "MOV.W @($%02X,%s),R0", (opcode & 15), regname[Rm]);
|
||||
break;
|
||||
case 8:
|
||||
sprintf(buffer, "CMP/EQ #$%02X,R0", (opcode & 0xff));
|
||||
break;
|
||||
case 9:
|
||||
sprintf(buffer, "BT $%08X", pc + SIGNX8(opcode & 0xff) * 2 + 2);
|
||||
break;
|
||||
case 11:
|
||||
sprintf(buffer, "BF $%08X", pc + SIGNX8(opcode & 0xff) * 2 + 2);
|
||||
break;
|
||||
case 13:
|
||||
sprintf(buffer, "BTS $%08X", pc + SIGNX8(opcode & 0xff) * 2 + 2);
|
||||
break;
|
||||
case 15:
|
||||
sprintf(buffer, "BFS $%08X", pc + SIGNX8(opcode & 0xff) * 2 + 2);
|
||||
break;
|
||||
default :
|
||||
sprintf(buffer, "invalid $%04X", opcode);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static UINT32 op1001(char *buffer, UINT32 pc, UINT16 opcode)
|
||||
{
|
||||
sprintf(buffer, "MOV.W @($%04X,PC),%s", (opcode & 0xff) * 2, regname[Rn]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static UINT32 op1010(char *buffer, UINT32 pc, UINT16 opcode)
|
||||
{
|
||||
sprintf(buffer, "BRA $%08X", SIGNX12(opcode & 0xfff) * 2 + pc + 2);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static UINT32 op1011(char *buffer, UINT32 pc, UINT16 opcode)
|
||||
{
|
||||
sprintf(buffer, "BSR $%08X", SIGNX12(opcode & 0xfff) * 2 + pc + 2);
|
||||
return DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1);
|
||||
}
|
||||
|
||||
static UINT32 op1100(char *buffer, UINT32 pc, UINT16 opcode)
|
||||
{
|
||||
UINT32 flags = 0;
|
||||
switch((opcode >> 8) & 15)
|
||||
{
|
||||
case 0:
|
||||
sprintf(buffer, "MOV.B R0,@($%02X,GBR)", opcode & 0xff);
|
||||
break;
|
||||
case 1:
|
||||
sprintf(buffer, "MOV.W R0,@($%04X,GBR)", (opcode & 0xff) * 2);
|
||||
break;
|
||||
case 2:
|
||||
sprintf(buffer, "MOV.L R0,@($%04X,GBR)", (opcode & 0xff) * 4);
|
||||
break;
|
||||
case 3:
|
||||
sprintf(buffer, "TRAPA #$%02X", opcode & 0xff);
|
||||
flags = DASMFLAG_STEP_OVER;
|
||||
break;
|
||||
case 4:
|
||||
sprintf(buffer, "MOV.B @($%02X,GBR),R0", opcode & 0xff);
|
||||
break;
|
||||
case 5:
|
||||
sprintf(buffer, "MOV.W @($%04X,GBR),R0", (opcode & 0xff) * 2);
|
||||
break;
|
||||
case 6:
|
||||
sprintf(buffer, "MOV.L @($%04X,GBR),R0", (opcode & 0xff) * 4);
|
||||
break;
|
||||
case 7:
|
||||
sprintf(buffer, "MOVA @($%04X,PC),R0", (opcode & 0xff) * 4);
|
||||
break;
|
||||
case 8:
|
||||
sprintf(buffer, "TST #$%02X,R0", opcode & 0xff);
|
||||
break;
|
||||
case 9:
|
||||
sprintf(buffer, "AND #$%02X,R0", opcode & 0xff);
|
||||
break;
|
||||
case 10:
|
||||
sprintf(buffer, "XOR #$%02X,R0", opcode & 0xff);
|
||||
break;
|
||||
case 11:
|
||||
sprintf(buffer, "OR #$%02X,R0", opcode & 0xff);
|
||||
break;
|
||||
case 12:
|
||||
sprintf(buffer, "TST.B #$%02X,@(R0,GBR)", opcode & 0xff);
|
||||
break;
|
||||
case 13:
|
||||
sprintf(buffer, "AND.B #$%02X,@(R0,GBR)", opcode & 0xff);
|
||||
break;
|
||||
case 14:
|
||||
sprintf(buffer, "XOR.B #$%02X,@(R0,GBR)", opcode & 0xff);
|
||||
break;
|
||||
case 15:
|
||||
sprintf(buffer, "OR.B #$%02X,@(R0,GBR)", opcode & 0xff);
|
||||
break;
|
||||
}
|
||||
return flags;
|
||||
}
|
||||
|
||||
static UINT32 op1101(char *buffer, UINT32 pc, UINT16 opcode)
|
||||
{
|
||||
sprintf(buffer, "MOV.L @($%02X,PC),%s ; #$%06x", (opcode * 4) & 0x3ff, regname[Rn],
|
||||
(pc + ((opcode * 4) & 0x3ff) + 2) & ~3);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static UINT32 op1110(char *buffer, UINT32 pc, UINT16 opcode)
|
||||
{
|
||||
sprintf(buffer, "MOV #$%02X,%s", (opcode & 0xff), regname[Rn]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static UINT32 op1111(char *buffer, UINT32 pc, UINT16 opcode)
|
||||
{
|
||||
sprintf(buffer, "unknown $%04X", opcode);
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned DasmSH2(char *buffer, unsigned pc, UINT16 opcode)
|
||||
{
|
||||
UINT32 flags;
|
||||
|
||||
pc += 2;
|
||||
|
||||
switch((opcode >> 12) & 15)
|
||||
{
|
||||
case 0: flags = op0000(buffer,pc,opcode); break;
|
||||
case 1: flags = op0001(buffer,pc,opcode); break;
|
||||
case 2: flags = op0010(buffer,pc,opcode); break;
|
||||
case 3: flags = op0011(buffer,pc,opcode); break;
|
||||
case 4: flags = op0100(buffer,pc,opcode); break;
|
||||
case 5: flags = op0101(buffer,pc,opcode); break;
|
||||
case 6: flags = op0110(buffer,pc,opcode); break;
|
||||
case 7: flags = op0111(buffer,pc,opcode); break;
|
||||
case 8: flags = op1000(buffer,pc,opcode); break;
|
||||
case 9: flags = op1001(buffer,pc,opcode); break;
|
||||
case 10: flags = op1010(buffer,pc,opcode); break;
|
||||
case 11: flags = op1011(buffer,pc,opcode); break;
|
||||
case 12: flags = op1100(buffer,pc,opcode); break;
|
||||
case 13: flags = op1101(buffer,pc,opcode); break;
|
||||
case 14: flags = op1110(buffer,pc,opcode); break;
|
||||
default: flags = op1111(buffer,pc,opcode); break;
|
||||
}
|
||||
return 0;//2 | flags | DASMFLAG_SUPPORTED;
|
||||
}
|
||||
|
||||
#if 0
|
||||
|
||||
#define swab32(x) (((x) << 24) | (((x) << 8) & 0xff0000) | (((x) >> 8) & 0xff00) | ((x) >> 24))
|
||||
#define swab16(x) ((((x) << 8) & 0xff00) | (((x) >> 8) & 0x00ff))
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
unsigned short op;
|
||||
char buff[256];
|
||||
unsigned pc;
|
||||
FILE *f;
|
||||
int ret;
|
||||
|
||||
if (argv[1] == NULL) {
|
||||
printf("usage\n%s <file>\n", argv[0]);
|
||||
return 1;
|
||||
}
|
||||
|
||||
f = fopen(argv[1], "rb");
|
||||
if (f == NULL) {
|
||||
fprintf(stderr, "can't open %s\n", argv[1]);
|
||||
return 1;
|
||||
}
|
||||
|
||||
for (pc = 0x140;; pc += 2)
|
||||
{
|
||||
fseek(f, pc, SEEK_SET);
|
||||
|
||||
ret = fread(&op, 1, sizeof(op), f);
|
||||
if (ret != sizeof(op))
|
||||
break;
|
||||
|
||||
DasmSH2(buff, pc, swab16(op));
|
||||
printf("%06x %04x %s\n", pc, swab16(op), buff);
|
||||
}
|
||||
|
||||
fclose(f);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
1
cpu/sh2/mame/sh2dasm.h
Normal file
1
cpu/sh2/mame/sh2dasm.h
Normal file
|
|
@ -0,0 +1 @@
|
|||
unsigned DasmSH2(char *buffer, unsigned pc, unsigned short opcode);
|
||||
|
|
@ -33,6 +33,8 @@ typedef unsigned char UINT8;
|
|||
|
||||
#include "sh2.c"
|
||||
|
||||
#ifndef DRC_TMP
|
||||
|
||||
void sh2_execute(SH2 *sh2_, int cycles)
|
||||
{
|
||||
sh2 = sh2_;
|
||||
|
|
@ -96,3 +98,43 @@ void sh2_execute(SH2 *sh2_, int cycles)
|
|||
sh2->cycles_done += cycles - sh2->icount;
|
||||
}
|
||||
|
||||
#else // DRC_TMP
|
||||
|
||||
// tmp
|
||||
void __attribute__((regparm(2))) sh2_do_op(SH2 *sh2_, int opcode)
|
||||
{
|
||||
sh2 = sh2_;
|
||||
sh2->pc += 2;
|
||||
|
||||
switch (opcode & ( 15 << 12))
|
||||
{
|
||||
case 0<<12: op0000(opcode); break;
|
||||
case 1<<12: op0001(opcode); break;
|
||||
case 2<<12: op0010(opcode); break;
|
||||
case 3<<12: op0011(opcode); break;
|
||||
case 4<<12: op0100(opcode); break;
|
||||
case 5<<12: op0101(opcode); break;
|
||||
case 6<<12: op0110(opcode); break;
|
||||
case 7<<12: op0111(opcode); break;
|
||||
case 8<<12: op1000(opcode); break;
|
||||
case 9<<12: op1001(opcode); break;
|
||||
case 10<<12: op1010(opcode); break;
|
||||
case 11<<12: op1011(opcode); break;
|
||||
case 12<<12: op1100(opcode); break;
|
||||
case 13<<12: op1101(opcode); break;
|
||||
case 14<<12: op1110(opcode); break;
|
||||
default: op1111(opcode); break;
|
||||
}
|
||||
|
||||
if (sh2->test_irq)
|
||||
{
|
||||
if (sh2->pending_irl > sh2->pending_int_irq)
|
||||
sh2_irl_irq(sh2, sh2->pending_irl);
|
||||
else
|
||||
sh2_internal_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector);
|
||||
sh2->test_irq = 0;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,19 @@
|
|||
#include <string.h>
|
||||
#include "sh2.h"
|
||||
#include "compiler.h"
|
||||
|
||||
#define I 0xf0
|
||||
|
||||
void sh2_init(SH2 *sh2, int is_slave)
|
||||
int sh2_init(SH2 *sh2, int is_slave)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
memset(sh2, 0, sizeof(*sh2));
|
||||
sh2->is_slave = is_slave;
|
||||
#ifdef DRC_SH2
|
||||
ret = sh2_drc_init(sh2);
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
void sh2_reset(SH2 *sh2)
|
||||
|
|
|
|||
|
|
@ -13,32 +13,37 @@ void p32x_sh2_write32(unsigned int a, unsigned int d, int id);
|
|||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int r[16];
|
||||
unsigned int r[16]; // 00
|
||||
unsigned int pc; // 40
|
||||
unsigned int ppc;
|
||||
unsigned int pc;
|
||||
unsigned int pr;
|
||||
unsigned int sr;
|
||||
unsigned int gbr, vbr;
|
||||
unsigned int mach, macl;
|
||||
unsigned int gbr, vbr; // 50
|
||||
unsigned int mach, macl; // 58
|
||||
|
||||
// interpreter stuff
|
||||
int icount; // 60 cycles left in current timeslice
|
||||
unsigned int ea;
|
||||
unsigned int delay;
|
||||
unsigned int test_irq;
|
||||
|
||||
// drc stuff
|
||||
void **pc_hashtab; // 70
|
||||
|
||||
// common
|
||||
int pending_irl;
|
||||
int pending_int_irq; // internal irq
|
||||
int pending_int_vector;
|
||||
void (*irq_callback)(int id, int level);
|
||||
int is_slave;
|
||||
|
||||
int icount; // cycles left in current timeslice
|
||||
unsigned int cycles_aim; // subtract sh2_icount to get global counter
|
||||
unsigned int cycles_done;
|
||||
} SH2;
|
||||
|
||||
extern SH2 *sh2; // active sh2
|
||||
|
||||
void sh2_init(SH2 *sh2, int is_slave);
|
||||
int sh2_init(SH2 *sh2, int is_slave);
|
||||
void sh2_reset(SH2 *sh2);
|
||||
void sh2_irl_irq(SH2 *sh2, int level);
|
||||
void sh2_internal_irq(SH2 *sh2, int level, int vector);
|
||||
|
|
|
|||
16
cpu/sh2/stub_x86.asm
Normal file
16
cpu/sh2/stub_x86.asm
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
section .text
|
||||
|
||||
global sh2_drc_entry ; SH2 *sh2, void *block
|
||||
|
||||
sh2_drc_entry:
|
||||
push ebp
|
||||
mov ebp, [esp+4+4] ; context
|
||||
mov eax, [esp+4+8]
|
||||
jmp eax
|
||||
|
||||
global sh2_drc_exit
|
||||
|
||||
sh2_drc_exit:
|
||||
pop ebp
|
||||
ret
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue