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sh2 drc, fixes for cache handling on arm and mips cpus

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This commit is contained in:
kub 2020-10-27 18:05:49 +01:00
parent e7faa8e4e1
commit 69c22514b0
3 changed files with 7 additions and 8 deletions
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2
cpu/drc/emit_arm.c
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@ -1247,7 +1247,7 @@ static inline void emith_pool_adjust(int tcache_offs, int move_offs)
} while (0)
#define host_instructions_updated(base, end, force) \
do { if (force) __builtin___clear_cache(base, end); } while (0)
do { if (force) emith_update_add(base, end); } while (0)
#define host_arg2reg(rd, arg) \
rd = arg

9
cpu/drc/emit_mips.c
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@ -1573,11 +1573,10 @@ static NOINLINE void host_instructions_updated(void *base, void *end, int force)
{
int step, tmp;
asm volatile(
" bal 0f;" // needed to allow for jr.hb
" b 3f;"
"0: rdhwr %2, $1;"
" beqz %2, 2f;"
" rdhwr %2, $1;"
" bal 0f;" // needed to allow for jr.hb:
"0: addiu $ra, $ra, 3f-0b;" // set ra to insn after jr.hb
" beqz %2, 3f;"
"1: synci 0(%0);"
" sltu %3, %0, %1;"