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sh2 drc, fixes for cache handling on arm and mips cpus

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This commit is contained in:
kub 2020-10-27 18:05:49 +01:00
parent e7faa8e4e1
commit 69c22514b0
3 changed files with 7 additions and 8 deletions
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2
cpu/drc/emit_arm.c
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@ -1247,7 +1247,7 @@ static inline void emith_pool_adjust(int tcache_offs, int move_offs)
} while (0)
#define host_instructions_updated(base, end, force) \
do { if (force) __builtin___clear_cache(base, end); } while (0)
do { if (force) emith_update_add(base, end); } while (0)
#define host_arg2reg(rd, arg) \
rd = arg