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core, add TH pad pin latency (load state regression)
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1 changed files with 6 additions and 4 deletions
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@ -314,7 +314,7 @@ static port_read_func *port_readers[3] = {
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read_nothing
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read_nothing
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};
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};
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static int padTHLatency[3];
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static int padTHLatency[3]; // TODO this should be in the save file structures
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static NOINLINE u32 port_read(int i)
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static NOINLINE u32 port_read(int i)
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{
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{
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@ -329,6 +329,8 @@ static NOINLINE u32 port_read(int i)
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// Decap Attack reportedly doesn't work on Nomad but works on must
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// Decap Attack reportedly doesn't work on Nomad but works on must
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// other MD revisions (different pull-up strength?).
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// other MD revisions (different pull-up strength?).
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u32 mask = 0x3f;
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u32 mask = 0x3f;
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if (CYCLES_GE(padTHLatency[i], SekCyclesDone()+100))
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padTHLatency[i] = SekCyclesDone(); // kludge to cope with cycle wrap
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if (CYCLES_GE(SekCyclesDone(), padTHLatency[i])) {
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if (CYCLES_GE(SekCyclesDone(), padTHLatency[i])) {
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mask |= 0x40;
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mask |= 0x40;
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padTHLatency[i] = SekCyclesDone();
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padTHLatency[i] = SekCyclesDone();
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@ -413,10 +415,10 @@ NOINLINE void io_ports_write(u32 a, u32 d)
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// after switching TH to input there's a latency before the pullup value is
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// after switching TH to input there's a latency before the pullup value is
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// read back as input (see Decap Attack, not in Samurai Showdown, 32x WWF Raw)
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// read back as input (see Decap Attack, not in Samurai Showdown, 32x WWF Raw)
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if (a >= 4 && a <= 5) {
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if (4 <= a && a <= 5) {
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padTHLatency[a - 4] = SekCyclesDone(); // if output, effective immediately
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if ((PicoMem.ioports[a] & 0x40) && !(d & 0x40))
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if ((PicoMem.ioports[a] & 0x40) && !(d & 0x40))
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padTHLatency[a - 4] += 25; // latency after switching to input
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// latency after switching to input
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padTHLatency[a - 4] = SekCyclesDone() + 25;
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}
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}
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// certain IO ports can be used as RAM
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// certain IO ports can be used as RAM
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