mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
fix ym2612 asm, rework EG
this should be split, but I'm lazy EG saves ~900 bytes
This commit is contained in:
notaz
parent
e0bcb7a90d
commit
6d28fb5023
3 changed files with 117 additions and 157 deletions
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@ -739,83 +739,57 @@ INLINE int advance_lfo(int lfo_ampm, UINT32 lfo_cnt_old, UINT32 lfo_cnt)
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return lfo_ampm;
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}
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#define EG_INC_VAL() \
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((1 << ((pack >> ((eg_cnt>>shift)&7)*3)&7)) >> 1)
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INLINE UINT32 update_eg_phase(FM_SLOT *SLOT, UINT32 eg_cnt)
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INLINE void update_eg_phase(UINT16 *vol_out, FM_SLOT *SLOT, UINT32 eg_cnt)
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{
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INT32 volume = SLOT->volume;
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UINT32 pack = SLOT->eg_pack[SLOT->state - 1];
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UINT32 shift = pack >> 24;
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INT32 eg_inc_val;
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switch(SLOT->state)
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if (eg_cnt & ((1 << shift) - 1))
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return;
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eg_inc_val = pack >> ((eg_cnt >> shift) & 7) * 3;
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eg_inc_val = (1 << (eg_inc_val & 7)) >> 1;
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switch (SLOT->state)
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{
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case EG_ATT: /* attack phase */
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{
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UINT32 pack = SLOT->eg_pack_ar;
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UINT32 shift = pack>>24;
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if ( !(eg_cnt & ((1<<shift)-1) ) )
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{
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volume += ( ~volume * EG_INC_VAL() ) >>4;
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if (volume <= MIN_ATT_INDEX)
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volume += ( ~volume * eg_inc_val ) >> 4;
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if ( volume <= MIN_ATT_INDEX )
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{
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volume = MIN_ATT_INDEX;
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SLOT->state = EG_DEC;
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}
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}
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break;
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}
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case EG_DEC: /* decay phase */
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{
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UINT32 pack = SLOT->eg_pack_d1r;
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UINT32 shift = pack>>24;
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if ( !(eg_cnt & ((1<<shift)-1) ) )
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{
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volume += EG_INC_VAL();
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volume += eg_inc_val;
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if ( volume >= (INT32) SLOT->sl )
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SLOT->state = EG_SUS;
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}
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break;
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}
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case EG_SUS: /* sustain phase */
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{
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UINT32 pack = SLOT->eg_pack_d2r;
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UINT32 shift = pack>>24;
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if ( !(eg_cnt & ((1<<shift)-1) ) )
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{
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volume += EG_INC_VAL();
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volume += eg_inc_val;
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if ( volume >= MAX_ATT_INDEX )
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{
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volume = MAX_ATT_INDEX;
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/* do not change SLOT->state (verified on real chip) */
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}
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}
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break;
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}
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case EG_REL: /* release phase */
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{
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UINT32 pack = SLOT->eg_pack_rr;
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UINT32 shift = pack>>24;
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if ( !(eg_cnt & ((1<<shift)-1) ) )
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{
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volume += EG_INC_VAL();
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volume += eg_inc_val;
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if ( volume >= MAX_ATT_INDEX )
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{
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volume = MAX_ATT_INDEX;
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SLOT->state = EG_OFF;
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}
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}
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break;
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}
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}
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SLOT->volume = volume;
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return SLOT->tl + ((UINT32)volume); /* tl is 7bit<<3, volume 0-1023 (0-2039 total) */
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*vol_out = SLOT->tl + volume; /* tl is 7bit<<3, volume 0-1023 (0-2039 total) */
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}
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#endif
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@ -873,10 +847,10 @@ static void chan_render_loop(chan_rend_context *ct, int *buffer, int length)
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ct->eg_timer -= EG_TIMER_OVERFLOW;
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ct->eg_cnt++;
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if (ct->CH->SLOT[SLOT1].state != EG_OFF) ct->vol_out1 = update_eg_phase(&ct->CH->SLOT[SLOT1], ct->eg_cnt);
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if (ct->CH->SLOT[SLOT2].state != EG_OFF) ct->vol_out2 = update_eg_phase(&ct->CH->SLOT[SLOT2], ct->eg_cnt);
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if (ct->CH->SLOT[SLOT3].state != EG_OFF) ct->vol_out3 = update_eg_phase(&ct->CH->SLOT[SLOT3], ct->eg_cnt);
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if (ct->CH->SLOT[SLOT4].state != EG_OFF) ct->vol_out4 = update_eg_phase(&ct->CH->SLOT[SLOT4], ct->eg_cnt);
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if (ct->CH->SLOT[SLOT1].state != EG_OFF) update_eg_phase(&ct->vol_out1, &ct->CH->SLOT[SLOT1], ct->eg_cnt);
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if (ct->CH->SLOT[SLOT2].state != EG_OFF) update_eg_phase(&ct->vol_out2, &ct->CH->SLOT[SLOT2], ct->eg_cnt);
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if (ct->CH->SLOT[SLOT3].state != EG_OFF) update_eg_phase(&ct->vol_out3, &ct->CH->SLOT[SLOT3], ct->eg_cnt);
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if (ct->CH->SLOT[SLOT4].state != EG_OFF) update_eg_phase(&ct->vol_out4, &ct->CH->SLOT[SLOT4], ct->eg_cnt);
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}
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if (ct->pack & 4) continue; /* output disabled */
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@ -1071,7 +1045,7 @@ static void chan_render_loop(chan_rend_context *ct, int *buffer, int length)
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} else {
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buffer[scounter] += smp;
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}
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ct->algo = 8; // algo is only used in asm, here only bit3 is used
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ct->algo |= 8;
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}
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/* update phase counters AFTER output calculations */
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@ -43,10 +43,16 @@ typedef struct
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INT16 volume; /* #0x1a envelope counter | need_save */
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UINT32 sl; /* #0x1c sustain level:sl_table[SL] */
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UINT32 eg_pack_ar; /* #0x20 (attack state) */
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UINT32 eg_pack_d1r; /* #0x24 (decay state) */
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UINT32 eg_pack_d2r; /* #0x28 (sustain state) */
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UINT32 eg_pack_rr; /* #0x2c (release state) */
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/* asm relies on this order: */
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union {
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struct {
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UINT32 eg_pack_rr; /* #0x20 1 (release state) */
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UINT32 eg_pack_d2r; /* #0x24 2 (sustain state) */
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UINT32 eg_pack_d1r; /* #0x28 3 (decay state) */
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UINT32 eg_pack_ar; /* #0x2c 4 (attack state) */
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};
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UINT32 eg_pack[4];
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};
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} FM_SLOT;
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@ -30,103 +30,73 @@
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.equiv EG_TIMER_OVERFLOW, (3*(1<<EG_SH)) @ envelope generator timer overflows every 3 samples (on real chip)
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.equiv LFO_SH, 25 /* 7.25 fixed point (LFO calculations) */
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.equiv ENV_QUIET, (2*13*256/8)/2
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.equiv ENV_QUIET, (2*13*256/8)
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.text
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.align 2
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@ r5=slot, r1=eg_cnt, trashes: r0,r2,r3
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@ writes output to routp, but only if vol_out changes
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.macro update_eg_phase_slot slot
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ldrb r2, [r5,#0x17] @ state
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mov r3, #1 @ 1ci
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cmp r2, #1
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blt 5f @ EG_OFF
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beq 3f @ EG_REL
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cmp r2, #3
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blt 2f @ EG_SUS
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beq 1f @ EG_DEC
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add r3, r5, #0x1c
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tst r2, r2
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beq 0f @ EG_OFF
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0: @ EG_ATT
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ldr r2, [r5,#0x20] @ eg_pack_ar (1ci)
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mov r0, r2, lsr #24
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ldr r2, [r3, r2, lsl #2] @ pack
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mov r3, #1
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mov r0, r2, lsr #24 @ shift
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mov r3, r3, lsl r0
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sub r3, r3, #1
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tst r1, r3
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bne 5f @ do smth for tl problem (set on init?)
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bne 0f @ no volume change
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mov r3, r1, lsr r0
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ldrh r0, [r5,#0x1a] @ volume, unsigned (0-1023)
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and r3, r3, #7
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add r3, r3, r3, lsl #1
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mov r3, r2, lsr r3
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and r3, r3, #7 @ shift for eg_inc calculation
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mvn r2, r0
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and r3, r3, #7 @ eg_inc_val shift, may be 0
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ldrb r2, [r5,#0x17] @ state
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ldrh r0, [r5,#0x1a] @ volume, unsigned (0-1023)
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cmp r2, #4 @ EG_ATT
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beq 4f
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cmp r2, #2
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mov r2, #1
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mov r2, r2, lsl r3
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add r0, r0, r2, asr #5
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mov r2, r2, lsr #1 @ eg_inc_val
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add r0, r0, r2
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blt 1f @ EG_REL
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beq 2f @ EG_SUS
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3: @ EG_DEC
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ldr r2, [r5,#0x1c] @ sl (can be 16bit?)
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mov r3, #EG_SUS
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cmp r0, r2 @ if ( volume >= (INT32) SLOT->sl )
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strgeb r3, [r5,#0x17] @ state
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b 10f
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4: @ EG_ATT
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subs r3, r3, #1 @ eg_inc_val_shift - 1
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mov r2, #0
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mvnpl r2, r0
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mov r2, r2, lsl r3
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add r0, r0, r2, asr #4
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cmp r0, #0 @ if (volume <= MIN_ATT_INDEX)
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movle r3, #EG_DEC
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strleb r3, [r5,#0x17] @ state
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movle r0, #0
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b 4f
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1: @ EG_DEC
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ldr r2, [r5,#0x24] @ eg_pack_d1r (1ci)
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mov r0, r2, lsr #24
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mov r3, r3, lsl r0
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sub r3, r3, #1
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tst r1, r3
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bne 5f @ do smth for tl problem (set on init?)
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mov r3, r1, lsr r0
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ldrh r0, [r5,#0x1a] @ volume
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and r3, r3, #7
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add r3, r3, r3, lsl #1
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mov r3, r2, lsr r3
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and r3, r3, #7 @ shift for eg_inc calculation
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mov r2, #1
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mov r3, r2, lsl r3
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ldr r2, [r5,#0x1c] @ sl (can be 16bit?)
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add r0, r0, r3, asr #1
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cmp r0, r2 @ if ( volume >= (INT32) SLOT->sl )
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movge r3, #EG_SUS
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strgeb r3, [r5,#0x17] @ state
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b 4f
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b 10f
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2: @ EG_SUS
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ldr r2, [r5,#0x28] @ eg_pack_d2r (1ci)
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mov r0, r2, lsr #24
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mov r3, r3, lsl r0
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sub r3, r3, #1
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tst r1, r3
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bne 5f @ do smth for tl problem (set on init?)
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mov r3, r1, lsr r0
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ldrh r0, [r5,#0x1a] @ volume
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and r3, r3, #7
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add r3, r3, r3, lsl #1
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mov r3, r2, lsr r3
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and r3, r3, #7 @ shift for eg_inc calculation
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mov r2, #1
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mov r3, r2, lsl r3
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add r0, r0, r3, asr #1
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mov r2, #1024
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sub r2, r2, #1 @ r2 = MAX_ATT_INDEX
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cmp r0, r2 @ if ( volume >= MAX_ATT_INDEX )
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movge r0, r2
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b 4f
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b 10f
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3: @ EG_REL
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ldr r2, [r5,#0x2c] @ eg_pack_rr (1ci)
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mov r0, r2, lsr #24
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mov r3, r3, lsl r0
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sub r3, r3, #1
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tst r1, r3
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bne 5f @ do smth for tl problem (set on init?)
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mov r3, r1, lsr r0
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ldrh r0, [r5,#0x1a] @ volume
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and r3, r3, #7
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add r3, r3, r3, lsl #1
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mov r3, r2, lsr r3
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and r3, r3, #7 @ shift for eg_inc calculation
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mov r2, #1
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mov r3, r2, lsl r3
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add r0, r0, r3, asr #1
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1: @ EG_REL
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mov r2, #1024
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sub r2, r2, #1 @ r2 = MAX_ATT_INDEX
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cmp r0, r2 @ if ( volume >= MAX_ATT_INDEX )
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@ -134,7 +104,7 @@
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movge r3, #EG_OFF
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strgeb r3, [r5,#0x17] @ state
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4:
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10: @ finish
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ldrh r3, [r5,#0x18] @ tl
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strh r0, [r5,#0x1a] @ volume
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.if \slot == SLOT1
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@ -157,7 +127,7 @@
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orr r7, r0, r7, lsr #16
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.endif
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5:
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0: @ EG_OFF
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.endm
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@ -187,28 +157,30 @@
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tstne r12, #(1<<(\slot+8))
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.if \slot == SLOT1
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mov r1, r6, lsl #16
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mov r1, r1, lsr #17
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mov r1, r1, lsr #16
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.elseif \slot == SLOT2
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mov r1, r6, lsr #17
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mov r1, r6, lsr #16
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.elseif \slot == SLOT3
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mov r1, r7, lsl #16
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mov r1, r1, lsr #17
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mov r1, r1, lsr #16
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.elseif \slot == SLOT4
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mov r1, r7, lsr #17
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mov r1, r7, lsr #16
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.endif
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andne r2, r12, #0xc0
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movne r2, r2, lsr #6
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addne r2, r2, #24
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addne r1, r1, r12, lsr r2
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bic r1, r1, #1
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.endm
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@ \r=sin/result, r1=env, r3=ym_tl_tab
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.macro lookup_tl r
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tst \r, #0x100
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eorne \r, \r, #0xff @ if (sin & 0x100) sin = 0xff - (sin&0xff);
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tst \r, #0x200
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and \r, \r, #0xff
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orr \r, \r, r1, lsl #8
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orr \r, \r, r1, lsl #7
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mov \r, \r, lsl #1
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ldrh \r, [r3, \r] @ 2ci if ne
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rsbne \r, \r, #0
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@ -345,9 +317,9 @@
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make_eg_out SLOT3
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cmp r1, #ENV_QUIET
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ldr r2, [lr, #0x38] @ mem (for future)
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movcs r0, r2
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mov r0, #0
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bcs 0f
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ldr r0, [lr, #0x18] @ 1ci
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ldr r0, [lr, #0x18] @ phase3
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mov r0, r0, lsr #16
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lookup_tl r0 @ r0=c2
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@ -370,7 +342,7 @@
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cmp r1, #ENV_QUIET
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movcs r2, #0
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bcs 2f
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ldr r2, [lr, #0x14]
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ldr r2, [lr, #0x14] @ phase2
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mov r5, r10, lsr #17
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add r2, r5, r2, lsr #16
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lookup_tl r2 @ r2=mem
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@ -541,9 +513,9 @@
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movne r0, r0, asr #16
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movne r0, r0, lsl r2
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ldr r2, [lr, #0x10]
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ldr r2, [lr, #0x10] @ phase1
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add r0, r0, r2
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mov r0, r0, lsr #16
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add r0, r0, r2, lsr #16
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lookup_tl r0
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mov r10,r10,lsl #16 @ ct->op1_out <<= 16;
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mov r0, r0, lsl #16
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@ -759,11 +731,18 @@ chan_render_loop:
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crl_loop_lfo:
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add r0, lr, #0x30
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ldmia r0, {r1,r2}
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subs r4, r4, #0x100
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bmi crl_loop_end
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add r2, r2, r1
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str r2, [lr, #0x30]
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@ r12=lfo_ampm[31:16], r1=lfo_cnt_old, r2=lfo_cnt
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advance_lfo_m
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add r4, r4, #0x100
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crl_loop:
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subs r4, r4, #0x100
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bmi crl_loop_end
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@ -859,7 +838,6 @@ crl_algo6:
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crl_algo7:
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upd_algo7_m
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.pool
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crl_algo_done:
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@ -917,6 +895,7 @@ crl_do_phase:
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crl_loop_end:
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@ stmia lr, {r6,r7} @ save volumes (for debug)
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str r8, [lr, #0x44] @ eg_timer
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str r12, [lr, #0x4c] @ pack (for lfo_ampm)
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str r4, [lr, #0x50] @ was_update
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@ -925,3 +904,4 @@ crl_loop_end:
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.pool
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@ vim:filetype=armasm
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue