mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
SH2 drc: bug fixing and small speed improvements
This commit is contained in:
kub
parent
1891e649e5
commit
748b8187db
8 changed files with 254 additions and 203 deletions
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@ -6,3 +6,39 @@ extern u8 *tcache;
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void drc_cmn_init(void);
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void drc_cmn_cleanup(void);
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#define BITMASK1(v0) (1 << (v0))
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#define BITMASK2(v0,v1) ((1 << (v0)) | (1 << (v1)))
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#define BITMASK3(v0,v1,v2) (BITMASK2(v0,v1) | (1 << (v2)))
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#define BITMASK4(v0,v1,v2,v3) (BITMASK3(v0,v1,v2) | (1 << (v3)))
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#define BITMASK5(v0,v1,v2,v3,v4) (BITMASK4(v0,v1,v2,v3) | (1 << (v4)))
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#define BITMASK6(v0,v1,v2,v3,v4,v5) (BITMASK5(v0,v1,v2,v3,v4) | (1 << (v5)))
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#define BITRANGE(v0,v1) (BITMASK1(v1+1)-BITMASK1(v0)) // set with v0..v1
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// binary search approach, since we don't have CLZ on ARM920T
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#define FOR_ALL_BITS_SET_DO(mask, bit, code) { \
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u32 __mask = mask; \
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for (bit = 31; bit >= 0 && mask; bit--, __mask <<= 1) { \
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if (!(__mask & (0xffff << 16))) \
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bit -= 16, __mask <<= 16; \
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if (!(__mask & (0xff << 24))) \
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bit -= 8, __mask <<= 8; \
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if (!(__mask & (0xf << 28))) \
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bit -= 4, __mask <<= 4; \
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if (!(__mask & (0x3 << 30))) \
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bit -= 2, __mask <<= 2; \
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if (!(__mask & (0x1 << 31))) \
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bit -= 1, __mask <<= 1; \
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if (__mask & (0x1 << 31)) { \
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code; \
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} \
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} \
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}
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// inspired by https://graphics.stanford.edu/~seander/bithacks.html
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static inline int count_bits(unsigned val)
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{
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val = val - ((val >> 1) & 0x55555555);
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val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
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return (((val + (val >> 4)) & 0x0F0F0F0F) * 0x01010101) >> 24;
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}
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@ -382,13 +382,6 @@ static void emith_flush(void)
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#define EOP_MOVT(rd,imm) \
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EMIT(0xe3400000 | ((rd)<<12) | (((imm)>>16)&0xfff) | (((imm)>>12)&0xf0000), M1(rd), NO)
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static inline int count_bits(unsigned val)
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{
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val = val - ((val >> 1) & 0x55555555);
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val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
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return (((val + (val >> 4)) & 0x0F0F0F0F) * 0x01010101) >> 24;
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}
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// host literal pool; must be significantly smaller than 1024 (max LDR offset = 4096)
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#define MAX_HOST_LITERALS 128
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static u32 literal_pool[MAX_HOST_LITERALS];
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@ -429,18 +422,26 @@ static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int
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// count insns needed for mov/orr #imm
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for (v = imm, ror2 = 0; (v >> 24) && ror2 < 32/2; ror2++)
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v = (v << 2) | (v >> 30);
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#ifdef HAVE_ARMV7
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for (i = 2; i > 0; i--, v >>= 8)
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while (v > 0xff && !(v & 3))
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v >>= 2;
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if (v) { // 3+ insns needed...
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if (op == A_OP_MVN)
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imm = ~imm;
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#ifdef HAVE_ARMV7
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// ...prefer movw/movt
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EOP_MOVW(rd, imm);
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if (imm & 0xffff0000)
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EOP_MOVT(rd, imm);
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return;
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}
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#else
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for (i = 3; i > 0; i--, v >>= 8)
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while (v > 0xff && !(v & 3))
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v >>= 2;
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if (v) { // 4 insns needed...
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if (op == A_OP_MVN)
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imm = ~imm;
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// ...emit literal load
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int idx, o;
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if (literal_iindex >= MAX_HOST_LITERALS) {
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@ -455,9 +456,9 @@ static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int
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EOP_C_DOP_IMM(cond, A_OP_ADD, 0, rd, rd, 0, o);
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else if (o < 0)
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EOP_C_DOP_IMM(cond, A_OP_SUB, 0, rd, rd, 0, -o);
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#endif
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return;
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}
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#endif
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break;
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case A_OP_AND:
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@ -544,7 +545,7 @@ static int emith_xbranch(int cond, void *target, int is_call)
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EMIT((u32)target,M1(PC),0);
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#else
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// should never happen
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elprintf(EL_STATUS|EL_SVP|EL_ANOMALY, "indirect jmp %08x->%08x", target, tcache_ptr);
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elprintf(EL_STATUS|EL_SVP|EL_ANOMALY, "indirect jmp %8p->%8p", target, tcache_ptr);
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exit(1);
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#endif
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}
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@ -633,9 +634,6 @@ static inline void emith_pool_adjust(int pool_index, int move_offs)
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#define EMITH_NOTHING1(cond) \
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(void)(cond)
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#define EMITH_SJMP_DECL_()
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#define EMITH_SJMP_START_(cond) EMITH_NOTHING1(cond)
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#define EMITH_SJMP_END_(cond) EMITH_NOTHING1(cond)
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#define EMITH_SJMP_START(cond) EMITH_NOTHING1(cond)
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#define EMITH_SJMP_END(cond) EMITH_NOTHING1(cond)
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#define EMITH_SJMP2_START(cond) EMITH_NOTHING1(cond)
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@ -806,6 +804,9 @@ static inline void emith_pool_adjust(int pool_index, int move_offs)
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#define emith_eor_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_EOR, r, imm)
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#define emith_eor_r_imm_ptr(r, imm) \
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emith_eor_r_imm(r, imm)
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// note: only use 8bit imm for these
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#define emith_tst_r_imm(r, imm) \
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emith_top_imm(A_COND_AL, A_OP_TST, r, imm)
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@ -837,6 +838,9 @@ static inline void emith_pool_adjust(int pool_index, int move_offs)
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#define emith_eor_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_EOR, r, imm)
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#define emith_eor_r_imm_ptr_c(cond, r, imm) \
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emith_eor_r_imm_c(cond, r, imm)
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#define emith_bic_r_imm_c(cond, r, imm) \
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emith_op_imm(cond, 0, A_OP_BIC, r, imm)
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@ -1139,6 +1143,8 @@ static inline void emith_pool_adjust(int pool_index, int move_offs)
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emith_jump(target); \
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} while (0)
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#define emith_call_cleanup() /**/
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#define emith_ret_c(cond) \
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emith_jump_reg_c(cond, LR)
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@ -1228,10 +1234,10 @@ static inline void emith_pool_adjust(int pool_index, int move_offs)
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/* if (reg <= turns) turns = reg-1 */ \
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t3 = rcache_get_reg(reg, RC_GR_RMW, NULL); \
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emith_cmp_r_r(t3, t2); \
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emith_sub_r_r_imm_c(DCOND_LE, t2, t3, 1); \
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emith_sub_r_r_imm_c(DCOND_LS, t2, t3, 1); \
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/* if (reg <= 1) turns = 0 */ \
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emith_cmp_r_imm(t3, 1); \
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emith_move_r_imm_c(DCOND_LE, t2, 0); \
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emith_move_r_imm_c(DCOND_LS, t2, 0); \
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/* reg -= turns */ \
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emith_sub_r_r(t3, t2); \
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} \
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@ -1361,7 +1367,7 @@ static int tcond = -1;
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#define emith_set_t(sr, val) \
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tcond = ((val) ? A_COND_AL: A_COND_NV)
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static void emith_sync_t(sr)
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static void emith_sync_t(int sr)
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{
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if (tcond == A_COND_AL)
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emith_or_r_imm(sr, T);
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@ -396,6 +396,12 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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#define emith_cmp_r_imm(r, imm) \
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emith_arith_r_imm(7, r, imm)
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#define emith_eor_r_imm_ptr(r, imm) do { \
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EMIT_REX_IF(1, 0, r); \
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EMIT_OP_MODRM64(0x81, 3, 6, r); \
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EMIT(imm, u32); \
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} while (0)
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#define emith_tst_r_imm(r, imm) do { \
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EMIT_REX_IF(0, 0, r); \
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EMIT_OP_MODRM64(0xf7, 3, 0, r); \
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@ -417,6 +423,8 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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emith_or_r_imm(r, imm)
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#define emith_eor_r_imm_c(cond, r, imm) \
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emith_eor_r_imm(r, imm)
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#define emith_eor_r_imm_ptr_c(cond, r, imm) \
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emith_eor_r_imm_ptr(r, imm)
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#define emith_bic_r_imm_c(cond, r, imm) \
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emith_bic_r_imm(r, imm)
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#define emith_tst_r_imm_c(cond, r, imm) \
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@ -589,9 +597,9 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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// XXX: stupid mess
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#define emith_mul_(op, dlo, dhi, s1, s2) do { \
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int rmr; \
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if (dlo != xAX && dhi != xAX) \
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if (dlo != xAX && dhi != xAX && rcache_is_hreg_used(xAX)) \
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emith_push(xAX); \
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if (dlo != xDX && dhi != xDX) \
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if (dlo != xDX && dhi != xDX && rcache_is_hreg_used(xDX)) \
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emith_push(xDX); \
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if ((s1) == xAX) \
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rmr = s2; \
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@ -609,9 +617,9 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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} \
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if (dhi != xDX && dhi != -1 && !(dhi == xAX && dlo == xDX)) \
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emith_move_r_r(dhi, (dlo == xDX ? xAX : xDX)); \
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if (dlo != xDX && dhi != xDX) \
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if (dlo != xDX && dhi != xDX && rcache_is_hreg_used(xDX)) \
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emith_pop(xDX); \
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if (dlo != xAX && dhi != xAX) \
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if (dlo != xAX && dhi != xAX && rcache_is_hreg_used(xAX)) \
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emith_pop(xAX); \
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} while (0)
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@ -898,6 +906,9 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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emith_jump(target); \
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} while (0)
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#define emith_call_cleanup() \
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emith_add_r_r_ptr_imm(xSP, xSP, sizeof(void *)); // remove return addr
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#define emith_ret() \
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EMIT_OP(0xc3)
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@ -912,10 +923,12 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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#define emith_push_ret(r) do { \
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int r_ = (r >= 0 ? r : xSI); \
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emith_push(r_); /* always push to align */ \
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emith_add_r_r_ptr_imm(xSP, xSP, -8*4); /* args shadow space */ \
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} while (0)
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#define emith_pop_and_ret(r) do { \
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int r_ = (r >= 0 ? r : xSI); \
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emith_add_r_r_ptr_imm(xSP, xSP, 8*4); /* args shadow space */ \
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emith_pop(r_); \
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emith_ret(); \
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} while (0)
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@ -942,15 +955,6 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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// "simple" jump (no more then a few insns)
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// ARM will use conditional instructions here
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#define EMITH_SJMP_DECL_() \
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u8 *cond_ptr
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#define EMITH_SJMP_START_(cond) \
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JMP8_POS(cond_ptr)
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#define EMITH_SJMP_END_(cond) \
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JMP8_EMIT(cond, cond_ptr)
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#define EMITH_SJMP_START EMITH_JMP_START
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#define EMITH_SJMP_END EMITH_JMP_END
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@ -1046,7 +1050,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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emith_push(xR15); \
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emith_push(xSI); \
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emith_push(xDI); \
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emith_add_r_r_ptr_imm(xSP, xSP, -8*5); /* align + ABI param area */ \
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emith_add_r_r_ptr_imm(xSP, xSP, -8*5); /* align + args shadow space */ \
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} while (0)
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#define emith_sh2_drc_exit() do { \
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@ -1106,19 +1110,17 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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#endif
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#define emith_save_caller_regs(mask) do { \
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if ((mask) & (1 << xAX)) emith_push(xAX); \
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if ((mask) & (1 << xCX)) emith_push(xCX); \
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if ((mask) & (1 << xDX)) emith_push(xDX); \
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if ((mask) & (1 << xSI)) emith_push(xSI); \
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if ((mask) & (1 << xDI)) emith_push(xDI); \
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int _c; u32 _m = mask & 0xfc7; /* AX, CX, DX, SI, DI, 8, 9, 10, 11 */ \
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if (__builtin_parity(_m) == 1) _m |= 0x8; /* BX for ABI align */ \
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for (_c = HOST_REGS; _m && _c >= 0; _m &= ~(1 << _c), _c--) \
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if (_m & (1 << _c)) emith_push(_c); \
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} while (0)
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#define emith_restore_caller_regs(mask) do { \
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if ((mask) & (1 << xDI)) emith_pop(xDI); \
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if ((mask) & (1 << xSI)) emith_pop(xSI); \
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if ((mask) & (1 << xDX)) emith_pop(xDX); \
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if ((mask) & (1 << xCX)) emith_pop(xCX); \
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if ((mask) & (1 << xAX)) emith_pop(xAX); \
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int _c; u32 _m = mask & 0xfc7; \
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if (__builtin_parity(_m) == 1) _m |= 0x8; /* BX for ABI align */ \
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for (_c = 0; _m && _c < HOST_REGS; _m &= ~(1 << _c), _c++) \
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if (_m & (1 << _c)) emith_pop(_c); \
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} while (0)
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#define emith_sh2_rcall(a, tab, func, mask) do { \
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@ -1192,14 +1194,14 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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/* if (reg <= turns) turns = reg-1 */ \
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t3 = rcache_get_reg(reg, RC_GR_RMW, NULL); \
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emith_cmp_r_r(t3, t2); \
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EMITH_SJMP_START(DCOND_GT); \
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emith_sub_r_r_imm_c(DCOND_LE, t2, t3, 1); \
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EMITH_SJMP_END(DCOND_GT); \
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EMITH_SJMP_START(DCOND_HI); \
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emith_sub_r_r_imm_c(DCOND_LS, t2, t3, 1); \
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EMITH_SJMP_END(DCOND_HI); \
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/* if (reg <= 1) turns = 0 */ \
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emith_cmp_r_imm(t3, 1); \
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EMITH_SJMP_START(DCOND_GT); \
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emith_move_r_imm_c(DCOND_LE, t2, 0); \
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EMITH_SJMP_END(DCOND_GT); \
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EMITH_SJMP_START(DCOND_HI); \
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emith_move_r_imm_c(DCOND_LS, t2, 0); \
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EMITH_SJMP_END(DCOND_HI); \
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/* reg -= turns */ \
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emith_sub_r_r(t3, t2); \
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} \
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