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https://github.com/RaySollium99/picodrive.git
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32x: more memhandler improvements
This commit is contained in:
notaz
parent
9e1fa0a6cf
commit
77e58d93fe
2 changed files with 144 additions and 15 deletions
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@ -350,12 +350,15 @@ static void p32x_reg_write8(u32 a, u32 d)
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case 0x31: // PWM control
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REG8IN16(r, a) &= ~0x0f;
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REG8IN16(r, a) |= d & 0x0f;
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d = r[0x30 / 2];
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goto pwm_write;
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case 0x32: // PWM cycle
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REG8IN16(r, a) = d & 0x0f;
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d = r[0x32 / 2];
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goto pwm_write;
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case 0x33:
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REG8IN16(r, a) = d;
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d = r[0x32 / 2];
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goto pwm_write;
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// PWM pulse regs.. Only writes to odd address send a value
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// to FIFO; reads are 0 (except status bits)
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@ -367,8 +370,8 @@ static void p32x_reg_write8(u32 a, u32 d)
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case 0x35:
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case 0x37:
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case 0x39:
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d = (REG8IN16(r, a) << 8) | (d & 0xff);
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REG8IN16(r, a) = 0;
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d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff);
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REG8IN16(r, a ^ 1) = 0;
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goto pwm_write;
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case 0x3a: // ignored, always 0
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case 0x3b:
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@ -378,7 +381,7 @@ static void p32x_reg_write8(u32 a, u32 d)
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case 0x3f:
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return;
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pwm_write:
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p32x_pwm_write16(a & ~1, r[a / 2], NULL, SekCyclesDoneT());
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p32x_pwm_write16(a & ~1, d, NULL, SekCyclesDoneT());
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return;
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}
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@ -440,6 +443,11 @@ static void p32x_reg_write16(u32 a, u32 d)
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case 0x1a: // TV + mystery bit
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r[a / 2] = d & 0x0101;
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return;
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case 0x30: // PWM control
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d = (r[a / 2] & ~0x0f) | (d & 0x0f);
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r[a / 2] = d;
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p32x_pwm_write16(a, d, NULL, SekCyclesDoneT());
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return;
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}
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// comm port
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@ -609,23 +617,24 @@ static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
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return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2));
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elprintf_sh2(sh2, EL_32X|EL_ANOMALY,
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"unhandled sysreg r16 [%06x] @%06x", a, SekPc);
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"unhandled sysreg r16 [%02x] @%08x", a, sh2_pc(sh2));
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return 0;
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}
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static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
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{
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u16 *r = Pico32x.regs;
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u32 old;
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a &= 0xff;
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sh2->poll_addr = 0;
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switch (a) {
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case 0: // FM
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Pico32x.regs[0] &= ~P32XS_FM;
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Pico32x.regs[0] |= (d << 8) & P32XS_FM;
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case 0x00: // FM
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r[0] &= ~P32XS_FM;
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r[0] |= (d << 8) & P32XS_FM;
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return;
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case 1: // HEN/irq masks
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case 0x01: // HEN/irq masks
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old = Pico32x.sh2irq_mask[sh2->is_slave];
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if ((d ^ old) & 1)
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p32x_pwm_sync_to_sh2(sh2);
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@ -641,7 +650,9 @@ static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
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if ((old ^ d) & 4)
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p32x_schedule_hint(sh2, 0);
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return;
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case 5: // H count
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case 0x04: // ignored?
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return;
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case 0x05: // H count
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d &= 0xff;
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if (Pico32x.sh2_regs[4 / 2] != d) {
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Pico32x.sh2_regs[4 / 2] = d;
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@ -650,15 +661,53 @@ static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
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sh2_end_run(sh2, 4);
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}
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return;
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case 0x30:
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REG8IN16(r, a) = d & 0x0f;
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d = r[0x30 / 2];
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goto pwm_write;
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case 0x31: // PWM control
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REG8IN16(r, a) = d & 0x8f;
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d = r[0x30 / 2];
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goto pwm_write;
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case 0x32: // PWM cycle
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REG8IN16(r, a) = d & 0x0f;
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d = r[0x32 / 2];
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goto pwm_write;
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case 0x33:
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REG8IN16(r, a) = d;
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d = r[0x32 / 2];
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goto pwm_write;
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// PWM pulse regs.. Only writes to odd address send a value
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// to FIFO; reads are 0 (except status bits)
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case 0x34:
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case 0x36:
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case 0x38:
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REG8IN16(r, a) = d;
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return;
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case 0x35:
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case 0x37:
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case 0x39:
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d = (REG8IN16(r, a ^ 1) << 8) | (d & 0xff);
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REG8IN16(r, a ^ 1) = 0;
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goto pwm_write;
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case 0x3a: // ignored, always 0?
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case 0x3b:
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case 0x3c:
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case 0x3d:
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case 0x3e:
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case 0x3f:
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return;
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pwm_write:
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p32x_pwm_write16(a & ~1, d, sh2, 0);
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return;
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}
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if ((a & 0x30) == 0x20) {
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u8 *r8 = (u8 *)Pico32x.regs;
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int comreg;
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if (r8[a ^ 1] == d)
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if (REG8IN16(r, a) == d)
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return;
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r8[a ^ 1] = d;
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REG8IN16(r, a) = d;
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p32x_m68k_poll_event(P32XF_68KCPOLL);
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p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
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sh2_cycles_done_m68k(sh2));
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@ -666,6 +715,9 @@ static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
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Pico32x.comm_dirty_sh2 |= comreg;
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return;
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}
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elprintf(EL_32X|EL_ANOMALY,
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"unhandled sysreg w8 [%02x] %02x @%08x", a, d, sh2_pc(sh2));
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}
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static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
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@ -816,6 +868,8 @@ static void PicoWrite8_32x_on(u32 a, u32 d)
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if ((a & 0xfc00) != 0x5000) {
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PicoWrite8_io(a, d);
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if (a == 0xa130f1)
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bank_switch(Pico32x.regs[4 / 2]);
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return;
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}
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@ -849,6 +903,8 @@ static void PicoWrite16_32x_on(u32 a, u32 d)
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if ((a & 0xfc00) != 0x5000) {
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PicoWrite16_io(a, d);
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if (a == 0xa130f0)
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bank_switch(Pico32x.regs[4 / 2]);
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return;
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}
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@ -1014,7 +1070,8 @@ static void PicoWrite8_hint(u32 a, u32 d)
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return;
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}
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elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
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elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x",
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a, d & 0xff, SekPc);
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}
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static void PicoWrite16_hint(u32 a, u32 d)
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@ -1024,7 +1081,64 @@ static void PicoWrite16_hint(u32 a, u32 d)
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return;
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}
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elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
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elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x",
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a, d & 0xffff, SekPc);
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}
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// normally not writable, but somebody could make a RAM cart
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static void PicoWrite8_cart(u32 a, u32 d)
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{
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elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
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a &= 0xfffff;
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m68k_write8(a, d);
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}
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static void PicoWrite16_cart(u32 a, u32 d)
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{
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elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
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a &= 0xfffff;
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m68k_write16(a, d);
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}
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// same with bank, but save ram is sometimes here
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static u32 PicoRead8_bank(u32 a)
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{
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a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
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return m68k_read8(a);
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}
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static u32 PicoRead16_bank(u32 a)
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{
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a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
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return m68k_read16(a);
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}
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static void PicoWrite8_bank(u32 a, u32 d)
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{
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if (!(Pico.m.sram_reg & SRR_MAPPED))
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elprintf(EL_UIO, "m68k w8 [%06x] %02x @%06x",
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a, d & 0xff, SekPc);
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a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
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m68k_write8(a, d);
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}
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static void PicoWrite16_bank(u32 a, u32 d)
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{
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if (!(Pico.m.sram_reg & SRR_MAPPED))
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elprintf(EL_UIO, "m68k w16 [%06x] %04x @%06x",
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a, d & 0xffff, SekPc);
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a = (Pico32x.regs[4 / 2] << 20) | (a & 0xfffff);
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m68k_write16(a, d);
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}
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static void bank_map_handler(void)
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{
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cpu68k_map_set(m68k_read8_map, 0x900000, 0x9fffff, PicoRead8_bank, 1);
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cpu68k_map_set(m68k_read16_map, 0x900000, 0x9fffff, PicoRead16_bank, 1);
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}
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static void bank_switch(int b)
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@ -1032,8 +1146,14 @@ static void bank_switch(int b)
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unsigned int rs, bank;
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bank = b << 20;
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if ((Pico.m.sram_reg & SRR_MAPPED) && bank == SRam.start) {
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bank_map_handler();
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return;
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}
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if (bank >= Pico.romsize) {
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elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank);
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bank_map_handler();
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return;
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}
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@ -1358,7 +1478,7 @@ u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
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return (pd[0] << 16) | pd[1];
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}
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if (offs == 0x1f)
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if (offs == SH2MAP_ADDR2OFFS_R(0xffffc000))
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return sh2_peripheral_read32(a, sh2);
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handler = (sh2_read_handler *)(p << 1);
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@ -1579,6 +1699,8 @@ void PicoMemSetup32x(void)
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rs = 0x80000;
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cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
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cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0);
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cpu68k_map_set(m68k_write8_map, 0x880000, 0x880000 + rs - 1, PicoWrite8_cart, 1);
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cpu68k_map_set(m68k_write16_map, 0x880000, 0x880000 + rs - 1, PicoWrite16_cart, 1);
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#ifdef EMU_F68K
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// setup FAME fetchmap
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PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
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@ -1588,6 +1710,8 @@ void PicoMemSetup32x(void)
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// 32X ROM (banked)
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bank_switch(0);
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cpu68k_map_set(m68k_write8_map, 0x900000, 0x9fffff, PicoWrite8_bank, 1);
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cpu68k_map_set(m68k_write16_map, 0x900000, 0x9fffff, PicoWrite16_bank, 1);
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// SYS regs
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cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1);
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@ -26,6 +26,11 @@ extern uptr s68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];
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typedef u32 (cpu68k_read_f)(u32 a);
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typedef void (cpu68k_write_f)(u32 a, u32 d);
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extern u32 m68k_read8(u32 a);
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extern u32 m68k_read16(u32 a);
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extern void m68k_write8(u32 a, u8 d);
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extern void m68k_write16(u32 a, u16 d);
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// z80
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#define Z80_MEM_SHIFT 13
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extern uptr z80_read_map [0x10000 >> Z80_MEM_SHIFT];
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