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https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
sh2 drc: speed optimization and bugfixing
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kub
parent
c3ebe082d3
commit
7869213d35
5 changed files with 61 additions and 55 deletions
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@ -160,7 +160,7 @@ enum { XT_UXTW=0x4, XT_UXTX=0x6, XT_LSL=0x7, XT_SXTW=0xc, XT_SXTX=0xe };
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#define A64_ROR_REG(rd, rn, rm) \
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A64_INSN(0xd,0x0,0x3,_,rm,_,0xb,rn,rd)
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// rd = REVERSE(n) rn
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// rd = REVERSE(rn)
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#define A64_RBIT_REG(rd, rn) \
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A64_INSN(0xd,0x2,0x3,_,_,_,_,rn,rd)
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@ -327,9 +327,10 @@ enum { AM_IDX, AM_IDXPOST, AM_IDXREG, AM_IDXPRE };
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// if-then-else conditional execution helpers
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#define JMP_POS(ptr) \
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#define JMP_POS(ptr) { \
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ptr = tcache_ptr; \
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EMIT(A64_B(0));
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EMIT(A64_B(0)); \
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}
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#define JMP_EMIT(cond, ptr) { \
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u32 val_ = (u8 *)tcache_ptr - (u8 *)(ptr); \
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@ -1225,9 +1226,9 @@ static void emith_ldst_offs(int sz, int rd, int rn, int o9, int ld, int mode)
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emith_tst_r_imm(sr, S); \
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EMITH_SJMP_START(DCOND_EQ); \
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/* overflow if top 17 bits of MACH aren't all 1 or 0 */ \
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/* to check: add MACH[15] to MACH[31:16]. this is 0 if no overflow */ \
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emith_asrf(rn, mh, 16); /* sum = (MACH>>16) + ((MACH>>15)&1) */ \
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emith_adcf_r_imm(rn, 0); /* (MACH>>15) is in carry after shift */ \
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/* to check: add MACH >> 31 to MACH >> 15. this is 0 if no overflow */ \
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emith_asr(rn, mh, 15); \
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emith_addf_r_r_r_lsr(rn, rn, mh, 31); \
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EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> ov */ \
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emith_move_r_imm_c(DCOND_NE, ml, 0x0000); /* -overflow */ \
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emith_move_r_imm_c(DCOND_NE, mh, 0x8000); \
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@ -1280,11 +1281,12 @@ static void emith_ldst_offs(int sz, int rd, int rn, int o9, int ld, int mode)
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#define emith_tpop_carry(sr, is_sub) do { \
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if (is_sub) \
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emith_eor_r_imm(sr, 1); \
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emith_lsrf(sr, sr, 1); \
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emith_ror(sr, sr, 1); \
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emith_addf_r_r(sr, sr); \
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} while (0)
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#define emith_tpush_carry(sr, is_sub) do { \
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emith_adc_r_r(sr, sr); \
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emith_adc_r_r(sr, Z0); \
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if (is_sub) \
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emith_eor_r_imm(sr, 1); \
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} while (0)
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@ -21,7 +21,7 @@
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#define AT 1 // used to hold intermediate results
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#define FNZ 15 // emulated processor flags: N (bit 31) ,Z (all bits)
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#define FC 24 // emulated processor flags: C (bit 0), others 0
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#define FV 25 // emulated processor flags: Nt^Ns (bit 31). others ?
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#define FV 25 // emulated processor flags: Nt^Ns (bit 31). others x
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// unified conditions; virtual, not corresponding to anything real on MIPS
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@ -208,8 +208,8 @@ enum { RT_BLTZ=000, RT_BGEZ, RT_BLTZAL=020, RT_BGEZAL, RT_SYNCI=037 };
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} while (0)
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// FIFO for 2 instructions, for delay slot handling
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u32 emith_last_insns[2] = { -1,-1 };
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int emith_last_idx, emith_last_cnt;
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static u32 emith_last_insns[2] = { -1,-1 };
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static int emith_last_idx, emith_last_cnt;
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#define EMIT_PUSHOP() \
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do { \
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@ -248,7 +248,7 @@ static int emith_is_b(u32 op) // B
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((op>>26) == OP__RT && ((op>>16) & 036) == RT_BLTZ); }
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// register usage for dependency evaluation XXX better do this as in emit_arm?
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static uint64_t emith_has_rs[3] = // OP__FN, OP__RT, others
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{ 0x00fffffffffa0ff0ULL, 0x000fff0fUL, 0xffffffff0f007f30ULL };
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{ 0x00fffffffffa0ff0ULL, 0x000fff0fUL, 0xffffffff0f007ff0ULL };
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static uint64_t emith_has_rt[3] = // OP__FN, OP__RT, others
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{ 0xff00fffffff00cffULL, 0x00000000UL, 0x8000ff0000000030ULL };
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static uint64_t emith_has_rd[3] = // OP__FN, OP__RT, others (rt instead of rd)
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@ -308,21 +308,23 @@ static void *emith_branch(u32 op)
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bop = emith_b_isswap(op, op2);
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}
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// flush FIFO and branch
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tcache_ptr = (void *)((u32 *)tcache_ptr - emith_last_cnt);
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if (emith_last_insns[idx^1] != -1)
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EMIT_PTR(tcache_ptr, emith_last_insns[idx^1]);
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if (bop) { // can swap
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tcache_ptr = (void *)((u32 *)tcache_ptr - emith_last_cnt);
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if (emith_last_insns[idx^1] != -1)
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EMIT_PTR(tcache_ptr, emith_last_insns[idx^1]);
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bp = tcache_ptr;
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EMIT_PTR(tcache_ptr, bop); COUNT_OP;
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EMIT_PTR(tcache_ptr, emith_last_insns[idx]);
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emith_last_insns[0] = emith_last_insns[1] = -1;
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emith_last_cnt = 0;
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} else { // can't swap
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emith_flush();
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if (emith_last_insns[idx] != -1)
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EMIT_PTR(tcache_ptr, emith_last_insns[idx]);
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bp = tcache_ptr;
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EMIT_PTR(tcache_ptr, op); COUNT_OP;
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EMIT_PTR(tcache_ptr, MIPS_NOP); COUNT_OP;
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}
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emith_last_insns[0] = emith_last_insns[1] = -1;
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emith_last_cnt = 0;
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return bp;
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}
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@ -392,8 +394,8 @@ static void *emith_branch(u32 op)
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// flag emulation creates 2 (ie cmp #0/beq) up to 9 (ie adcf/ble) extra insns.
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// flag handling shortcuts may reduce this by 1-4 insns, see emith_cond_check()
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int emith_flg_rs, emith_flg_rt; // registers used in FNZ=rs-rt (aka cmp_r_r)
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int emith_flg_noV; // V flag known not to be set
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static int emith_flg_rs, emith_flg_rt; // registers used in FNZ=rs-rt (cmp_r_r)
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static int emith_flg_noV; // V flag known not to be set
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// store minimal cc information: rd, rt^rs, carry
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// NB: the result *must* first go to FNZ, in case rd == rs or rd == rt.
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@ -625,7 +627,11 @@ static void emith_set_arith_flags(int rd, int rt, int rs, s32 imm, int sub)
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// move immediate
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static void emith_move_imm(int r, uintptr_t imm)
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{
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if ((s16)imm != imm) {
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if ((s16)imm == imm) {
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EMIT(MIPS_ADD_IMM(r, Z0, imm));
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} else if (!(imm >> 16)) {
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EMIT(MIPS_OR_IMM(r, Z0, imm));
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} else {
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int s = Z0;
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if (imm >> 16) {
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EMIT(MIPS_MOVT_IMM(r, imm >> 16));
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@ -633,8 +639,7 @@ static void emith_move_imm(int r, uintptr_t imm)
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}
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if ((u16)imm)
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EMIT(MIPS_OR_IMM(r, s, (u16)imm));
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} else
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EMIT(MIPS_ADD_IMM(r, Z0, imm));
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}
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}
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#define emith_move_r_ptr_imm(r, imm) \
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@ -1372,16 +1377,17 @@ static int emith_cond_check(int cond, int *r)
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emith_tst_r_imm(sr, S); \
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EMITH_SJMP_START(DCOND_EQ); \
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/* overflow if top 17 bits of MACH aren't all 1 or 0 */ \
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/* to check: add MACH[15] to MACH[31:16]. this is 0 if no overflow */ \
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emith_asrf(rn, mh, 16); /* sum = (MACH>>16) + ((MACH>>15)&1) */ \
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emith_adcf_r_imm(rn, 0); /* (MACH>>15) is in carry after shift */ \
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/* to check: add MACH >> 31 to MACH >> 15. this is 0 if no overflow */ \
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emith_asr(rn, mh, 15); \
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emith_add_r_r_r_lsr(rn, rn, mh, 31); /* sum = (MACH>>31)+(MACH>>15) */ \
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emith_teq_r_r(rn, Z0); /* (need only N and Z flags) */ \
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EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> ov */ \
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emith_move_r_imm_c(DCOND_NE, ml, 0x0000); /* -overflow */ \
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emith_move_r_imm_c(DCOND_NE, mh, 0x8000); \
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EMITH_SJMP_START(DCOND_LE); /* sum > 0 -> +ovl */ \
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emith_sub_r_imm_c(DCOND_GT, ml, 1); /* 0xffffffff */ \
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emith_sub_r_imm_c(DCOND_GT, mh, 1); /* 0x00007fff */ \
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EMITH_SJMP_END(DCOND_LE); \
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EMITH_SJMP_START(DCOND_PL); /* sum > 0 -> +ovl */ \
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emith_sub_r_imm_c(DCOND_MI, ml, 1); /* 0xffffffff */ \
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emith_sub_r_imm_c(DCOND_MI, mh, 1); /* 0x00007fff */ \
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EMITH_SJMP_END(DCOND_PL); \
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EMITH_SJMP_END(DCOND_EQ); \
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EMITH_SJMP_END(DCOND_EQ); \
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} while (0)
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@ -1399,14 +1405,15 @@ static int emith_cond_check(int cond, int *r)
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/* overflow if top 33 bits of MACH:MACL aren't all 1 or 0 */ \
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/* to check: add MACL[31] to MACH. this is 0 if no overflow */ \
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emith_lsr(rn, ml, 31); \
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emith_addf_r_r(rn, mh); /* sum = MACH + ((MACL>>31)&1) */ \
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emith_add_r_r(rn, mh); /* sum = MACH + ((MACL>>31)&1) */ \
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emith_teq_r_r(rn, Z0); /* (need only N and Z flags) */ \
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EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> overflow */ \
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/* XXX: LSB signalling only in SH1, or in SH2 too? */ \
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emith_move_r_imm_c(DCOND_NE, mh, 0x00000001); /* LSB of MACH */ \
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emith_move_r_imm_c(DCOND_NE, ml, 0x80000000); /* negative ovrfl */ \
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EMITH_SJMP_START(DCOND_LE); /* sum > 0 -> positive ovrfl */ \
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emith_sub_r_imm_c(DCOND_GT, ml, 1); /* 0x7fffffff */ \
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EMITH_SJMP_END(DCOND_LE); \
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EMITH_SJMP_START(DCOND_PL); /* sum > 0 -> positive ovrfl */ \
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emith_sub_r_imm_c(DCOND_MI, ml, 1); /* 0x7fffffff */ \
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EMITH_SJMP_END(DCOND_PL); \
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EMITH_SJMP_END(DCOND_EQ); \
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EMITH_SJMP_END(DCOND_EQ); \
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} while (0)
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@ -1225,6 +1225,11 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
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rcache_free_tmp(tmp_); \
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} while (0)
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#define emith_carry_to_t(sr, is_sub) do { \
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emith_rorc(sr); \
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emith_rol(sr, sr, 1); \
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} while (0)
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#define emith_tpop_carry(sr, is_sub) \
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emith_lsr(sr, sr, 1)
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