mirror of
https://github.com/RaySollium99/picodrive.git
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vdp fifo, another revision
This commit is contained in:
kub
parent
25be5c52b0
commit
787a0af9dc
2 changed files with 120 additions and 104 deletions
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@ -296,10 +296,9 @@ extern SH2 sh2s[2];
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// not part of real SR
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#define PVS_ACTIVE (1 << 16)
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#define PVS_VB2 (1 << 17) // ignores forced blanking
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#define PVS_CPUWR (1 << 18) // CPU hold by FIFO full
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#define PVS_CPURD (1 << 19) // CPU hold by FIFO full
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#define PVS_DMAPEND (1 << 20) // DMA operation waiting for start
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#define PVS_DMAFILL (1 << 21) // DMA fill is in progress
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#define PVS_CPUWR (1 << 18) // CPU write blocked by FIFO full
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#define PVS_CPURD (1 << 19) // CPU read blocked by FIFO not empty
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#define PVS_DMAFILL (1 << 20) // DMA fill is waiting for fill data
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struct PicoVideo
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{
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217
pico/videoport.c
217
pico/videoport.c
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@ -37,8 +37,10 @@ int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned
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* fifo_slot is always behind slot2cyc[cycles]. Advancing it beyond cycles
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* implies blocking the 68k up to that slot.
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*
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* A FIFO write goes to the end of the fifo queue. There can be more pending
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* writes than FIFO slots, but the 68k will be blocked in most of those cases.
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* A FIFO write goes to the end of the FIFO queue, but DMA running in background
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* is always the last queue entry (transfers by CPU intervene and come 1st).
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* There can be more pending writes than FIFO slots, but the CPU will be blocked
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* until FIFO level (without background DMA) <= 4.
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* This is only about correct timing, data xfer must be handled by the caller.
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* Blocking the CPU means burning cycles via SekCyclesBurn*(), which is to be
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* executed by the caller.
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@ -50,16 +52,14 @@ int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned
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* FIFORead executes a 68k read. 68k is blocked until the next transfer slot.
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*/
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// FIFO transfer slots per line: H32 blank, H40 blank, H32 active, H40 active
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static const short vdpslots[] = { 166, 204, 16, 18 };
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// mapping between slot# and 68k cycles in a blanked scanline
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static const int vdpcyc2sl_bl[] = { (166<<16)/488, (204<<16)/488, (16<<16)/488, (18<<16)/488 };
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static const int vdpsl2cyc_bl[] = { (488<<16)/166, (488<<16)/204, (488<<16)/16, (488<<16)/18 };
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// mapping between slot# and 68k cycles in a blanked scanline [H32, H40]
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static const int vdpcyc2sl_bl[] = { (166<<16)/488, (204<<16)/488 };
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static const int vdpsl2cyc_bl[] = { (488<<16)/166, (488<<16)/204 };
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// VDP transfer slots in active display 32col mode. 1 slot is 488/171 = 2.8538
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// 68k cycles. Only 16 of the 171 slots in a scanline can be used by CPU/DMA:
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// (HINT=slot 0): 13,27,42,50,58,74,82,90,106,114,122,138,146,154,169,170
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const unsigned char vdpcyc2sl_32[] = { // 68k cycles/4 since HINT to slot #
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static const unsigned char vdpcyc2sl_32[] = { // 68k cycles/4 to slot #
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// 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
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0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
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@ -70,14 +70,14 @@ const unsigned char vdpcyc2sl_32[] = { // 68k cycles/4 since HINT to slot #
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11,11,12,12,12,12,12,12,13,13,13,13,13,13,14,14,
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14,14,14,14,14,14,14,14,15,16,16,16,16,16,16,16,
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};
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const unsigned char vdpsl2cyc_32[] = { // slot # to 68k cycles/4 since HINT
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0, 9, 19, 30, 35, 41, 52, 58, 64, 75, 81, 87, 98,104,110,120,121,123
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static const unsigned char vdpsl2cyc_32[] = { // slot # to 68k cycles/4
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0, 9, 19, 30, 35, 41, 52, 58, 64, 75, 81, 87, 98,104,110,120,121,131
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};
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// VDP transfer slots in active display 40col mode. 1 slot is 488/210 = 2.3238
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// 68k cycles. Only 18 of the 210 slots in a scanline can be used by CPU/DMA:
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// (HINT=0): 23,49,57,65,81,89,97,113,121,129,145,153,161,177,185,193,208,209
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const unsigned char vdpcyc2sl_40[] = { // 68k cycles/4 since HINT to slot #
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static const unsigned char vdpcyc2sl_40[] = { // 68k cycles/4 to slot #
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// 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
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@ -88,8 +88,8 @@ const unsigned char vdpcyc2sl_40[] = { // 68k cycles/4 since HINT to slot #
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13,13,13,13,13,13,14,14,14,14,14,15,15,15,15,15,
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16,16,16,16,16,16,16,16,17,18,18,18,18,18,18,18,
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};
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const unsigned char vdpsl2cyc_40[] = { // slot # to 68k cycles/4 since HINT
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0, 13, 28, 33, 37, 47, 51, 56, 65, 70, 74, 84, 88, 93,102,107,112,120,121,123
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static const unsigned char vdpsl2cyc_40[] = { // slot # to 68k cycles/4
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0, 13, 28, 33, 37, 47, 51, 56, 65, 70, 74, 84, 88, 93,102,107,112,120,121,135
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};
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// NB code assumes fifo_* arrays have size 2^n
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@ -97,51 +97,79 @@ const unsigned char vdpsl2cyc_40[] = { // slot # to 68k cycles/4 since HINT
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static short fifo_data[4], fifo_dx; // XXX must go into save?
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// queued FIFO transfers, ...x = index, ...l = queue length
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// each entry has 2 values: [n]>>2=#writes, [n]&3=flags:2=DMA fill 1=byte access
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// each entry has 2 values: [n]>>3 = #writes, [n]&7 = flags
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static int fifo_queue[8], fifo_qx, fifo_ql; // XXX must go into save?
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unsigned int fifo_total; // total# of pending FIFO entries
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enum { FQ_BYTE = 1, FQ_BGDMA = 2, FQ_FGDMA = 4 }; // queue flags, NB: BYTE = 1!
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unsigned int fifo_total; // total# of pending FIFO entries (w/o BGDMA)
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unsigned short fifo_slot; // last executed slot in current scanline
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// map cycles to FIFO slot
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static __inline int GetFIFOSlot(struct PicoVideo *pv, int cycles)
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{
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int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);
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int h40 = pv->reg[12] & 1;
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if (active) return (h40 ? vdpcyc2sl_40 : vdpcyc2sl_32)[cycles/4];
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else return (cycles * vdpcyc2sl_bl[h40] + cycles) >> 16;
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}
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// map FIFO slot to cycles
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static __inline int GetFIFOCycles(struct PicoVideo *pv, int slot)
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{
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int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);
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int h40 = pv->reg[12] & 1;
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if (active) return (h40 ? vdpsl2cyc_40 : vdpsl2cyc_32)[slot]*4;
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else return ((slot * vdpsl2cyc_bl[h40] + slot) >> 16);
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}
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// do the FIFO math
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static __inline int AdvanceFIFOEntry(struct PicoVideo *pv, int slots)
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{
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int l = slots, b = fifo_queue[fifo_qx&7] & 1;
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int l = slots, b = fifo_queue[fifo_qx] & FQ_BYTE;
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// advance currently active FIFO entry
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if (l > pv->fifo_cnt)
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l = pv->fifo_cnt;
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fifo_total -= ((pv->fifo_cnt & b) + l) >> b;
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if (!(fifo_queue[fifo_qx] & FQ_BGDMA))
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fifo_total -= ((pv->fifo_cnt & b) + l) >> b;
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pv->fifo_cnt -= l;
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// if entry has been processed...
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if (pv->fifo_cnt == 0) {
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if (fifo_ql) {
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// terminate DMA if applicable
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if ((pv->status & SR_DMA) && (fifo_queue[fifo_qx] & FQ_BGDMA)) {
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pv->status &= ~SR_DMA;
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pv->command &= ~0x80;
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}
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// remove entry from FIFO
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fifo_qx ++, fifo_qx &= 7, fifo_ql --;
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}
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// start processing for next entry if there is one
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if (fifo_ql)
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fifo_qx ++, fifo_ql --;
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if (fifo_ql)
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pv->fifo_cnt= (fifo_queue[fifo_qx&7] >> 2) << (fifo_queue[fifo_qx&7] & 1);
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pv->fifo_cnt= (fifo_queue[fifo_qx] >> 3) << (fifo_queue[fifo_qx] & FQ_BYTE);
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else
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fifo_total = 0;
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}
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return l;
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}
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static __inline int GetFIFOSlot(struct PicoVideo *pv, int cycles)
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static __inline void SetFIFOState(struct PicoVideo *pv)
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{
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int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);
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int h40 = pv->reg[12] & 1;
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const unsigned char *cs = h40 ? vdpcyc2sl_40 : vdpcyc2sl_32;
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if (active) return cs[cycles/4];
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else return (cycles * vdpcyc2sl_bl[h40] + cycles) >> 16;
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}
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static __inline int GetFIFOCycles(struct PicoVideo *pv, int slot)
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{
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int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);
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int h40 = pv->reg[12] & 1;
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const unsigned char *sc = h40 ? vdpsl2cyc_40 : vdpsl2cyc_32;
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if (active) return sc[slot]*4;
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else return ((slot * vdpsl2cyc_bl[h40] + slot) >> 16);
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// release CPU and terminate DMA if FIFO isn't blocking the 68k anymore
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if (fifo_total == 0)
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pv->status &= ~PVS_CPURD;
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if (fifo_total <= 4) {
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int x = (fifo_qx + fifo_ql - 1) & 7;
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if ((pv->status & SR_DMA) && !(pv->status & PVS_DMAFILL) &&
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fifo_ql && !(fifo_queue[x] & FQ_BGDMA)) {
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pv->status &= ~SR_DMA;
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pv->command &= ~0x80;
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}
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pv->status &= ~PVS_CPUWR;
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}
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}
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// sync FIFO to cycles
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@ -161,57 +189,40 @@ void PicoVideoFIFOSync(int cycles)
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done -= l;
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}
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// release CPU and terminate DMA if FIFO isn't blocking the 68k anymore
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if (fifo_total <= 4) {
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pv->status &= ~PVS_CPUWR;
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pv->command &= ~0x80;
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if (!(pv->status & PVS_DMAPEND))
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pv->status &= ~(SR_DMA|PVS_DMAFILL);
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}
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if (fifo_total == 0)
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pv->status &= ~PVS_CPURD;
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SetFIFOState(pv);
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}
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// drain FIFO, blocking 68k on the way. FIFO must be synced prior to drain.
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int PicoVideoFIFODrain(int level, int cycles)
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int PicoVideoFIFODrain(int level, int cycles, int bgdma)
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{
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struct PicoVideo *pv = &Pico.video;
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int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);
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int h40 = pv->reg[12] & 1;
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int maxsl = vdpslots[h40 + 2*active]; // max xfer slots in this scanline
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int maxsl = GetFIFOSlot(pv, 488); // max xfer slots in this scanline
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int burn = 0;
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while (fifo_total > level && fifo_slot < maxsl) {
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int b = fifo_queue[fifo_qx&7] & 1;
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int cnt = (fifo_total-level) << b;
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// process FIFO entries until low level is reached
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while (fifo_total > level && fifo_slot < maxsl &&
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(!(fifo_queue[fifo_qx] & FQ_BGDMA) || bgdma)) {
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int b = fifo_queue[fifo_qx] & FQ_BYTE;
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int cnt = ((fifo_total-level) << b) - (pv->fifo_cnt & b);
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int last = fifo_slot;
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int slot = (pv->fifo_cnt<cnt?pv->fifo_cnt:cnt) + last; // target slot
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int slot = (pv->fifo_cnt < cnt ? pv->fifo_cnt : cnt) + last; // target slot
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unsigned ocyc = cycles;
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if (slot > maxsl) {
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// target in later scanline, advance to eol
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slot = maxsl;
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fifo_slot = maxsl;
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cycles = 488;
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} else {
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// advance FIFO to target slot and CPU to cycles at that slot
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fifo_slot = slot;
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cycles = GetFIFOCycles(pv, slot);
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}
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fifo_slot = slot;
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burn += cycles - ocyc;
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AdvanceFIFOEntry(pv, slot - last);
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}
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// release CPU and terminate DMA if FIFO isn't blocking the bus anymore
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if (fifo_total <= 4) {
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pv->status &= ~PVS_CPUWR;
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pv->command &= ~0x80;
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if (!(pv->status & PVS_DMAPEND))
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pv->status &= ~(SR_DMA|PVS_DMAFILL);
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}
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if (fifo_total == 0)
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pv->status &= ~PVS_CPURD;
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SetFIFOState(pv);
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return burn;
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}
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@ -220,13 +231,13 @@ int PicoVideoFIFODrain(int level, int cycles)
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int PicoVideoFIFORead(void)
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{
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struct PicoVideo *pv = &Pico.video;
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int lc = SekCyclesDone()-Pico.t.m68c_line_start+4;
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int lc = SekCyclesDone()-Pico.t.m68c_line_start;
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int burn = 0;
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PicoVideoFIFOSync(lc);
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// advance FIFO and CPU until FIFO is empty
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burn = PicoVideoFIFODrain(0, lc);
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burn = PicoVideoFIFODrain(0, lc, 1);
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lc += burn;
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if (fifo_total > 0)
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pv->status |= PVS_CPURD; // target slot is in later scanline
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@ -243,34 +254,41 @@ int PicoVideoFIFORead(void)
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int PicoVideoFIFOWrite(int count, int flags, unsigned sr_mask,unsigned sr_flags)
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{
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struct PicoVideo *pv = &Pico.video;
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int lc = SekCyclesDone()-Pico.t.m68c_line_start+4;
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int burn = 0;
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int lc = SekCyclesDone()-Pico.t.m68c_line_start;
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int burn = 0, x;
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PicoVideoFIFOSync(lc);
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pv->status = (pv->status & ~sr_mask) | sr_flags;
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if (count && fifo_ql < 8) {
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// update FIFO state if it was empty
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if (fifo_total == 0 && count) {
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fifo_slot = GetFIFOSlot(pv, lc);
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pv->fifo_cnt = count << (flags&1);
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if (fifo_ql == 0) {
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fifo_slot = GetFIFOSlot(pv, lc+10); // FIFO latency ~4 vdp slots
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pv->fifo_cnt = count << (flags & FQ_BYTE);
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}
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// create xfer queue entry
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int x = (fifo_qx + fifo_ql) & 7;
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fifo_queue[x] = (count << 2) | flags;
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x = (fifo_qx + fifo_ql - 1) & 7;
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if (fifo_ql && (fifo_queue[x] & FQ_BGDMA)) {
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// CPU FIFO writes have priority over a background DMA Fill/Copy
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fifo_queue[(x+1) & 7] = fifo_queue[x];
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if (fifo_ql == 1) {
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// XXX if interrupting a DMA fill, fill data changes
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int f = fifo_queue[x] & 7;
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fifo_queue[(x+1) & 7] = (pv->fifo_cnt >> (f & FQ_BYTE) << 3) | f;
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pv->fifo_cnt = count << (flags & FQ_BYTE);
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}
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} else
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x = (x+1) & 7;
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fifo_queue[x] = (count << 3) | flags;
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fifo_ql ++;
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fifo_total += count;
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if (!(flags & FQ_BGDMA))
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fifo_total += count;
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}
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// if CPU is waiting for the bus, advance CPU and FIFO until bus is free
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if ((pv->status & (PVS_CPUWR|PVS_DMAFILL)) == PVS_CPUWR)
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burn = PicoVideoFIFODrain(4, lc);
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else if (fifo_queue[fifo_qx&7]&2) {
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// if interrupting a DMA fill terminate it XXX wrong, changes fill data
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AdvanceFIFOEntry(pv, pv->fifo_cnt);
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pv->status &= ~PVS_DMAFILL;
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}
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if (pv->status & PVS_CPUWR)
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burn = PicoVideoFIFODrain(4, lc, 0);
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return burn;
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}
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@ -287,7 +305,7 @@ int PicoVideoFIFOHint(void)
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// if CPU is waiting for the bus, advance CPU and FIFO until bus is free
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if (pv->status & PVS_CPURD)
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burn = PicoVideoFIFORead();
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if (pv->status & PVS_CPUWR)
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else if (pv->status & PVS_CPUWR)
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burn = PicoVideoFIFOWrite(0, 0, 0, 0);
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return burn;
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@ -297,16 +315,15 @@ int PicoVideoFIFOHint(void)
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void PicoVideoFIFOMode(int active)
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{
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struct PicoVideo *pv = &Pico.video;
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const unsigned char *cs = pv->reg[12]&1 ? vdpcyc2sl_40 : vdpcyc2sl_32;
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int h40 = pv->reg[12] & 1;
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int lc = SekCyclesDone() - Pico.t.m68c_line_start;
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PicoVideoFIFOSync(lc);
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if (fifo_total) {
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if (fifo_ql) {
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// recalculate FIFO slot for new mode
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if (!(pv->status & SR_VB) && active)
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fifo_slot = cs[lc/4];
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fifo_slot = (pv->reg[12]&1 ? vdpcyc2sl_40 : vdpcyc2sl_32)[lc/4];
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else fifo_slot = ((lc * vdpcyc2sl_bl[h40] + lc) >> 16);
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}
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}
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@ -421,8 +438,8 @@ static void DmaSlow(int len, unsigned int source)
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|||
Pico.video.type, source, a, len, inc, (Pico.video.status&SR_VB)||!(Pico.video.reg[1]&0x40),
|
||||
SekCyclesDone(), SekPc);
|
||||
|
||||
SekCyclesBurnRun(PicoVideoFIFOWrite(len, Pico.video.type == 1, PVS_DMAPEND,
|
||||
SR_DMA | PVS_CPUWR) + 8);
|
||||
SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_FGDMA | (Pico.video.type == 1),
|
||||
0, SR_DMA| PVS_CPUWR));
|
||||
|
||||
if ((source & 0xe00000) == 0xe00000) { // Ram
|
||||
base = (u16 *)PicoMem.ram;
|
||||
|
|
@ -546,7 +563,8 @@ static void DmaCopy(int len)
|
|||
int source;
|
||||
elprintf(EL_VDPDMA, "DmaCopy len %i [%u]", len, SekCyclesDone());
|
||||
|
||||
SekCyclesBurnRun(PicoVideoFIFOWrite(len, 1, PVS_CPUWR | PVS_DMAPEND, SR_DMA));
|
||||
SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA | FQ_BYTE,
|
||||
PVS_CPUWR, SR_DMA));
|
||||
|
||||
source =Pico.video.reg[0x15];
|
||||
source|=Pico.video.reg[0x16]<<8;
|
||||
|
|
@ -577,8 +595,8 @@ static NOINLINE void DmaFill(int data)
|
|||
len = GetDmaLength();
|
||||
elprintf(EL_VDPDMA, "DmaFill len %i inc %i [%u]", len, inc, SekCyclesDone());
|
||||
|
||||
SekCyclesBurnRun(PicoVideoFIFOWrite(len, 2|(Pico.video.type == 1),
|
||||
PVS_CPUWR | PVS_DMAPEND, SR_DMA));
|
||||
SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA | (Pico.video.type == 1),
|
||||
PVS_CPUWR | PVS_DMAFILL, SR_DMA));
|
||||
|
||||
switch (Pico.video.type)
|
||||
{
|
||||
|
|
@ -648,7 +666,6 @@ static NOINLINE void CommandDma(void)
|
|||
u32 len, method;
|
||||
u32 source;
|
||||
|
||||
pvid->status |= PVS_DMAPEND;
|
||||
PicoVideoFIFOSync(SekCyclesDone()-Pico.t.m68c_line_start);
|
||||
if (pvid->status & SR_DMA) {
|
||||
elprintf(EL_VDPDMA, "Dma overlap, left=%d @ %06x",
|
||||
|
|
@ -748,12 +765,14 @@ PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d)
|
|||
VideoWrite(d);
|
||||
|
||||
// start DMA fill on write. NB VSRAM and CRAM fills use wrong FIFO data.
|
||||
if ((pvid->status & (PVS_DMAPEND|PVS_DMAFILL)) == (PVS_DMAPEND|PVS_DMAFILL))
|
||||
if (pvid->status & PVS_DMAFILL)
|
||||
DmaFill(fifo_data[(fifo_dx + !!(pvid->type&~0x81))&3]);
|
||||
|
||||
break;
|
||||
|
||||
case 0x04: // Control (command) port 4 or 6
|
||||
if (pvid->status & SR_DMA)
|
||||
SekCyclesBurnRun(PicoVideoFIFORead()); // kludge, flush out running DMA
|
||||
if (pvid->pending)
|
||||
{
|
||||
// Low word of command:
|
||||
|
|
@ -886,14 +905,12 @@ static u32 VideoSr(const struct PicoVideo *pv)
|
|||
unsigned int hp = pv->reg[12]&1 ? 32:40; // HBLANK start
|
||||
unsigned int hl = pv->reg[12]&1 ? 94:84; // HBLANK length
|
||||
|
||||
c = SekCyclesDone();
|
||||
if (c - Pico.t.m68c_line_start - hp < hl)
|
||||
c = SekCyclesDone() - Pico.t.m68c_line_start;
|
||||
if (c - hp < hl)
|
||||
d |= SR_HB;
|
||||
|
||||
PicoVideoFIFOSync(c-Pico.t.m68c_line_start);
|
||||
if (pv->status & SR_DMA)
|
||||
d |= SR_EMPT; // unused by DMA, or rather flags not updated?
|
||||
else if (fifo_total >= 4)
|
||||
PicoVideoFIFOSync(c);
|
||||
if (fifo_total >= 4)
|
||||
d |= SR_FULL;
|
||||
else if (!fifo_total)
|
||||
d |= SR_EMPT;
|
||||
|
|
@ -1010,7 +1027,7 @@ void PicoVideoSave(void)
|
|||
|
||||
// account for all outstanding xfers XXX kludge, entry attr's not saved
|
||||
for (l = fifo_ql, x = fifo_qx + l-1; l > 1; l--, x--)
|
||||
pv->fifo_cnt += (fifo_queue[x&7] >> 2) << (fifo_queue[x&7] & 1);
|
||||
pv->fifo_cnt += (fifo_queue[x&7] >> 2) << (fifo_queue[x&7] & FQ_BYTE);
|
||||
}
|
||||
|
||||
void PicoVideoLoad(void)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue