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sram handling refactored
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@239 be3aeb3a-fb24-0410-a615-afba39da0efa
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notaz
parent
f58f05d28a
commit
7969166ef6
5 changed files with 144 additions and 147 deletions
102
Pico/Memory.c
102
Pico/Memory.c
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@ -144,14 +144,49 @@ int PadRead(int i)
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#ifndef _ASM_MEMORY_C
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// address must already be checked
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static int SRAMRead(u32 a)
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{
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u8 *d = SRam.data-SRam.start+a;
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return (d[0]<<8)|d[1];
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}
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static
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#endif
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u32 SRAMRead(u32 a)
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{
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unsigned int sreg = Pico.m.sram_reg;
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if(!(sreg & 0x10) && (sreg & 1) && a > 0x200001) { // not yet detected SRAM
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Pico.m.sram_reg|=0x10; // should be normal SRAM
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}
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if(sreg & 4) // EEPROM read
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return SRAMReadEEPROM();
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else // if(sreg & 1) // (sreg&5) is one of prerequisites
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return *(u8 *)(SRam.data-SRam.start+a);
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}
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static void SRAMWrite(u32 a, u32 d)
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{
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dprintf("sram_w: %06x, %08x @%06x", a&0xffffff, d, SekPc);
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unsigned int sreg = Pico.m.sram_reg;
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if(!(sreg & 0x10)) {
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// not detected SRAM
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if((a&~1)==0x200000) {
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Pico.m.sram_reg|=4; // this should be a game with EEPROM (like NBA Jam)
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SRam.start=0x200000; SRam.end=SRam.start+1;
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}
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Pico.m.sram_reg|=0x10;
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}
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if(sreg & 4) { // EEPROM write
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if(SekCyclesDoneT()-lastSSRamWrite < 46) {
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// just update pending state
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SRAMUpdPending(a, d);
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} else {
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SRAMWriteEEPROM(sreg>>6); // execute pending
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SRAMUpdPending(a, d);
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lastSSRamWrite = SekCyclesDoneT();
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}
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} else if(!(sreg & 2)) {
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u8 *pm=(u8 *)(SRam.data-SRam.start+a);
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if(*pm != (u8)d) {
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SRam.changed = 1;
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*pm=(u8)d;
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}
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}
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}
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// for nonstandard reads
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#ifndef _ASM_MEMORY_C
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@ -237,32 +272,7 @@ static void OtherWrite8End(u32 a,u32 d,int realsize)
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//if(a==0x200000) dprintf("cc : %02x @ %06x [%i|%i]", d, SekPc, SekCyclesDoneT(), SekCyclesDone());
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//if(a==0x200001) dprintf("w8 : %02x @ %06x [%i]", d, SekPc, SekCyclesDoneT());
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if(a >= SRam.start && a <= SRam.end) {
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dprintf("sram w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);
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unsigned int sreg = Pico.m.sram_reg;
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if(!(sreg & 0x10)) {
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// not detected SRAM
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if((a&~1)==0x200000) {
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Pico.m.sram_reg|=4; // this should be a game with EEPROM (like NBA Jam)
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SRam.start=0x200000; SRam.end=SRam.start+1;
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}
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Pico.m.sram_reg|=0x10;
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}
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if(sreg & 4) { // EEPROM write
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if(SekCyclesDoneT()-lastSSRamWrite < 46) {
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// just update pending state
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SRAMUpdPending(a, d);
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} else {
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SRAMWriteEEPROM(sreg>>6); // execute pending
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SRAMUpdPending(a, d);
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lastSSRamWrite = SekCyclesDoneT();
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}
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} else if(!(sreg & 2)) {
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u8 *pm=(u8 *)(SRam.data-SRam.start+a);
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if(*pm != (u8)d) {
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SRam.changed = 1;
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*pm=(u8)d;
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}
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}
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SRAMWrite(a, d);
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return;
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}
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@ -317,18 +327,9 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead8(u32 a)
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#if !(defined(EMU_C68K) && defined(EMU_M68K))
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// sram
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if(a >= SRam.start && a <= SRam.end) {
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unsigned int sreg = Pico.m.sram_reg;
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if(!(sreg & 0x10) && (sreg & 1) && a > 0x200001) { // not yet detected SRAM
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Pico.m.sram_reg|=0x10; // should be normal SRAM
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}
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if(sreg & 4) { // EEPROM read
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d = SRAMReadEEPROM();
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goto end;
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} else if(sreg & 1) {
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d = *(u8 *)(SRam.data-SRam.start+a);
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goto end;
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}
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if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {
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d = SRAMRead(a);
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goto end;
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}
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#endif
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@ -345,7 +346,7 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead8(u32 a)
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//if ((a&0xe0ffff)==0xe0a9ba+0x69c)
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// dprintf("r8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);
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//if(a==0x200001) dprintf("r8 : %02x @ %06x [%i]", d, SekPc, SekCyclesDoneT());
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//if(a==0x200001||a==0x200000) printf("r8 : %02x [%06x] @ %06x [%i]\n", d, a, SekPc, SekCyclesDoneT());
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//dprintf("r8 : %06x, %02x @%06x [%03i]", a&0xffffff, (u8)d, SekPc, Pico.m.scanline);
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#ifdef __debug_io
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dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);
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@ -369,8 +370,9 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead16(u32 a)
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#if !(defined(EMU_C68K) && defined(EMU_M68K))
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// sram
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if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg & 1)) {
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if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {
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d = SRAMRead(a);
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d |= d<<8;
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goto end;
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}
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#endif
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@ -383,6 +385,7 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead16(u32 a)
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end:
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//if ((a&0xe0ffff)==0xe0AF0E+0x69c||(a&0xe0ffff)==0xe0A9A8+0x69c||(a&0xe0ffff)==0xe0A9AA+0x69c||(a&0xe0ffff)==0xe0A9AC+0x69c)
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// dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);
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//if(a==0x200000) printf("r16: %04x @ %06x [%i]\n", d, SekPc, SekCyclesDoneT());
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#ifdef __debug_io
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dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);
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@ -405,8 +408,9 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead32(u32 a)
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a&=0xfffffe;
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// sram
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if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg & 1)) {
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if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {
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d = (SRAMRead(a)<<16)|SRAMRead(a+2);
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d |= d<<8;
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goto end;
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}
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@ -416,6 +420,7 @@ PICO_INTERNAL_ASM u32 CPU_CALL PicoRead32(u32 a)
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d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);
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end:
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//if(a==0x200000) printf("r32: %08x @ %06x [%i]\n", d, SekPc, SekCyclesDoneT());
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#ifdef __debug_io
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dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);
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#endif
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@ -442,6 +447,7 @@ PICO_INTERNAL_ASM void CPU_CALL PicoWrite8(u32 a,u8 d)
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lastwrite_cyc_d[lwp_cyc++&15] = d;
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#endif
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//if ((a&0xe0ffff)==0xe0a9ba+0x69c)
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//if(a==0x200000||a==0x200001) printf("w8 : %02x [%06x] @ %06x [%i]\n", d, a, SekPc, SekCyclesDoneT());
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// dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);
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if ((a&0xe00000)==0xe00000) { *(u8 *)(Pico.ram+((a^1)&0xffff))=d; return; } // Ram
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@ -462,6 +468,7 @@ void CPU_CALL PicoWrite16(u32 a,u16 d)
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#endif
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//if ((a&0xe0ffff)==0xe0AF0E+0x69c||(a&0xe0ffff)==0xe0A9A8+0x69c||(a&0xe0ffff)==0xe0A9AA+0x69c||(a&0xe0ffff)==0xe0A9AC+0x69c)
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// dprintf("w16: %06x, %04x @%06x", a&0xffffff, d, SekPc);
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//if(a==0x200000) printf("w16: %04x @ %06x [%i]\n", d, SekPc, SekCyclesDoneT());
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if ((a&0xe00000)==0xe00000) { *(u16 *)(Pico.ram+(a&0xfffe))=d; return; } // Ram
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log_io(a, 16, 1);
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@ -478,6 +485,7 @@ static void CPU_CALL PicoWrite32(u32 a,u32 d)
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#if defined(EMU_C68K) && defined(EMU_M68K)
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lastwrite_cyc_d[lwp_cyc++&15] = d;
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#endif
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//if(a==0x200000) printf("w32: %08x @ %06x [%i]\n", d, SekPc, SekCyclesDoneT());
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if ((a&0xe00000)==0xe00000)
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{
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