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https://github.com/RaySollium99/picodrive.git
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32x, finetuning
This commit is contained in:
kub
parent
1fd8f98696
commit
7e940f142e
4 changed files with 41 additions and 43 deletions
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@ -162,15 +162,13 @@ void NOINLINE p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
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sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
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}
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static void sh2s_sync_on_read(SH2 *sh2)
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static void sh2s_sync_on_read(SH2 *sh2, unsigned cycles)
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{
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int cycles;
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if (sh2->poll_cnt != 0)
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return;
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cycles = sh2_cycles_done(sh2);
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if (cycles > 600)
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p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + C_SH2_TO_M68K(sh2, cycles));
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if (p32x_sh2_ready(sh2->other_sh2, cycles-250))
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p32x_sync_other_sh2(sh2, cycles);
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}
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// poll fifo, stores writes to potential addresses used for polling.
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@ -271,8 +269,8 @@ u32 REGPARM(3) p32x_sh2_poll_memory16(unsigned int a, u32 d, SH2 *sh2)
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DRC_SAVE_SR(sh2);
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// is this a synchronisation address?
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if(p[(a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT] & 0x80) {
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sh2s_sync_on_read(sh2);
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cycles = sh2_cycles_done_m68k(sh2);
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sh2s_sync_on_read(sh2, cycles);
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// check poll fifo and sign-extend the result correctly
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d = (s16)sh2_poll_read(a, d, cycles, sh2);
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}
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@ -291,8 +289,8 @@ u32 REGPARM(3) p32x_sh2_poll_memory32(unsigned int a, u32 d, SH2 *sh2)
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DRC_SAVE_SR(sh2);
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// is this a synchronisation address?
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if(p[(a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT] & 0x80) {
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sh2s_sync_on_read(sh2);
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cycles = sh2_cycles_done_m68k(sh2);
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sh2s_sync_on_read(sh2, cycles);
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// check poll fifo and sign-extend the result correctly
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d = (sh2_poll_read(a, d >> 16, cycles, sh2) << 16) |
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((u16)sh2_poll_read(a+2, d, cycles, sh2));
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@ -729,6 +727,7 @@ static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
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static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
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{
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u16 *r = Pico32x.regs;
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unsigned cycles;
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a &= 0x3e;
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switch (a/2) {
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@ -737,8 +736,9 @@ static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
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| Pico32x.sh2irq_mask[sh2->is_slave];
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case 0x04/2: // H count (often as comm too)
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sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 9);
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sh2s_sync_on_read(sh2);
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return sh2_poll_read(a, Pico32x.sh2_regs[4 / 2], sh2_cycles_done_m68k(sh2), sh2);
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cycles = sh2_cycles_done_m68k(sh2);
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sh2s_sync_on_read(sh2, cycles);
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return sh2_poll_read(a, Pico32x.sh2_regs[4 / 2], cycles, sh2);
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case 0x06/2:
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return (r[a / 2] & ~P32XS_FULL) | 0x4000;
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case 0x08/2: // DREQ src
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@ -770,8 +770,9 @@ static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
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case 0x2c/2:
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case 0x2e/2:
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sh2_poll_detect(a, sh2, SH2_STATE_CPOLL, 9);
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sh2s_sync_on_read(sh2);
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return sh2_poll_read(a, r[a / 2], sh2_cycles_done_m68k(sh2), sh2);
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cycles = sh2_cycles_done_m68k(sh2);
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sh2s_sync_on_read(sh2, cycles);
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return sh2_poll_read(a, r[a / 2], cycles, sh2);
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case 0x30/2: // PWM
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case 0x32/2:
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case 0x34/2:
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@ -825,7 +826,7 @@ static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
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unsigned int cycles = sh2_cycles_done_m68k(sh2);
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Pico32x.sh2_regs[4 / 2] = d;
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p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL, cycles);
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if (p32x_sh2_ready(sh2->other_sh2, cycles+16))
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if (p32x_sh2_ready(sh2->other_sh2, cycles+8))
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sh2_end_run(sh2, 4);
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sh2_poll_write(a & ~1, d, cycles, sh2);
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}
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@ -852,7 +853,7 @@ static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
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REG8IN16(r, a) = d;
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p32x_m68k_poll_event(P32XF_68KCPOLL);
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p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL, cycles);
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if (p32x_sh2_ready(sh2->other_sh2, cycles+16))
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if (p32x_sh2_ready(sh2->other_sh2, cycles+8))
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sh2_end_run(sh2, 1);
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sh2_poll_write(a & ~1, r[a / 2], cycles, sh2);
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}
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@ -945,7 +946,7 @@ static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
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Pico32x.regs[a / 2] = d;
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p32x_m68k_poll_event(P32XF_68KCPOLL);
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p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL, cycles);
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if (p32x_sh2_ready(sh2->other_sh2, cycles+16))
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if (p32x_sh2_ready(sh2->other_sh2, cycles+8))
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sh2_end_run(sh2, 1);
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sh2_poll_write(a, d, cycles, sh2);
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}
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@ -1580,7 +1581,7 @@ static void sh2_sdram_poll(u32 a, u32 d, SH2 *sh2)
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cycles = sh2_cycles_done_m68k(sh2);
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sh2_poll_write(a, d, cycles, sh2);
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p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_RPOLL, cycles);
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if (p32x_sh2_ready(sh2->other_sh2, cycles+16))
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if (p32x_sh2_ready(sh2->other_sh2, cycles+8))
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sh2_end_run(sh2, 1);
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DRC_RESTORE_SR(sh2);
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}
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@ -1588,27 +1589,25 @@ static void sh2_sdram_poll(u32 a, u32 d, SH2 *sh2)
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void sh2_sdram_checks(u32 a, u32 d, SH2 *sh2, u32 t)
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{
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if (t & 0x80) sh2_sdram_poll(a, d, sh2);
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if (t & 0x7f) sh2_drc_wcheck_ram(a, t & 0x7f, sh2);
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if (t & 0x7f) sh2_drc_wcheck_ram(a, 2, sh2);
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}
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void sh2_sdram_checks_l(u32 a, u32 d, SH2 *sh2, u32 t)
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{
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u32 m = 0x80 | 0x800000;
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if (t & 0x000080) sh2_sdram_poll(a, d>>16, sh2);
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if (t & 0x800000) sh2_sdram_poll(a+2, d, sh2);
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if (t & ~m) sh2_drc_wcheck_ram(a, t & ~m, sh2);
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if (t & ~0x800080) sh2_drc_wcheck_ram(a, 4, sh2);
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}
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#ifndef _ASM_32X_MEMORY_C
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static void sh2_da_checks(u32 a, u32 t, SH2 *sh2)
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{
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sh2_drc_wcheck_da(a, t, sh2);
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sh2_drc_wcheck_da(a, 2, sh2);
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}
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static void sh2_da_checks_l(u32 a, u32 t, SH2 *sh2)
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{
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sh2_drc_wcheck_da(a, t, sh2);
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sh2_drc_wcheck_da(a, 4, sh2);
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}
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#endif
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#endif
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@ -139,12 +139,11 @@ sh2_write8_sdram:
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mov r3, r3, lsl #SH2_RAM_SHIFT
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strb r1, [ip, r3, lsr #SH2_RAM_SHIFT]
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#ifdef DRC_SH2
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ldr ip, [r2, #OFS_SH2_p_drcblk_ram]
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ldrb r3, [ip, r3, lsr #SH2_RAM_SHIFT+1]
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ldr r1, [r2, #OFS_SH2_p_drcblk_ram]
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ldrb r3, [r1, r3, lsr #SH2_RAM_SHIFT+1]
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cmp r3, #0
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bxeq lr
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@ need to load aligned 16 bit data for check
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ldr ip, [r2, #OFS_SH2_p_sdram]
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bic r0, r0, #1
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mov r1, r0, lsl #SH2_RAM_SHIFT
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mov r1, r1, lsr #SH2_RAM_SHIFT
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@ -166,6 +165,7 @@ sh2_write8_da:
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bic r0, r0, #1
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cmp r1, #0
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bxeq lr
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mov r1, #2
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b sh2_drc_wcheck_da
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#else
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bx lr
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@ -206,6 +206,7 @@ sh2_write16_da:
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ldrb r1, [ip, r3, lsr #1]
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cmp r1, #0
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bxeq lr
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mov r1, #2
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b sh2_drc_wcheck_da
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#else
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bx lr
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@ -256,6 +257,7 @@ sh2_write32_da:
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ldrb ip, [ip, #1]
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orrs r1, r1, ip, lsl #16
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bxeq lr
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mov r1, #4
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b sh2_drc_wcheck_da
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#else
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bx lr
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