mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
32x: m68k memory handler improvemets
did some hw tests today..
This commit is contained in:
notaz
parent
4a1fb18323
commit
7eaa381224
3 changed files with 196 additions and 60 deletions
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@ -9,17 +9,17 @@
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* a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
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* a15102 ........ ......SM ? 4002 // intS intM
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* a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint
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* a15106 F....... .....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
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* a15106 ........ F....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb]
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* a15108 (32bit DREQ src) 4008
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* a1510c (32bit DREQ dst) 400c
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* a15110 llllllll llllll00 4010 // DREQ Len
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* a15112 (16bit FIFO reg) 4012
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* a15114 ? (16bit VRES clr) 4014
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* a15116 ? (16bit Vint clr) 4016
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* a15118 ? (16bit Hint clr) 4018
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* a1511a ........ .......C (16bit CMD clr) 401a // Cm
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* a1511c ? (16bit PWM clr) 401c
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* a1511e ? ? 401e
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* a15114 0 (16bit VRES clr) 4014
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* a15116 0 (16bit Vint clr) 4016
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* a15118 0 (16bit Hint clr) 4018
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* a1511a .......? .......C (16bit CMD clr) 401a // TV Cm
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* a1511c 0 (16bit PWM clr) 401c
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* a1511e 0 ? 401e
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* a15120 (16 bytes comm) 2020
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* a15130 (PWM) 2030
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*
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@ -49,6 +49,9 @@ struct Pico32xMem *Pico32xMem;
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static void bank_switch(int b);
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// addressing byte in 16bit reg
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#define REG8IN16(ptr, offs) ((u8 *)ptr)[(offs) ^ 1]
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// poll detection
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#define POLL_THRESHOLD 3
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@ -219,6 +222,32 @@ out:
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return Pico32x.regs[a / 2];
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}
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static void dreq0_write(u16 *r, u32 d)
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{
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if (!(r[6 / 2] & P32XS_68S)) {
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elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
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return; // ignored - tested
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}
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if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) {
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Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d;
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if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN)
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r[6 / 2] |= P32XS_FULL;
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// tested: len register decrements and 68S clears
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// even if SH2s/DMAC aren't active..
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r[0x10 / 2]--;
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if (r[0x10 / 2] == 0)
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r[6 / 2] &= ~P32XS_68S;
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if ((Pico32x.dmac0_fifo_ptr & 3) == 0) {
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p32x_sync_sh2s(SekCyclesDoneT());
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p32x_dreq0_trigger();
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}
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}
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else
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elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO overflow!");
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}
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// writable bits tested
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static void p32x_reg_write8(u32 a, u32 d)
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{
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u16 *r = Pico32x.regs;
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@ -228,15 +257,18 @@ static void p32x_reg_write8(u32 a, u32 d)
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m68k_poll.cnt = 0;
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switch (a) {
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case 0: // adapter ctl
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r[0] = (r[0] & ~P32XS_FM) | ((d << 8) & P32XS_FM);
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case 0x00: // adapter ctl: FM writable
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REG8IN16(r, 0x00) = d & 0x80;
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return;
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case 1: // adapter ctl, RES bit writeable
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case 0x01: // adapter ctl: RES and ADEN writable
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if ((d ^ r[0]) & d & P32XS_nRES)
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p32x_reset_sh2s();
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r[0] = (r[0] & ~P32XS_nRES) | (d & P32XS_nRES);
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REG8IN16(r, 0x01) &= ~(P32XS_nRES|P32XS_ADEN);
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REG8IN16(r, 0x01) |= d & (P32XS_nRES|P32XS_ADEN);
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return;
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case 3: // irq ctl
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case 0x02: // ignored, always 0
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return;
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case 0x03: // irq ctl
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if ((d & 1) != !!(Pico32x.sh2irqi[0] & P32XI_CMD)) {
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p32x_sync_sh2s(SekCyclesDoneT());
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if (d & 1)
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@ -254,34 +286,124 @@ static void p32x_reg_write8(u32 a, u32 d)
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p32x_update_irls(NULL, SekCyclesDoneT2());
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}
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return;
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case 5: // bank
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d &= 7;
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if (r[4 / 2] != d) {
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r[4 / 2] = d;
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case 0x04: // ignored, always 0
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return;
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case 0x05: // bank
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d &= 3;
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if (r[0x04 / 2] != d) {
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r[0x04 / 2] = d;
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bank_switch(d);
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}
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return;
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case 7: // DREQ ctl
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r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV));
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case 0x06: // ignored, always 0
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return;
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case 0x07: // DREQ ctl
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REG8IN16(r, 0x07) &= ~(P32XS_68S|P32XS_DMA|P32XS_RV);
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if (!(d & P32XS_68S)) {
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Pico32x.dmac0_fifo_ptr = 0;
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REG8IN16(r, 0x07) &= ~P32XS_FULL;
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}
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REG8IN16(r, 0x07) |= d & (P32XS_68S|P32XS_DMA|P32XS_RV);
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return;
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case 0x08: // ignored, always 0
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return;
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case 0x09: // DREQ src
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REG8IN16(r, 0x09) = d;
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return;
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case 0x0a:
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REG8IN16(r, 0x0a) = d;
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return;
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case 0x0b:
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REG8IN16(r, 0x0b) = d & 0xfe;
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return;
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case 0x0c: // ignored, always 0
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return;
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case 0x0d: // DREQ dest
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case 0x0e:
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case 0x0f:
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case 0x10: // DREQ len
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REG8IN16(r, a) = d;
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return;
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case 0x11:
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REG8IN16(r, a) = d & 0xfc;
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return;
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// DREQ FIFO - writes to odd addr go to fifo
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// do writes to even work? Reads return 0
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case 0x12:
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REG8IN16(r, a) = d;
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return;
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case 0x13:
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d = (REG8IN16(r, 0x12) << 8) | (d & 0xff);
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REG8IN16(r, 0x12) = 0;
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dreq0_write(r, d);
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return;
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case 0x14: // ignored, always 0
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case 0x15:
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case 0x16:
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case 0x17:
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case 0x18:
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case 0x19:
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return;
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case 0x1a: // what's this?
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elprintf(EL_32X|EL_ANOMALY, "mystery w8 %02x %02x", a, d);
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REG8IN16(r, a) = d & 0x01;
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return;
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case 0x1b: // TV
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r[0x1a / 2] = d;
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REG8IN16(r, a) = d & 0x01;
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return;
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case 0x1c: // ignored, always 0
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case 0x1d:
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case 0x1e:
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case 0x1f:
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case 0x30:
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return;
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case 0x31: // PWM control
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REG8IN16(r, a) &= ~0x0f;
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REG8IN16(r, a) |= d & 0x0f;
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goto pwm_write;
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case 0x32: // PWM cycle
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REG8IN16(r, a) = d & 0x0f;
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goto pwm_write;
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case 0x33:
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REG8IN16(r, a) = d;
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goto pwm_write;
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// PWM pulse regs.. Only writes to odd address send a value
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// to FIFO; reads are 0 (except status bits)
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case 0x34:
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case 0x36:
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case 0x38:
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REG8IN16(r, a) = d;
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return;
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case 0x35:
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case 0x37:
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case 0x39:
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d = (REG8IN16(r, a) << 8) | (d & 0xff);
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REG8IN16(r, a) = 0;
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goto pwm_write;
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case 0x3a: // ignored, always 0
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case 0x3b:
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case 0x3c:
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case 0x3d:
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case 0x3e:
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case 0x3f:
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return;
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pwm_write:
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p32x_pwm_write16(a & ~1, r[a / 2], NULL, SekCyclesDoneT());
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return;
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}
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if ((a & 0x30) == 0x20) {
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u8 *r8 = (u8 *)r;
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int cycles = SekCyclesDoneT();
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int comreg;
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if (r8[a ^ 1] == d)
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if (REG8IN16(r, a) == d)
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return;
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comreg = 1 << (a & 0x0f) / 2;
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if (Pico32x.comm_dirty_68k & comreg)
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p32x_sync_sh2s(cycles);
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r8[a ^ 1] = d;
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REG8IN16(r, a) = d;
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p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
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p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
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Pico32x.comm_dirty_68k |= comreg;
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@ -304,35 +426,34 @@ static void p32x_reg_write16(u32 a, u32 d)
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case 0x00: // adapter ctl
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if ((d ^ r[0]) & d & P32XS_nRES)
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p32x_reset_sh2s();
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r[0] = (r[0] & ~(P32XS_FM|P32XS_nRES)) | (d & (P32XS_FM|P32XS_nRES));
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r[0] &= ~(P32XS_FM|P32XS_nRES|P32XS_ADEN);
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r[0] |= d & (P32XS_FM|P32XS_nRES|P32XS_ADEN);
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return;
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case 0x08: // DREQ src
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r[a / 2] = d & 0xff;
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return;
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case 0x0a:
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r[a / 2] = d & ~1;
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return;
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case 0x0c: // DREQ dest
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r[a / 2] = d & 0xff;
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return;
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case 0x0e:
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r[a / 2] = d;
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return;
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case 0x10: // DREQ len
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r[a / 2] = d & ~3;
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return;
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case 0x12: // FIFO reg
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if (!(r[6 / 2] & P32XS_68S)) {
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elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
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return;
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}
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if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) {
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Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d;
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if ((Pico32x.dmac0_fifo_ptr & 3) == 0)
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p32x_dreq0_trigger();
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if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN)
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r[6 / 2] |= P32XS_FULL;
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}
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else
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elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO overflow!");
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break;
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dreq0_write(r, d);
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return;
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case 0x1a: // TV + mystery bit
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r[a / 2] = d & 0x0101;
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return;
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}
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// DREQ src, dst
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if ((a & 0x38) == 0x08) {
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r[a / 2] = d;
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return;
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}
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// comm port
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else if ((a & 0x30) == 0x20) {
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if ((a & 0x30) == 0x20) {
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int cycles = SekCyclesDoneT();
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int comreg;
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@ -460,13 +581,30 @@ static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
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sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
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sh2s_sync_on_read(sh2);
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return Pico32x.sh2_regs[4 / 2];
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case 0x06:
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return (r[a / 2] & ~P32XS_FULL) | 0x4000;
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case 0x08: // DREQ src
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case 0x0a:
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case 0x0c: // DREQ dst
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case 0x0e:
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case 0x10: // DREQ len
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return r[a / 2];
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case 0x12: // DREQ FIFO - does this work on hw?
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if (Pico32x.dmac0_fifo_ptr > 0) {
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Pico32x.dmac0_fifo_ptr--;
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r[a / 2] = Pico32x.dmac_fifo[0];
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memmove(&Pico32x.dmac_fifo[0], &Pico32x.dmac_fifo[1],
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Pico32x.dmac0_fifo_ptr * 2);
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}
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return r[a / 2];
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case 0x14:
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case 0x16:
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case 0x18:
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case 0x1a:
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case 0x1c:
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return 0; // ?
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}
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// DREQ src, dst
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if ((a & 0x38) == 0x08)
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return r[a / 2];
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// comm port
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if ((a & 0x30) == 0x20) {
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int comreg = 1 << (a & 0x0f) / 2;
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@ -477,10 +615,11 @@ static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
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sh2s_sync_on_read(sh2);
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return r[a / 2];
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}
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if ((a & 0x30) == 0x30) {
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if ((a & 0x30) == 0x30)
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return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2));
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}
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elprintf_sh2(sh2, EL_32X|EL_ANOMALY,
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"unhandled sysreg r16 [%06x] @%06x", a, SekPc);
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return 0;
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}
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@ -360,13 +360,13 @@ void sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
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/* 32X specific */
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static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
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{
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unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
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unsigned short dreqlen = Pico32x.regs[0x10 / 2];
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int i;
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// debug/sanity checks
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if (chan->tcr != *dreqlen)
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elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0 and len differ: %d != %d",
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chan->tcr, *dreqlen);
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if (chan->tcr < dreqlen || chan->tcr > dreqlen + 4)
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elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0/len inconsistent: %d/%d",
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chan->tcr, dreqlen);
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// note: DACK is not connected, single addr mode should not be used
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if ((chan->chcr & 0x3f08) != 0x0400)
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elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr);
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@ -377,12 +377,11 @@ static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
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sh2->state |= SH2_STATE_SLEEP;
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for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) {
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elprintf(EL_32XP, "dmaw [%08x] %04x, left %d",
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chan->dar, Pico32x.dmac_fifo[i], *dreqlen);
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elprintf(EL_32XP, "dreq0 [%08x] %04x, dreq_len %d",
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chan->dar, Pico32x.dmac_fifo[i], dreqlen);
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p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2);
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chan->dar += 2;
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chan->tcr--;
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(*dreqlen)--;
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}
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if (Pico32x.dmac0_fifo_ptr != i)
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@ -391,8 +390,6 @@ static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
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Pico32x.dmac0_fifo_ptr -= i;
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Pico32x.regs[6 / 2] &= ~P32XS_FULL;
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if (*dreqlen == 0)
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Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
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if (chan->tcr == 0)
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dmac_transfer_complete(sh2, chan);
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else
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@ -489,8 +489,7 @@ typedef struct
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// peripheral reg access
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#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]
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// real one is 4*2, but we use more because we don't lockstep
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#define DMAC_FIFO_LEN (4*4)
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#define DMAC_FIFO_LEN (4*2)
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#define PWM_BUFF_LEN 1024 // in one channel samples
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#define SH2_DRCBLK_RAM_SHIFT 1
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@ -511,9 +510,10 @@ struct Pico32x
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unsigned char sh2irqi[2]; // individual
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unsigned int sh2irqs; // common irqs
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unsigned short dmac_fifo[DMAC_FIFO_LEN];
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unsigned int pad[4];
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unsigned int dmac0_fifo_ptr;
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unsigned short vdp_fbcr_fake;
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unsigned short pad;
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unsigned short pad2;
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unsigned char comm_dirty_68k;
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unsigned char comm_dirty_sh2;
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||||
unsigned char pwm_irq_cnt;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue