various small fixes and optimsations

cpu/drc/emit_arm.c

@@ -1174,6 +1174,8 @@ static inline void emith_pool_adjust(int pool_index, int move_offs)
 #define host_arg2reg(rd, arg) \
 	rd = arg
 
+#define emith_rw_offs_max()	0xff
+
 /* SH2 drc specific */
 /* pushes r12 for eabi alignment */
 #define emith_sh2_drc_entry() \

cpu/drc/emit_arm64.c

@@ -1117,6 +1117,7 @@ static void emith_ldst_offs(int sz, int rd, int rn, int o9, int ld, int mode)
 #define	emith_flush()		/**/
 #define host_instructions_updated(base, end) __builtin___clear_cache(base, end)
 #define emith_jump_patch_size()	8
+#define emith_rw_offs_max()	0xff
 
 
 // SH2 drc specific

cpu/drc/emit_mips.c

@@ -394,7 +394,7 @@ int emith_flg_noV;		// V flag known not to be set
 // NB: for adcf and sbcf, carry-in must be dealt with separately (see there)
 static void emith_set_arith_flags(int rd, int rt, int rs, s32 imm, int sub)
 {
-	if (sub && rd == FNZ && rt && rs)	// is this cmp_r_r?
+	if (sub && rd == FNZ && rt > AT && rs > AT)	// is this cmp_r_r?
 		emith_flg_rs = rs, emith_flg_rt = rt;
 	else	emith_flg_rs = emith_flg_rt = 0;
 
@@ -858,7 +858,7 @@ static void emith_log_imm(int op, int rd, int rs, u32 imm)
 // NB: mips32r2 has EXT and INS
 #define emith_clear_msb(d, s, count) /* bits to clear */ do { \
 	u32 t; \
-	if ((count) > 16) { \
+	if ((count) >= 16) { \
 		t = (count) - 16; \
 		t = 0xffff >> t; \
 		emith_and_r_r_imm(d, s, t); \
@@ -1262,6 +1262,7 @@ static int emith_cond_check(int cond, int *r)
 // NB: mips32r2 has SYNCI
 #define host_instructions_updated(base, end) __builtin___clear_cache(base, end)
 #define emith_jump_patch_size()	4
+#define emith_rw_offs_max()	0x7fff
 
 // SH2 drc specific
 #define emith_sh2_drc_entry() do { \

cpu/drc/emit_x86.c

@@ -986,6 +986,8 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI,	// x86-64,i386 common
 
 #define host_instructions_updated(base, end)
 
+#define emith_rw_offs_max()	0xffffffff
+
 #ifdef __x86_64__
 
 #define HOST_REGS 16

cpu/sh2/compiler.c

@@ -419,8 +419,8 @@ typedef struct {
 static int rcache_get_tmp(void);
 static void rcache_free_tmp(int hr);
 
-// Note: cache_regs[] must have at least the amount of REG and TEMP registers
-// used by handlers in worst case (currently 4). 
+// Note: cache_regs[] must have at least the amount of HRF_REG registers used
+// by handlers in worst case (currently 4). 
 // Register assignment goes by ABI convention. Caller save registers are TEMP,
 // the others are either static or REG. SR must be static, R0 very recommended.
 // VBR, PC, PR must not be static (read from context in utils).
@@ -2418,7 +2418,7 @@ static void rcache_init(void)
 // NB may return either REG or TEMP
 static int emit_get_rbase_and_offs(SH2 *sh2, sh2_reg_e r, int rmode, u32 *offs)
 {
-  uptr omask = 0xff; // offset mask, XXX: ARM oriented..
+  uptr omask = emith_rw_offs_max(); // offset mask
   u32 mask = 0;
   u32 a;
   int poffs;
@@ -4447,7 +4447,7 @@ end_op:
 
 static void sh2_generate_utils(void)
 {
-  int arg0, arg1, arg2, arg3, sr, tmp;
+  int arg0, arg1, arg2, arg3, sr, tmp, tmp2;
 
   host_arg2reg(arg0, 0);
   host_arg2reg(arg1, 1);
@@ -4689,18 +4689,18 @@ static void sh2_generate_utils(void)
   emith_sub_r_imm(tmp, 4*2);
   rcache_clean();
   // push SR
-  tmp = rcache_get_reg_arg(0, SHR_SP, NULL);
-  emith_add_r_imm(tmp, 4);
+  tmp = rcache_get_reg_arg(0, SHR_SP,&tmp2);
+  emith_add_r_r_imm(tmp, tmp2, 4);
   tmp = rcache_get_reg_arg(1, SHR_SR, NULL);
   emith_clear_msb(tmp, tmp, 22);
   emith_move_r_r_ptr(arg2, CONTEXT_REG);
-  rcache_invalidate();
+  rcache_invalidate_tmp();
   emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
   // push PC
   rcache_get_reg_arg(0, SHR_SP, NULL);
   emith_ctx_read(arg1, SHR_PC * 4);
   emith_move_r_r_ptr(arg2, CONTEXT_REG);
-  rcache_invalidate();
+  rcache_invalidate_tmp();
   emith_call(p32x_sh2_write32);
   // update I, cycles, do callback
   emith_ctx_read(arg1, offsetof(SH2, pending_level));