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32x, fix reset interrupt handling

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This commit is contained in:
kub 2024-05-12 10:06:24 +02:00
parent fb79e7baa8
commit 8341673054
5 changed files with 8 additions and 9 deletions
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9
pico/32x/32x.c
View file

@ -44,13 +44,13 @@ void p32x_update_irls(SH2 *active_sh2, unsigned int m68k_cycles)
// find top bit = highest irq number (0 <= irl <= 14/2) by binary search
// msh2
irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[0];
irqs = Pico32x.sh2irqi[0];
if (irqs >= 0x10) mlvl += 8, irqs >>= 4;
if (irqs >= 0x04) mlvl += 4, irqs >>= 2;
if (irqs >= 0x02) mlvl += 2, irqs >>= 1;
// ssh2
irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[1];
irqs = Pico32x.sh2irqi[1];
if (irqs >= 0x10) slvl += 8, irqs >>= 4;
if (irqs >= 0x04) slvl += 4, irqs >>= 2;
if (irqs >= 0x02) slvl += 2, irqs >>= 1;
@ -77,7 +77,8 @@ void p32x_update_irls(SH2 *active_sh2, unsigned int m68k_cycles)
// TODO: test on hw..
void p32x_trigger_irq(SH2 *sh2, unsigned int m68k_cycles, unsigned int mask)
{
Pico32x.sh2irqs |= mask & P32XI_VRES;
Pico32x.sh2irqi[0] |= mask & P32XI_VRES;
Pico32x.sh2irqi[1] |= mask & P32XI_VRES;
Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3);
Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3);
@ -238,8 +239,6 @@ void PicoReset32x(void)
p32x_sh2_poll_event(ssh2.poll_addr, &ssh2, SH2_IDLE_STATES, SekCyclesDone());
p32x_pwm_ctl_changed();
p32x_timers_recalc();
Pico32x.vdp_regs[0] &= ~P32XV_Mx; // 32X graphics disabled
Pico32x.pending_fb = Pico32x.vdp_regs[0x0a/2] & P32XV_FS;
}
}

2
pico/32x/draw.c
View file

@ -10,7 +10,7 @@
// NB: 32X officially doesn't support H32 mode. However, it does work since the
// cartridge slot carries the EDCLK signal which is always H40 clock and is used
// as video clock by the 32X. The H32 MD image is overlayed with the 320 px 32X
// as video clock by the 32X. The H32 MD image is overlaid with the 320 px 32X
// image which has the same on-screen width. How the /YS signal on the cartridge
// slot (signalling the display of background color) is processed in this case
// is however unclear and might lead to glitches due to race conditions by the

2
pico/32x/memory.c
View file

@ -930,7 +930,7 @@ static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
Pico32x.regs[0] |= d & P32XS_FM;
break;
case 0x14/2:
Pico32x.sh2irqs &= ~P32XI_VRES;
Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_VRES;
goto irls;
case 0x16/2:
Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_VINT;

2
pico/debug.c
View file

@ -77,7 +77,7 @@ char *PDebug32x(void)
}
r = Pico32x.sh2_regs;
sprintf(dstrp, "SH: %04x %04x %04x IRQs: %02x eflags: %02x\n",
r[0], r[1], r[2], Pico32x.sh2irqs, Pico32x.emu_flags); MVP;
r[0], r[1], r[2], Pico32x.sh2irqi[0]|Pico32x.sh2irqi[1], Pico32x.emu_flags); MVP;
i = 0;
r = Pico32x.vdp_regs;

2
pico/pico_int.h
View file

@ -641,7 +641,7 @@ struct Pico32x
unsigned int emu_flags;
unsigned char sh2irq_mask[2];
unsigned char sh2irqi[2]; // individual
unsigned int sh2irqs; // common irqs
unsigned int pad4; // was sh2irqs
unsigned short dmac_fifo[DMAC_FIFO_LEN];
unsigned int pad[4];
unsigned int dmac0_fifo_ptr;