mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
32x: drc: finish MAC, gen drc entry/exit (for statically alloced regs)
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@837 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz
parent
20e0619b16
commit
8796b7ee88
7 changed files with 297 additions and 189 deletions
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@ -11,6 +11,7 @@
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#include "compiler.h"
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#include "../drc/cmn.h"
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// debug stuff {
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#ifndef DRC_DEBUG
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#define DRC_DEBUG 0
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#endif
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@ -40,6 +41,7 @@ static char sh2dasm_buff[64];
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#else
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#define do_host_disasm(x)
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#endif
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// } debug
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#define BLOCK_CYCLE_LIMIT 100
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#define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6)
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@ -47,6 +49,7 @@ static char sh2dasm_buff[64];
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// we have 3 translation cache buffers, split from one drc/cmn buffer.
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// BIOS shares tcache with data array because it's only used for init
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// and can be discarded early
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// XXX: need to tune sizes
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static const int tcache_sizes[3] = {
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DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM
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DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
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@ -152,8 +155,8 @@ static int block_counts[3];
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#define HASH_MASK (MAX_HASH_ENTRIES - 1)
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static void **hash_table;
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extern void sh2_drc_entry(SH2 *sh2, void *block);
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extern void sh2_drc_exit(void);
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static void REGPARM(2) (*sh2_drc_entry)(const void *block, SH2 *sh2);
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static void (*sh2_drc_exit)(void);
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// tmp
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extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode);
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@ -503,12 +506,13 @@ static int emit_indirect_indexed_read(int rx, int ry, int size)
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return emit_memhandler_read(size);
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}
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// Rwr -> @(Rx,Ry)
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static void emit_indirect_indexed_write(int rx, int ry, int wr, int size)
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// tmp_wr -> @(Rx,Ry)
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static void emit_indirect_indexed_write(int tmp_wr, int rx, int ry, int size)
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{
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int a0, t;
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rcache_clean();
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rcache_get_reg_arg(1, wr);
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t = rcache_get_tmp_arg(1);
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emith_move_r_r(t, tmp_wr);
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a0 = rcache_get_reg_arg(0, rx);
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t = rcache_get_reg(ry, RC_GR_READ);
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emith_add_r_r(a0, t);
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@ -537,35 +541,57 @@ static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int si
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emith_add_r_imm(tmp, 1 << size);
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}
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// fixup for saturated MAC, to be called from generated code
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// FIXME: statically alloced regs need to be fixed
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static void sh2_macl_sat_fixup(void)
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static void emit_do_static_regs(int is_write, int tmpr)
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{
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if ((signed int)sh2->mach < 0 && sh2->mach < 0xffff8000)
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{
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sh2->mach = 0x00008000;
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sh2->macl = 0x00000000;
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}
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else if ((signed int)sh2->mach > 0 && sh2->mach > 0x00007fff)
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{
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sh2->mach = 0x00007fff;
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sh2->macl = 0xffffffff;
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int i, r, count;
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for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
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r = reg_map_g2h[i];
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if (r == -1)
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continue;
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for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
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if (reg_map_g2h[i + 1] != r + 1)
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break;
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count++;
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}
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if (count > 1) {
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// i, r point to last item
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if (is_write)
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emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
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else
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emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
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} else {
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if (is_write)
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emith_ctx_write(r, i * 4);
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else
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emith_ctx_read(r, i * 4);
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}
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}
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}
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static void sh2_macw_sat_fixup(void)
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static void sh2_generate_utils(void)
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{
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signed int t = sh2->mach;
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if (t < -1 || (t == -1 && !(sh2->macl & 0x80000000)))
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{
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sh2->mach = 0xffffffff; // ?
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sh2->macl = 0x80000000;
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}
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else if (t > 0 || (t == 0 && (sh2->macl & 0x80000000)))
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{
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sh2->mach = 0x7fffffff;
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sh2->macl = 0xffffffff;
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}
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int ctx, blk, tmp;
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host_arg2reg(blk, 0);
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host_arg2reg(ctx, 1);
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host_arg2reg(tmp, 2);
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// sh2_drc_entry(void *block, SH2 *sh2)
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sh2_drc_entry = (void *)tcache_ptr;
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emith_sh2_drc_entry();
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emith_move_r_r(CONTEXT_REG, ctx); // move ctx, arg1
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emit_do_static_regs(0, tmp);
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emith_jump_reg(blk); // jump arg0
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// sh2_drc_exit(void)
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sh2_drc_exit = (void *)tcache_ptr;
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emit_do_static_regs(1, tmp);
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emith_sh2_drc_exit();
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rcache_invalidate();
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}
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#define DELAYED_OP \
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@ -697,7 +723,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
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case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
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case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
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emit_indirect_indexed_write(SHR_R0, GET_Rn(), GET_Rm(), op & 3);
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tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
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emit_indirect_indexed_write(tmp, SHR_R0, GET_Rn(), op & 3);
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goto end_op;
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case 0x07:
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// MUL.L Rm,Rn 0000nnnnmmmm0111
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@ -712,12 +739,12 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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switch (GET_Fx())
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{
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case 0: // CLRT 0000000000001000
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tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
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emith_bic_r_imm(tmp, T);
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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emith_bic_r_imm(sr, T);
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break;
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case 1: // SETT 0000000000011000
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tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
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emith_or_r_imm(tmp, T);
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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emith_or_r_imm(sr, T);
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break;
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case 2: // CLRMAC 0000000000101000
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tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
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@ -737,13 +764,13 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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break;
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case 1: // DIV0U 0000000000011001
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CHECK_UNHANDLED_BITS(0xf00);
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tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
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emith_bic_r_imm(tmp, M|Q|T);
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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emith_bic_r_imm(sr, M|Q|T);
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break;
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case 2: // MOVT Rn 0000nnnn00101001
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tmp = rcache_get_reg(SHR_SR, RC_GR_READ);
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sr = rcache_get_reg(SHR_SR, RC_GR_READ);
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tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
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emith_clear_msb(tmp2, tmp, 31);
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emith_clear_msb(tmp2, sr, 31);
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break;
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default:
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goto default_;
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@ -822,24 +849,34 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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goto end_op;
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case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
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emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
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tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ);
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sr = rcache_get_reg(SHR_SR, RC_GR_READ);
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tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
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/* MS 16 MAC bits unused if saturated */
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emith_tst_r_imm(tmp3, S);
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emith_tst_r_imm(sr, S);
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EMITH_SJMP_START(DCOND_EQ);
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emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
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EMITH_SJMP_END(DCOND_EQ);
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tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
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emith_mula_s64(tmp3, tmp4, tmp, tmp2);
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rcache_free_tmp(tmp);
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rcache_free_tmp(tmp2);
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rcache_clean();
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tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ);
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emith_tst_r_imm(tmp3, S);
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EMITH_SJMP_START(DCOND_EQ);
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emith_call_cond(DCOND_NE, sh2_macl_sat_fixup);
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EMITH_SJMP_END(DCOND_EQ);
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rcache_invalidate();
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sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
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emith_tst_r_imm(sr, S);
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EMITH_JMP_START(DCOND_EQ);
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emith_asr(tmp, tmp4, 15);
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emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
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EMITH_SJMP_START(DCOND_GE);
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emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
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emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
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EMITH_SJMP_END(DCOND_GE);
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emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
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EMITH_SJMP_START(DCOND_LE);
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emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
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emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
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EMITH_SJMP_END(DCOND_LE);
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EMITH_JMP_END(DCOND_EQ);
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rcache_free_tmp(tmp);
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cycles += 3;
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goto end_op;
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}
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@ -877,30 +914,30 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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emit_memhandler_write(op & 3);
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goto end_op;
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case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
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tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
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tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
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emith_bic_r_imm(tmp, M|Q|T);
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emith_bic_r_imm(sr, M|Q|T);
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emith_tst_r_imm(tmp2, (1<<31));
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EMITH_SJMP_START(DCOND_EQ);
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emith_or_r_imm_c(DCOND_NE, tmp, Q);
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emith_or_r_imm_c(DCOND_NE, sr, Q);
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EMITH_SJMP_END(DCOND_EQ);
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emith_tst_r_imm(tmp3, (1<<31));
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EMITH_SJMP_START(DCOND_EQ);
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emith_or_r_imm_c(DCOND_NE, tmp, M);
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emith_or_r_imm_c(DCOND_NE, sr, M);
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EMITH_SJMP_END(DCOND_EQ);
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emith_teq_r_r(tmp2, tmp3);
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EMITH_SJMP_START(DCOND_PL);
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emith_or_r_imm_c(DCOND_MI, tmp, T);
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emith_or_r_imm_c(DCOND_MI, sr, T);
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EMITH_SJMP_END(DCOND_PL);
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goto end_op;
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case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
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tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
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tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
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emith_bic_r_imm(tmp, T);
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emith_bic_r_imm(sr, T);
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emith_tst_r_r(tmp2, tmp3);
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emit_or_t_if_eq(tmp);
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emit_or_t_if_eq(sr);
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goto end_op;
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case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
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tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
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@ -922,8 +959,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
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tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
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emith_eor_r_r_r(tmp, tmp2, tmp3);
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tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
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emith_bic_r_imm(tmp2, T);
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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emith_bic_r_imm(sr, T);
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emith_tst_r_imm(tmp, 0x000000ff);
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emit_or_t_if_eq(tmp);
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emith_tst_r_imm(tmp, 0x0000ff00);
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@ -971,34 +1008,34 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
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case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
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case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
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tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
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tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
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emith_bic_r_imm(tmp, T);
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emith_bic_r_imm(sr, T);
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emith_cmp_r_r(tmp2, tmp3);
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switch (op & 0x07)
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{
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case 0x00: // CMP/EQ
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emit_or_t_if_eq(tmp);
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emit_or_t_if_eq(sr);
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break;
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case 0x02: // CMP/HS
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EMITH_SJMP_START(DCOND_LO);
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emith_or_r_imm_c(DCOND_HS, tmp, T);
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emith_or_r_imm_c(DCOND_HS, sr, T);
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EMITH_SJMP_END(DCOND_LO);
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break;
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case 0x03: // CMP/GE
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EMITH_SJMP_START(DCOND_LT);
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emith_or_r_imm_c(DCOND_GE, tmp, T);
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emith_or_r_imm_c(DCOND_GE, sr, T);
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EMITH_SJMP_END(DCOND_LT);
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break;
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case 0x06: // CMP/HI
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EMITH_SJMP_START(DCOND_LS);
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emith_or_r_imm_c(DCOND_HI, tmp, T);
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emith_or_r_imm_c(DCOND_HI, sr, T);
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EMITH_SJMP_END(DCOND_LS);
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break;
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case 0x07: // CMP/GT
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EMITH_SJMP_START(DCOND_LE);
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emith_or_r_imm_c(DCOND_GT, tmp, T);
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emith_or_r_imm_c(DCOND_GT, sr, T);
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EMITH_SJMP_END(DCOND_LE);
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break;
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}
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@ -1055,29 +1092,29 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
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case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
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tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
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tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
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tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW);
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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if (op & 4) { // adc
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emith_set_carry(tmp3);
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emith_set_carry(sr);
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emith_adcf_r_r(tmp, tmp2);
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emith_carry_to_t(tmp3, 0);
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emith_carry_to_t(sr, 0);
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} else {
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emith_set_carry_sub(tmp3);
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emith_set_carry_sub(sr);
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emith_sbcf_r_r(tmp, tmp2);
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emith_carry_to_t(tmp3, 1);
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emith_carry_to_t(sr, 1);
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}
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goto end_op;
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case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
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case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
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tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
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tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
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tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW);
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emith_bic_r_imm(tmp3, T);
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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emith_bic_r_imm(sr, T);
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if (op & 4) {
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emith_addf_r_r(tmp, tmp2);
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} else
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emith_subf_r_r(tmp, tmp2);
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EMITH_SJMP_START(DCOND_VC);
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emith_or_r_imm_c(DCOND_VS, tmp3, T);
|
||||
emith_or_r_imm_c(DCOND_VS, sr, T);
|
||||
EMITH_SJMP_END(DCOND_VC);
|
||||
goto end_op;
|
||||
case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
|
||||
|
|
@ -1099,10 +1136,10 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
{
|
||||
case 0: // SHLL Rn 0100nnnn00000000
|
||||
case 2: // SHAL Rn 0100nnnn00100000
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_lslf(tmp, tmp, 1);
|
||||
emith_carry_to_t(tmp2, 0);
|
||||
emith_carry_to_t(sr, 0);
|
||||
goto end_op;
|
||||
case 1: // DT Rn 0100nnnn00010000
|
||||
if (p32x_sh2_read16(pc, sh2) == 0x8bfd) { // BF #-2
|
||||
|
|
@ -1110,10 +1147,10 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
goto end_op;
|
||||
}
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_bic_r_imm(tmp2, T);
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_bic_r_imm(sr, T);
|
||||
emith_subf_r_imm(tmp, 1);
|
||||
emit_or_t_if_eq(tmp2);
|
||||
emit_or_t_if_eq(sr);
|
||||
goto end_op;
|
||||
}
|
||||
goto default_;
|
||||
|
|
@ -1122,21 +1159,21 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
{
|
||||
case 0: // SHLR Rn 0100nnnn00000001
|
||||
case 2: // SHAR Rn 0100nnnn00100001
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
if (op & 0x20) {
|
||||
emith_asrf(tmp, tmp, 1);
|
||||
} else
|
||||
emith_lsrf(tmp, tmp, 1);
|
||||
emith_carry_to_t(tmp2, 0);
|
||||
emith_carry_to_t(sr, 0);
|
||||
goto end_op;
|
||||
case 1: // CMP/PZ Rn 0100nnnn00010001
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_bic_r_imm(tmp2, T);
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_bic_r_imm(sr, T);
|
||||
emith_cmp_r_imm(tmp, 0);
|
||||
EMITH_SJMP_START(DCOND_LT);
|
||||
emith_or_r_imm_c(DCOND_GE, tmp2, T);
|
||||
emith_or_r_imm_c(DCOND_GE, sr, T);
|
||||
EMITH_SJMP_END(DCOND_LT);
|
||||
goto end_op;
|
||||
}
|
||||
|
|
@ -1181,32 +1218,32 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
{
|
||||
case 0x04: // ROTL Rn 0100nnnn00000100
|
||||
case 0x05: // ROTR Rn 0100nnnn00000101
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
if (op & 1) {
|
||||
emith_rorf(tmp, tmp, 1);
|
||||
} else
|
||||
emith_rolf(tmp, tmp, 1);
|
||||
emith_carry_to_t(tmp2, 0);
|
||||
emith_carry_to_t(sr, 0);
|
||||
goto end_op;
|
||||
case 0x24: // ROTCL Rn 0100nnnn00100100
|
||||
case 0x25: // ROTCR Rn 0100nnnn00100101
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_set_carry(tmp2);
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_set_carry(sr);
|
||||
if (op & 1) {
|
||||
emith_rorcf(tmp);
|
||||
} else
|
||||
emith_rolcf(tmp);
|
||||
emith_carry_to_t(tmp2, 0);
|
||||
emith_carry_to_t(sr, 0);
|
||||
goto end_op;
|
||||
case 0x15: // CMP/PL Rn 0100nnnn00010101
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_bic_r_imm(tmp2, T);
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_bic_r_imm(sr, T);
|
||||
emith_cmp_r_imm(tmp, 0);
|
||||
EMITH_SJMP_START(DCOND_LE);
|
||||
emith_or_r_imm_c(DCOND_GT, tmp2, T);
|
||||
emith_or_r_imm_c(DCOND_GT, sr, T);
|
||||
EMITH_SJMP_END(DCOND_LE);
|
||||
goto end_op;
|
||||
}
|
||||
|
|
@ -1310,11 +1347,11 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
// XXX: is TAS working on 32X?
|
||||
rcache_clean();
|
||||
rcache_get_reg_arg(0, GET_Rn());
|
||||
tmp = emit_memhandler_read(0);
|
||||
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_bic_r_imm(tmp2, T);
|
||||
tmp = emit_memhandler_read(0);
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_bic_r_imm(sr, T);
|
||||
emith_cmp_r_imm(tmp, 0);
|
||||
emit_or_t_if_eq(tmp2);
|
||||
emit_or_t_if_eq(sr);
|
||||
rcache_clean();
|
||||
emith_or_r_imm(tmp, 0x80);
|
||||
tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
|
||||
|
|
@ -1360,16 +1397,24 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
|
||||
tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
|
||||
emith_mula_s64(tmp3, tmp4, tmp, tmp2);
|
||||
rcache_free_tmp(tmp);
|
||||
rcache_free_tmp(tmp2);
|
||||
rcache_clean();
|
||||
// XXX: MACH should be untouched when S is set?
|
||||
tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ);
|
||||
emith_tst_r_imm(tmp3, S);
|
||||
EMITH_SJMP_START(DCOND_EQ);
|
||||
emith_call_cond(DCOND_NE, sh2_macw_sat_fixup);
|
||||
EMITH_SJMP_END(DCOND_EQ);
|
||||
rcache_invalidate();
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_READ);
|
||||
emith_tst_r_imm(sr, S);
|
||||
EMITH_JMP_START(DCOND_EQ);
|
||||
|
||||
emith_asr(tmp, tmp3, 31);
|
||||
emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
|
||||
EMITH_JMP_START(DCOND_EQ);
|
||||
emith_move_r_imm(tmp3, 0x80000000);
|
||||
emith_tst_r_r(tmp4, tmp4);
|
||||
EMITH_SJMP_START(DCOND_MI);
|
||||
emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
|
||||
EMITH_SJMP_END(DCOND_MI);
|
||||
EMITH_JMP_END(DCOND_EQ);
|
||||
|
||||
EMITH_JMP_END(DCOND_EQ);
|
||||
rcache_free_tmp(tmp);
|
||||
cycles += 2;
|
||||
goto end_op;
|
||||
}
|
||||
|
|
@ -1441,10 +1486,10 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
emith_rol(tmp2, tmp, 16);
|
||||
break;
|
||||
case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
|
||||
tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_set_carry_sub(tmp3);
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_set_carry_sub(sr);
|
||||
emith_negcf_r_r(tmp2, tmp);
|
||||
emith_carry_to_t(tmp3, 1);
|
||||
emith_carry_to_t(sr, 1);
|
||||
break;
|
||||
case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
|
||||
emith_neg_r_r(tmp2, tmp);
|
||||
|
|
@ -1504,11 +1549,11 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
// XXX: could use cmn
|
||||
tmp = rcache_get_tmp();
|
||||
tmp2 = rcache_get_reg(0, RC_GR_READ);
|
||||
tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_move_r_imm_s8(tmp, op & 0xff);
|
||||
emith_bic_r_imm(tmp3, T);
|
||||
emith_bic_r_imm(sr, T);
|
||||
emith_cmp_r_r(tmp2, tmp);
|
||||
emit_or_t_if_eq(tmp3);
|
||||
emit_or_t_if_eq(sr);
|
||||
rcache_free_tmp(tmp);
|
||||
goto end_op;
|
||||
case 0x0d00: // BT/S label 10001101dddddddd
|
||||
|
|
@ -1626,11 +1671,11 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3);
|
||||
goto end_op;
|
||||
case 0x0800: // TST #imm,R0 11001000iiiiiiii
|
||||
tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
|
||||
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_bic_r_imm(tmp2, T);
|
||||
tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_bic_r_imm(sr, T);
|
||||
emith_tst_r_imm(tmp, op & 0xff);
|
||||
emit_or_t_if_eq(tmp2);
|
||||
emit_or_t_if_eq(sr);
|
||||
goto end_op;
|
||||
case 0x0900: // AND #imm,R0 11001001iiiiiiii
|
||||
tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
|
||||
|
|
@ -1645,30 +1690,33 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
|
|||
emith_or_r_imm(tmp, op & 0xff);
|
||||
goto end_op;
|
||||
case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
|
||||
tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
|
||||
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_bic_r_imm(tmp2, T);
|
||||
tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
|
||||
emith_bic_r_imm(sr, T);
|
||||
emith_tst_r_imm(tmp, op & 0xff);
|
||||
emit_or_t_if_eq(tmp2);
|
||||
emit_or_t_if_eq(sr);
|
||||
rcache_free_tmp(tmp);
|
||||
cycles += 2;
|
||||
goto end_op;
|
||||
case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
|
||||
tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
|
||||
emith_and_r_imm(tmp, op & 0xff);
|
||||
emit_indirect_indexed_write(SHR_R0, SHR_GBR, tmp, 0);
|
||||
cycles += 2;
|
||||
goto end_op;
|
||||
goto end_rmw_op;
|
||||
case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
|
||||
tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
|
||||
emith_eor_r_imm(tmp, op & 0xff);
|
||||
emit_indirect_indexed_write(SHR_R0, SHR_GBR, tmp, 0);
|
||||
cycles += 2;
|
||||
goto end_op;
|
||||
goto end_rmw_op;
|
||||
case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
|
||||
tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
|
||||
emith_or_r_imm(tmp, op & 0xff);
|
||||
emit_indirect_indexed_write(SHR_R0, SHR_GBR, tmp, 0);
|
||||
end_rmw_op:
|
||||
tmp2 = rcache_get_tmp_arg(1);
|
||||
emith_move_r_r(tmp2, tmp);
|
||||
rcache_free_tmp(tmp);
|
||||
tmp3 = rcache_get_reg_arg(0, SHR_GBR);
|
||||
tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
|
||||
emith_add_r_r(tmp3, tmp4);
|
||||
emit_memhandler_write(0);
|
||||
cycles += 2;
|
||||
goto end_op;
|
||||
}
|
||||
|
|
@ -1837,7 +1885,7 @@ void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2)
|
|||
if (bd != NULL)
|
||||
bd->refcount++;
|
||||
#endif
|
||||
sh2_drc_entry(sh2, block);
|
||||
sh2_drc_entry(block, sh2);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1969,8 +2017,11 @@ int sh2_drc_init(SH2 *sh2)
|
|||
if (block_tables[0] == NULL)
|
||||
return -1;
|
||||
|
||||
tcache_ptr = tcache;
|
||||
sh2_generate_utils();
|
||||
|
||||
memset(block_counts, 0, sizeof(block_counts));
|
||||
tcache_bases[0] = tcache_ptrs[0] = tcache;
|
||||
tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
|
||||
|
||||
for (i = 1; i < ARRAY_SIZE(block_tables); i++) {
|
||||
block_tables[i] = block_tables[i - 1] + block_max_counts[i - 1];
|
||||
|
|
@ -1983,6 +2034,9 @@ int sh2_drc_init(SH2 *sh2)
|
|||
#if (DRC_DEBUG & 2)
|
||||
for (i = 0; i < ARRAY_SIZE(block_tables); i++)
|
||||
tcache_dsm_ptrs[i] = tcache_bases[i];
|
||||
// disasm the utils
|
||||
tcache_dsm_ptrs[0] = tcache;
|
||||
do_host_disasm(0);
|
||||
#endif
|
||||
#if (DRC_DEBUG & 1)
|
||||
hash_collisions = 0;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue