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32x: drc: finish MAC, gen drc entry/exit (for statically alloced regs)

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git-svn-id: file:///home/notaz/opt/svn/PicoDrive@837 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz 2009-12-07 12:30:56 +00:00
parent 20e0619b16
commit 8796b7ee88
7 changed files with 297 additions and 189 deletions
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83
cpu/drc/emit_arm.c
View file

@ -24,6 +24,7 @@
#define A_R10M (1 << 10) #define A_R10M (1 << 10)
#define A_R11M (1 << 11) #define A_R11M (1 << 11)
#define A_R14M (1 << 14) #define A_R14M (1 << 14)
#define A_R15M (1 << 15)
#define A_COND_AL 0xe #define A_COND_AL 0xe
#define A_COND_EQ 0x0 #define A_COND_EQ 0x0
@ -81,6 +82,7 @@
#define A_OP_TST 0x8 #define A_OP_TST 0x8
#define A_OP_TEQ 0x9 #define A_OP_TEQ 0x9
#define A_OP_CMP 0xa #define A_OP_CMP 0xa
#define A_OP_CMN 0xa
#define A_OP_ORR 0xc #define A_OP_ORR 0xc
#define A_OP_MOV 0xd #define A_OP_MOV 0xd
#define A_OP_BIC 0xe #define A_OP_BIC 0xe
@ -180,8 +182,8 @@
#define EOP_XXM(cond,p,u,s,w,l,rn,list) \ #define EOP_XXM(cond,p,u,s,w,l,rn,list) \
EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list)) EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list))
#define EOP_STMFD_ST(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list) #define EOP_STMFD(rb,list) EOP_XXM(A_COND_AL,1,0,0,1,0,rb,list)
#define EOP_LDMFD_ST(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list) #define EOP_LDMFD(rb,list) EOP_XXM(A_COND_AL,0,1,0,1,1,rb,list)
/* branches */ /* branches */
#define EOP_C_BX(cond,rm) \ #define EOP_C_BX(cond,rm) \
@ -232,9 +234,13 @@ static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int
int ror2; int ror2;
u32 v; u32 v;
if (op == A_OP_MOV) if (op == A_OP_MOV) {
rn = 0; rn = 0;
else if (imm == 0) if (~imm < 0x100) {
imm = ~imm;
op = A_OP_MVN;
}
} else if (imm == 0)
return; return;
for (v = imm, ror2 = 0; v != 0 || op == A_OP_MOV; v >>= 8, ror2 -= 8/2) { for (v = imm, ror2 = 0; v != 0 || op == A_OP_MOV; v >>= 8, ror2 -= 8/2) {
@ -294,6 +300,22 @@ static int emith_xbranch(int cond, void *target, int is_call)
return (u32 *)tcache_ptr - start_ptr; return (u32 *)tcache_ptr - start_ptr;
} }
#define JMP_POS(ptr) \
ptr = tcache_ptr; \
tcache_ptr += sizeof(u32)
#define JMP_EMIT(cond, ptr) { \
int val = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \
EOP_C_B_PTR(ptr, cond, 0, val & 0xffffff); \
}
#define EMITH_JMP_START(cond) { \
void *cond_ptr; \
JMP_POS(cond_ptr)
#define EMITH_JMP_END(cond) \
JMP_EMIT(cond, cond_ptr); \
}
// fake "simple" or "short" jump - using cond insns instead // fake "simple" or "short" jump - using cond insns instead
#define EMITH_SJMP_START(cond) \ #define EMITH_SJMP_START(cond) \
@ -365,6 +387,9 @@ static int emith_xbranch(int cond, void *target, int is_call)
#define emith_sbcf_r_r(d, s) \ #define emith_sbcf_r_r(d, s) \
EOP_SBC_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0) EOP_SBC_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
#define emith_eorf_r_r(d, s) \
EOP_EOR_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
#define emith_move_r_imm(r, imm) \ #define emith_move_r_imm(r, imm) \
emith_op_imm(A_COND_AL, 0, A_OP_MOV, r, imm) emith_op_imm(A_COND_AL, 0, A_OP_MOV, r, imm)
@ -390,12 +415,21 @@ static int emith_xbranch(int cond, void *target, int is_call)
#define emith_tst_r_imm(r, imm) \ #define emith_tst_r_imm(r, imm) \
emith_top_imm(A_COND_AL, A_OP_TST, r, imm) emith_top_imm(A_COND_AL, A_OP_TST, r, imm)
#define emith_cmp_r_imm(r, imm) \ #define emith_cmp_r_imm(r, imm) { \
emith_top_imm(A_COND_AL, A_OP_CMP, r, imm) u32 op = A_OP_CMP, imm_ = imm; \
if (~imm_ < 0x100) { \
imm_ = ~imm_; \
op = A_OP_CMN; \
} \
emith_top_imm(A_COND_AL, op, r, imm); \
}
#define emith_subf_r_imm(r, imm) \ #define emith_subf_r_imm(r, imm) \
emith_op_imm(A_COND_AL, 1, A_OP_SUB, r, imm) emith_op_imm(A_COND_AL, 1, A_OP_SUB, r, imm)
#define emith_move_r_imm_c(cond, r, imm) \
emith_op_imm(cond, 0, A_OP_MOV, r, imm)
#define emith_add_r_imm_c(cond, r, imm) \ #define emith_add_r_imm_c(cond, r, imm) \
emith_op_imm(cond, 0, A_OP_ADD, r, imm) emith_op_imm(cond, 0, A_OP_ADD, r, imm)
@ -430,6 +464,9 @@ static int emith_xbranch(int cond, void *target, int is_call)
#define emith_lsr(d, s, cnt) \ #define emith_lsr(d, s, cnt) \
EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSR,cnt) EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSR,cnt)
#define emith_asr(d, s, cnt) \
EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ASR,cnt)
#define emith_ror(d, s, cnt) \ #define emith_ror(d, s, cnt) \
EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,cnt) EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,cnt)
@ -484,9 +521,25 @@ static int emith_xbranch(int cond, void *target, int is_call)
#define emith_ctx_read(r, offs) \ #define emith_ctx_read(r, offs) \
EOP_LDR_IMM(r, CONTEXT_REG, offs) EOP_LDR_IMM(r, CONTEXT_REG, offs)
#define emith_ctx_read_multiple(r, offs, count, tmpr) do { \
int v_, r_ = r, c_ = count; \
for (v_ = 0; c_; c_--, r_++) \
v_ |= 1 << r_; \
EOP_ADD_IMM(tmpr,CONTEXT_REG,30/2,(offs)>>2); \
EOP_LDMFD(tmpr,v_); \
} while(0)
#define emith_ctx_write(r, offs) \ #define emith_ctx_write(r, offs) \
EOP_STR_IMM(r, CONTEXT_REG, offs) EOP_STR_IMM(r, CONTEXT_REG, offs)
#define emith_ctx_write_multiple(r, offs, count, tmpr) do { \
int v_, r_ = r, c_ = count; \
for (v_ = 0; c_; c_--, r_++) \
v_ |= 1 << r_; \
EOP_ADD_IMM(tmpr,CONTEXT_REG,30/2,(offs)>>2); \
EOP_STMFD(tmpr,v_); \
} while(0)
#define emith_clear_msb_c(cond, d, s, count) { \ #define emith_clear_msb_c(cond, d, s, count) { \
u32 t; \ u32 t; \
if ((count) <= 8) { \ if ((count) <= 8) { \
@ -513,15 +566,6 @@ static int emith_xbranch(int cond, void *target, int is_call)
EOP_MOV_REG_ASR(d,d,32 - (bits)); \ EOP_MOV_REG_ASR(d,d,32 - (bits)); \
} }
#define JMP_POS(ptr) \
ptr = tcache_ptr; \
tcache_ptr += sizeof(u32)
#define JMP_EMIT(cond, ptr) { \
int val = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \
EOP_C_B_PTR(ptr, cond, 0, val & 0xffffff); \
}
// _r_r // _r_r
// put bit0 of r0 to carry // put bit0 of r0 to carry
#define emith_set_carry(r0) \ #define emith_set_carry(r0) \
@ -557,7 +601,16 @@ static int emith_xbranch(int cond, void *target, int is_call)
#define emith_jump(target) \ #define emith_jump(target) \
emith_jump_cond(A_COND_AL, target) emith_jump_cond(A_COND_AL, target)
#define emith_jump_reg(r) \
EOP_BX(r)
/* SH2 drc specific */ /* SH2 drc specific */
#define emith_sh2_drc_entry() \
EOP_STMFD(13,A_R7M|A_R14M)
#define emith_sh2_drc_exit() \
EOP_LDMFD(13,A_R7M|A_R15M)
#define emith_sh2_test_t() { \ #define emith_sh2_test_t() { \
int r = rcache_get_reg(SHR_SR, RC_GR_READ); \ int r = rcache_get_reg(SHR_SR, RC_GR_READ); \
EOP_TST_IMM(r, 0, 1); \ EOP_TST_IMM(r, 0, 1); \

49
cpu/drc/emit_x86.c
View file

@ -202,6 +202,11 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
emith_arith_r_imm(4, r, ~(imm)) emith_arith_r_imm(4, r, ~(imm))
// fake conditionals (using SJMP instead) // fake conditionals (using SJMP instead)
#define emith_move_r_imm_c(cond, r, imm) { \
(void)(cond); \
emith_move_r_imm(r, imm); \
}
#define emith_add_r_imm_c(cond, r, imm) { \ #define emith_add_r_imm_c(cond, r, imm) { \
(void)(cond); \ (void)(cond); \
emith_add_r_imm(r, imm); \ emith_add_r_imm(r, imm); \
@ -365,6 +370,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
#define emith_subf_r_r emith_sub_r_r #define emith_subf_r_r emith_sub_r_r
#define emith_adcf_r_r emith_adc_r_r #define emith_adcf_r_r emith_adc_r_r
#define emith_sbcf_r_r emith_sbc_r_r #define emith_sbcf_r_r emith_sbc_r_r
#define emith_eorf_r_r emith_eor_r_r
#define emith_negcf_r_r emith_negc_r_r #define emith_negcf_r_r emith_negc_r_r
#define emith_lslf emith_lsl #define emith_lslf emith_lsl
@ -376,15 +382,27 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
#define emith_rorcf emith_rorc #define emith_rorcf emith_rorc
// XXX: offs is 8bit only // XXX: offs is 8bit only
#define emith_ctx_read(r, offs) { \ #define emith_ctx_read(r, offs) do { \
EMIT_OP_MODRM(0x8b, 1, r, xBP); \ EMIT_OP_MODRM(0x8b, 1, r, xBP); \
EMIT(offs, u8); /* mov tmp, [ebp+#offs] */ \ EMIT(offs, u8); /* mov tmp, [ebp+#offs] */ \
} } while (0)
#define emith_ctx_write(r, offs) { \ #define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
int r_ = r, offs_ = offs, cnt_ = cnt; \
for (; cnt > 0; r_++, offs_ += 4, cnt_--) \
emith_ctx_read(r_, offs_); \
} while (0)
#define emith_ctx_write(r, offs) do { \
EMIT_OP_MODRM(0x89, 1, r, xBP); \ EMIT_OP_MODRM(0x89, 1, r, xBP); \
EMIT(offs, u8); /* mov [ebp+#offs], tmp */ \ EMIT(offs, u8); /* mov [ebp+#offs], tmp */ \
} } while (0)
#define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
int r_ = r, offs_ = offs, cnt_ = cnt; \
for (; cnt > 0; r_++, offs_ += 4, cnt_--) \
emith_ctx_write(r_, offs_); \
} while (0)
#define emith_jump(ptr) { \ #define emith_jump(ptr) { \
u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \ u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
@ -401,15 +419,21 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
#define emith_call_cond(cond, ptr) \ #define emith_call_cond(cond, ptr) \
emith_call(ptr) emith_call(ptr)
// "simple" or "short" jump #define emith_jump_reg(r) \
#define EMITH_SJMP_START(cond) { \ EMIT_OP_MODRM(0xff, 3, 4, r)
#define EMITH_JMP_START(cond) { \
u8 *cond_ptr; \ u8 *cond_ptr; \
JMP8_POS(cond_ptr) JMP8_POS(cond_ptr)
#define EMITH_SJMP_END(cond) \ #define EMITH_JMP_END(cond) \
JMP8_EMIT(cond, cond_ptr); \ JMP8_EMIT(cond, cond_ptr); \
} }
// "simple" jump (no more then a few insns)
#define EMITH_SJMP_START EMITH_JMP_START
#define EMITH_SJMP_END EMITH_JMP_END
#define host_arg2reg(rd, arg) \ #define host_arg2reg(rd, arg) \
switch (arg) { \ switch (arg) { \
case 0: rd = xAX; break; \ case 0: rd = xAX; break; \
@ -430,6 +454,17 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
} }
/* SH2 drc specific */ /* SH2 drc specific */
#define emith_sh2_drc_entry() { \
emith_push(xBX); \
emith_push(xBP); \
}
#define emith_sh2_drc_exit() { \
emith_pop(xBP); \
emith_pop(xBX); \
EMIT_OP(0xc3); /* ret */\
}
#define emith_sh2_test_t() { \ #define emith_sh2_test_t() { \
int t = rcache_get_reg(SHR_SR, RC_GR_READ); \ int t = rcache_get_reg(SHR_SR, RC_GR_READ); \
EMIT_OP_MODRM(0xf6, 3, 0, t); \ EMIT_OP_MODRM(0xf6, 3, 0, t); \

318
cpu/sh2/compiler.c
View file

@ -11,6 +11,7 @@
#include "compiler.h" #include "compiler.h"
#include "../drc/cmn.h" #include "../drc/cmn.h"
// debug stuff {
#ifndef DRC_DEBUG #ifndef DRC_DEBUG
#define DRC_DEBUG 0 #define DRC_DEBUG 0
#endif #endif
@ -40,6 +41,7 @@ static char sh2dasm_buff[64];
#else #else
#define do_host_disasm(x) #define do_host_disasm(x)
#endif #endif
// } debug
#define BLOCK_CYCLE_LIMIT 100 #define BLOCK_CYCLE_LIMIT 100
#define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6) #define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6)
@ -47,6 +49,7 @@ static char sh2dasm_buff[64];
// we have 3 translation cache buffers, split from one drc/cmn buffer. // we have 3 translation cache buffers, split from one drc/cmn buffer.
// BIOS shares tcache with data array because it's only used for init // BIOS shares tcache with data array because it's only used for init
// and can be discarded early // and can be discarded early
// XXX: need to tune sizes
static const int tcache_sizes[3] = { static const int tcache_sizes[3] = {
DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM
DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
@ -152,8 +155,8 @@ static int block_counts[3];
#define HASH_MASK (MAX_HASH_ENTRIES - 1) #define HASH_MASK (MAX_HASH_ENTRIES - 1)
static void **hash_table; static void **hash_table;
extern void sh2_drc_entry(SH2 *sh2, void *block); static void REGPARM(2) (*sh2_drc_entry)(const void *block, SH2 *sh2);
extern void sh2_drc_exit(void); static void (*sh2_drc_exit)(void);
// tmp // tmp
extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode); extern void REGPARM(2) sh2_do_op(SH2 *sh2, int opcode);
@ -503,12 +506,13 @@ static int emit_indirect_indexed_read(int rx, int ry, int size)
return emit_memhandler_read(size); return emit_memhandler_read(size);
} }
// Rwr -> @(Rx,Ry) // tmp_wr -> @(Rx,Ry)
static void emit_indirect_indexed_write(int rx, int ry, int wr, int size) static void emit_indirect_indexed_write(int tmp_wr, int rx, int ry, int size)
{ {
int a0, t; int a0, t;
rcache_clean(); rcache_clean();
rcache_get_reg_arg(1, wr); t = rcache_get_tmp_arg(1);
emith_move_r_r(t, tmp_wr);
a0 = rcache_get_reg_arg(0, rx); a0 = rcache_get_reg_arg(0, rx);
t = rcache_get_reg(ry, RC_GR_READ); t = rcache_get_reg(ry, RC_GR_READ);
emith_add_r_r(a0, t); emith_add_r_r(a0, t);
@ -537,35 +541,57 @@ static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int si
emith_add_r_imm(tmp, 1 << size); emith_add_r_imm(tmp, 1 << size);
} }
// fixup for saturated MAC, to be called from generated code static void emit_do_static_regs(int is_write, int tmpr)
// FIXME: statically alloced regs need to be fixed
static void sh2_macl_sat_fixup(void)
{ {
if ((signed int)sh2->mach < 0 && sh2->mach < 0xffff8000) int i, r, count;
{
sh2->mach = 0x00008000; for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
sh2->macl = 0x00000000; r = reg_map_g2h[i];
} if (r == -1)
else if ((signed int)sh2->mach > 0 && sh2->mach > 0x00007fff) continue;
{
sh2->mach = 0x00007fff; for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
sh2->macl = 0xffffffff; if (reg_map_g2h[i + 1] != r + 1)
break;
count++;
}
if (count > 1) {
// i, r point to last item
if (is_write)
emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
else
emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
} else {
if (is_write)
emith_ctx_write(r, i * 4);
else
emith_ctx_read(r, i * 4);
}
} }
} }
static void sh2_macw_sat_fixup(void) static void sh2_generate_utils(void)
{ {
signed int t = sh2->mach; int ctx, blk, tmp;
if (t < -1 || (t == -1 && !(sh2->macl & 0x80000000)))
{ host_arg2reg(blk, 0);
sh2->mach = 0xffffffff; // ? host_arg2reg(ctx, 1);
sh2->macl = 0x80000000; host_arg2reg(tmp, 2);
}
else if (t > 0 || (t == 0 && (sh2->macl & 0x80000000))) // sh2_drc_entry(void *block, SH2 *sh2)
{ sh2_drc_entry = (void *)tcache_ptr;
sh2->mach = 0x7fffffff; emith_sh2_drc_entry();
sh2->macl = 0xffffffff; emith_move_r_r(CONTEXT_REG, ctx); // move ctx, arg1
} emit_do_static_regs(0, tmp);
emith_jump_reg(blk); // jump arg0
// sh2_drc_exit(void)
sh2_drc_exit = (void *)tcache_ptr;
emit_do_static_regs(1, tmp);
emith_sh2_drc_exit();
rcache_invalidate();
} }
#define DELAYED_OP \ #define DELAYED_OP \
@ -697,7 +723,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
emit_indirect_indexed_write(SHR_R0, GET_Rn(), GET_Rm(), op & 3); tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
emit_indirect_indexed_write(tmp, SHR_R0, GET_Rn(), op & 3);
goto end_op; goto end_op;
case 0x07: case 0x07:
// MUL.L Rm,Rn 0000nnnnmmmm0111 // MUL.L Rm,Rn 0000nnnnmmmm0111
@ -712,12 +739,12 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
switch (GET_Fx()) switch (GET_Fx())
{ {
case 0: // CLRT 0000000000001000 case 0: // CLRT 0000000000001000
tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_bic_r_imm(tmp, T); emith_bic_r_imm(sr, T);
break; break;
case 1: // SETT 0000000000011000 case 1: // SETT 0000000000011000
tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_or_r_imm(tmp, T); emith_or_r_imm(sr, T);
break; break;
case 2: // CLRMAC 0000000000101000 case 2: // CLRMAC 0000000000101000
tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE); tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
@ -737,13 +764,13 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
break; break;
case 1: // DIV0U 0000000000011001 case 1: // DIV0U 0000000000011001
CHECK_UNHANDLED_BITS(0xf00); CHECK_UNHANDLED_BITS(0xf00);
tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_bic_r_imm(tmp, M|Q|T); emith_bic_r_imm(sr, M|Q|T);
break; break;
case 2: // MOVT Rn 0000nnnn00101001 case 2: // MOVT Rn 0000nnnn00101001
tmp = rcache_get_reg(SHR_SR, RC_GR_READ); sr = rcache_get_reg(SHR_SR, RC_GR_READ);
tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE); tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
emith_clear_msb(tmp2, tmp, 31); emith_clear_msb(tmp2, sr, 31);
break; break;
default: default:
goto default_; goto default_;
@ -822,24 +849,34 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
goto end_op; goto end_op;
case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2); emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ); sr = rcache_get_reg(SHR_SR, RC_GR_READ);
tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW); tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
/* MS 16 MAC bits unused if saturated */ /* MS 16 MAC bits unused if saturated */
emith_tst_r_imm(tmp3, S); emith_tst_r_imm(sr, S);
EMITH_SJMP_START(DCOND_EQ); EMITH_SJMP_START(DCOND_EQ);
emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16); emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
EMITH_SJMP_END(DCOND_EQ); EMITH_SJMP_END(DCOND_EQ);
tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
emith_mula_s64(tmp3, tmp4, tmp, tmp2); emith_mula_s64(tmp3, tmp4, tmp, tmp2);
rcache_free_tmp(tmp);
rcache_free_tmp(tmp2); rcache_free_tmp(tmp2);
rcache_clean(); sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ); emith_tst_r_imm(sr, S);
emith_tst_r_imm(tmp3, S);
EMITH_SJMP_START(DCOND_EQ); EMITH_JMP_START(DCOND_EQ);
emith_call_cond(DCOND_NE, sh2_macl_sat_fixup); emith_asr(tmp, tmp4, 15);
EMITH_SJMP_END(DCOND_EQ); emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
rcache_invalidate(); EMITH_SJMP_START(DCOND_GE);
emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
EMITH_SJMP_END(DCOND_GE);
emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
EMITH_SJMP_START(DCOND_LE);
emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
EMITH_SJMP_END(DCOND_LE);
EMITH_JMP_END(DCOND_EQ);
rcache_free_tmp(tmp);
cycles += 3; cycles += 3;
goto end_op; goto end_op;
} }
@ -877,30 +914,30 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
emit_memhandler_write(op & 3); emit_memhandler_write(op & 3);
goto end_op; goto end_op;
case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
emith_bic_r_imm(tmp, M|Q|T); emith_bic_r_imm(sr, M|Q|T);
emith_tst_r_imm(tmp2, (1<<31)); emith_tst_r_imm(tmp2, (1<<31));
EMITH_SJMP_START(DCOND_EQ); EMITH_SJMP_START(DCOND_EQ);
emith_or_r_imm_c(DCOND_NE, tmp, Q); emith_or_r_imm_c(DCOND_NE, sr, Q);
EMITH_SJMP_END(DCOND_EQ); EMITH_SJMP_END(DCOND_EQ);
emith_tst_r_imm(tmp3, (1<<31)); emith_tst_r_imm(tmp3, (1<<31));
EMITH_SJMP_START(DCOND_EQ); EMITH_SJMP_START(DCOND_EQ);
emith_or_r_imm_c(DCOND_NE, tmp, M); emith_or_r_imm_c(DCOND_NE, sr, M);
EMITH_SJMP_END(DCOND_EQ); EMITH_SJMP_END(DCOND_EQ);
emith_teq_r_r(tmp2, tmp3); emith_teq_r_r(tmp2, tmp3);
EMITH_SJMP_START(DCOND_PL); EMITH_SJMP_START(DCOND_PL);
emith_or_r_imm_c(DCOND_MI, tmp, T); emith_or_r_imm_c(DCOND_MI, sr, T);
EMITH_SJMP_END(DCOND_PL); EMITH_SJMP_END(DCOND_PL);
goto end_op; goto end_op;
case 0x08: // TST Rm,Rn 0010nnnnmmmm1000 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
emith_bic_r_imm(tmp, T); emith_bic_r_imm(sr, T);
emith_tst_r_r(tmp2, tmp3); emith_tst_r_r(tmp2, tmp3);
emit_or_t_if_eq(tmp); emit_or_t_if_eq(sr);
goto end_op; goto end_op;
case 0x09: // AND Rm,Rn 0010nnnnmmmm1001 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
@ -922,8 +959,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
emith_eor_r_r_r(tmp, tmp2, tmp3); emith_eor_r_r_r(tmp, tmp2, tmp3);
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_bic_r_imm(tmp2, T); emith_bic_r_imm(sr, T);
emith_tst_r_imm(tmp, 0x000000ff); emith_tst_r_imm(tmp, 0x000000ff);
emit_or_t_if_eq(tmp); emit_or_t_if_eq(tmp);
emith_tst_r_imm(tmp, 0x0000ff00); emith_tst_r_imm(tmp, 0x0000ff00);
@ -971,34 +1008,34 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
tmp = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ); tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ); tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
emith_bic_r_imm(tmp, T); emith_bic_r_imm(sr, T);
emith_cmp_r_r(tmp2, tmp3); emith_cmp_r_r(tmp2, tmp3);
switch (op & 0x07) switch (op & 0x07)
{ {
case 0x00: // CMP/EQ case 0x00: // CMP/EQ
emit_or_t_if_eq(tmp); emit_or_t_if_eq(sr);
break; break;
case 0x02: // CMP/HS case 0x02: // CMP/HS
EMITH_SJMP_START(DCOND_LO); EMITH_SJMP_START(DCOND_LO);
emith_or_r_imm_c(DCOND_HS, tmp, T); emith_or_r_imm_c(DCOND_HS, sr, T);
EMITH_SJMP_END(DCOND_LO); EMITH_SJMP_END(DCOND_LO);
break; break;
case 0x03: // CMP/GE case 0x03: // CMP/GE
EMITH_SJMP_START(DCOND_LT); EMITH_SJMP_START(DCOND_LT);
emith_or_r_imm_c(DCOND_GE, tmp, T); emith_or_r_imm_c(DCOND_GE, sr, T);
EMITH_SJMP_END(DCOND_LT); EMITH_SJMP_END(DCOND_LT);
break; break;
case 0x06: // CMP/HI case 0x06: // CMP/HI
EMITH_SJMP_START(DCOND_LS); EMITH_SJMP_START(DCOND_LS);
emith_or_r_imm_c(DCOND_HI, tmp, T); emith_or_r_imm_c(DCOND_HI, sr, T);
EMITH_SJMP_END(DCOND_LS); EMITH_SJMP_END(DCOND_LS);
break; break;
case 0x07: // CMP/GT case 0x07: // CMP/GT
EMITH_SJMP_START(DCOND_LE); EMITH_SJMP_START(DCOND_LE);
emith_or_r_imm_c(DCOND_GT, tmp, T); emith_or_r_imm_c(DCOND_GT, sr, T);
EMITH_SJMP_END(DCOND_LE); EMITH_SJMP_END(DCOND_LE);
break; break;
} }
@ -1055,29 +1092,29 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (op & 4) { // adc if (op & 4) { // adc
emith_set_carry(tmp3); emith_set_carry(sr);
emith_adcf_r_r(tmp, tmp2); emith_adcf_r_r(tmp, tmp2);
emith_carry_to_t(tmp3, 0); emith_carry_to_t(sr, 0);
} else { } else {
emith_set_carry_sub(tmp3); emith_set_carry_sub(sr);
emith_sbcf_r_r(tmp, tmp2); emith_sbcf_r_r(tmp, tmp2);
emith_carry_to_t(tmp3, 1); emith_carry_to_t(sr, 1);
} }
goto end_op; goto end_op;
case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ); tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_bic_r_imm(tmp3, T); emith_bic_r_imm(sr, T);
if (op & 4) { if (op & 4) {
emith_addf_r_r(tmp, tmp2); emith_addf_r_r(tmp, tmp2);
} else } else
emith_subf_r_r(tmp, tmp2); emith_subf_r_r(tmp, tmp2);
EMITH_SJMP_START(DCOND_VC); EMITH_SJMP_START(DCOND_VC);
emith_or_r_imm_c(DCOND_VS, tmp3, T); emith_or_r_imm_c(DCOND_VS, sr, T);
EMITH_SJMP_END(DCOND_VC); EMITH_SJMP_END(DCOND_VC);
goto end_op; goto end_op;
case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
@ -1099,10 +1136,10 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
{ {
case 0: // SHLL Rn 0100nnnn00000000 case 0: // SHLL Rn 0100nnnn00000000
case 2: // SHAL Rn 0100nnnn00100000 case 2: // SHAL Rn 0100nnnn00100000
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_lslf(tmp, tmp, 1); emith_lslf(tmp, tmp, 1);
emith_carry_to_t(tmp2, 0); emith_carry_to_t(sr, 0);
goto end_op; goto end_op;
case 1: // DT Rn 0100nnnn00010000 case 1: // DT Rn 0100nnnn00010000
if (p32x_sh2_read16(pc, sh2) == 0x8bfd) { // BF #-2 if (p32x_sh2_read16(pc, sh2) == 0x8bfd) { // BF #-2
@ -1110,10 +1147,10 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
goto end_op; goto end_op;
} }
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_bic_r_imm(tmp2, T); emith_bic_r_imm(sr, T);
emith_subf_r_imm(tmp, 1); emith_subf_r_imm(tmp, 1);
emit_or_t_if_eq(tmp2); emit_or_t_if_eq(sr);
goto end_op; goto end_op;
} }
goto default_; goto default_;
@ -1122,21 +1159,21 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
{ {
case 0: // SHLR Rn 0100nnnn00000001 case 0: // SHLR Rn 0100nnnn00000001
case 2: // SHAR Rn 0100nnnn00100001 case 2: // SHAR Rn 0100nnnn00100001
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (op & 0x20) { if (op & 0x20) {
emith_asrf(tmp, tmp, 1); emith_asrf(tmp, tmp, 1);
} else } else
emith_lsrf(tmp, tmp, 1); emith_lsrf(tmp, tmp, 1);
emith_carry_to_t(tmp2, 0); emith_carry_to_t(sr, 0);
goto end_op; goto end_op;
case 1: // CMP/PZ Rn 0100nnnn00010001 case 1: // CMP/PZ Rn 0100nnnn00010001
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_bic_r_imm(tmp2, T); emith_bic_r_imm(sr, T);
emith_cmp_r_imm(tmp, 0); emith_cmp_r_imm(tmp, 0);
EMITH_SJMP_START(DCOND_LT); EMITH_SJMP_START(DCOND_LT);
emith_or_r_imm_c(DCOND_GE, tmp2, T); emith_or_r_imm_c(DCOND_GE, sr, T);
EMITH_SJMP_END(DCOND_LT); EMITH_SJMP_END(DCOND_LT);
goto end_op; goto end_op;
} }
@ -1181,32 +1218,32 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
{ {
case 0x04: // ROTL Rn 0100nnnn00000100 case 0x04: // ROTL Rn 0100nnnn00000100
case 0x05: // ROTR Rn 0100nnnn00000101 case 0x05: // ROTR Rn 0100nnnn00000101
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
if (op & 1) { if (op & 1) {
emith_rorf(tmp, tmp, 1); emith_rorf(tmp, tmp, 1);
} else } else
emith_rolf(tmp, tmp, 1); emith_rolf(tmp, tmp, 1);
emith_carry_to_t(tmp2, 0); emith_carry_to_t(sr, 0);
goto end_op; goto end_op;
case 0x24: // ROTCL Rn 0100nnnn00100100 case 0x24: // ROTCL Rn 0100nnnn00100100
case 0x25: // ROTCR Rn 0100nnnn00100101 case 0x25: // ROTCR Rn 0100nnnn00100101
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_set_carry(tmp2); emith_set_carry(sr);
if (op & 1) { if (op & 1) {
emith_rorcf(tmp); emith_rorcf(tmp);
} else } else
emith_rolcf(tmp); emith_rolcf(tmp);
emith_carry_to_t(tmp2, 0); emith_carry_to_t(sr, 0);
goto end_op; goto end_op;
case 0x15: // CMP/PL Rn 0100nnnn00010101 case 0x15: // CMP/PL Rn 0100nnnn00010101
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW); tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_bic_r_imm(tmp2, T); emith_bic_r_imm(sr, T);
emith_cmp_r_imm(tmp, 0); emith_cmp_r_imm(tmp, 0);
EMITH_SJMP_START(DCOND_LE); EMITH_SJMP_START(DCOND_LE);
emith_or_r_imm_c(DCOND_GT, tmp2, T); emith_or_r_imm_c(DCOND_GT, sr, T);
EMITH_SJMP_END(DCOND_LE); EMITH_SJMP_END(DCOND_LE);
goto end_op; goto end_op;
} }
@ -1310,11 +1347,11 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
// XXX: is TAS working on 32X? // XXX: is TAS working on 32X?
rcache_clean(); rcache_clean();
rcache_get_reg_arg(0, GET_Rn()); rcache_get_reg_arg(0, GET_Rn());
tmp = emit_memhandler_read(0); tmp = emit_memhandler_read(0);
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_bic_r_imm(tmp2, T); emith_bic_r_imm(sr, T);
emith_cmp_r_imm(tmp, 0); emith_cmp_r_imm(tmp, 0);
emit_or_t_if_eq(tmp2); emit_or_t_if_eq(sr);
rcache_clean(); rcache_clean();
emith_or_r_imm(tmp, 0x80); emith_or_r_imm(tmp, 0x80);
tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
@ -1360,16 +1397,24 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW); tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
emith_mula_s64(tmp3, tmp4, tmp, tmp2); emith_mula_s64(tmp3, tmp4, tmp, tmp2);
rcache_free_tmp(tmp);
rcache_free_tmp(tmp2); rcache_free_tmp(tmp2);
rcache_clean();
// XXX: MACH should be untouched when S is set? // XXX: MACH should be untouched when S is set?
tmp3 = rcache_get_reg(SHR_SR, RC_GR_READ); sr = rcache_get_reg(SHR_SR, RC_GR_READ);
emith_tst_r_imm(tmp3, S); emith_tst_r_imm(sr, S);
EMITH_SJMP_START(DCOND_EQ); EMITH_JMP_START(DCOND_EQ);
emith_call_cond(DCOND_NE, sh2_macw_sat_fixup);
EMITH_SJMP_END(DCOND_EQ); emith_asr(tmp, tmp3, 31);
rcache_invalidate(); emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
EMITH_JMP_START(DCOND_EQ);
emith_move_r_imm(tmp3, 0x80000000);
emith_tst_r_r(tmp4, tmp4);
EMITH_SJMP_START(DCOND_MI);
emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
EMITH_SJMP_END(DCOND_MI);
EMITH_JMP_END(DCOND_EQ);
EMITH_JMP_END(DCOND_EQ);
rcache_free_tmp(tmp);
cycles += 2; cycles += 2;
goto end_op; goto end_op;
} }
@ -1441,10 +1486,10 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
emith_rol(tmp2, tmp, 16); emith_rol(tmp2, tmp, 16);
break; break;
case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_set_carry_sub(tmp3); emith_set_carry_sub(sr);
emith_negcf_r_r(tmp2, tmp); emith_negcf_r_r(tmp2, tmp);
emith_carry_to_t(tmp3, 1); emith_carry_to_t(sr, 1);
break; break;
case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
emith_neg_r_r(tmp2, tmp); emith_neg_r_r(tmp2, tmp);
@ -1504,11 +1549,11 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
// XXX: could use cmn // XXX: could use cmn
tmp = rcache_get_tmp(); tmp = rcache_get_tmp();
tmp2 = rcache_get_reg(0, RC_GR_READ); tmp2 = rcache_get_reg(0, RC_GR_READ);
tmp3 = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_move_r_imm_s8(tmp, op & 0xff); emith_move_r_imm_s8(tmp, op & 0xff);
emith_bic_r_imm(tmp3, T); emith_bic_r_imm(sr, T);
emith_cmp_r_r(tmp2, tmp); emith_cmp_r_r(tmp2, tmp);
emit_or_t_if_eq(tmp3); emit_or_t_if_eq(sr);
rcache_free_tmp(tmp); rcache_free_tmp(tmp);
goto end_op; goto end_op;
case 0x0d00: // BT/S label 10001101dddddddd case 0x0d00: // BT/S label 10001101dddddddd
@ -1626,11 +1671,11 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3); emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3);
goto end_op; goto end_op;
case 0x0800: // TST #imm,R0 11001000iiiiiiii case 0x0800: // TST #imm,R0 11001000iiiiiiii
tmp = rcache_get_reg(SHR_R0, RC_GR_READ); tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_bic_r_imm(tmp2, T); emith_bic_r_imm(sr, T);
emith_tst_r_imm(tmp, op & 0xff); emith_tst_r_imm(tmp, op & 0xff);
emit_or_t_if_eq(tmp2); emit_or_t_if_eq(sr);
goto end_op; goto end_op;
case 0x0900: // AND #imm,R0 11001001iiiiiiii case 0x0900: // AND #imm,R0 11001001iiiiiiii
tmp = rcache_get_reg(SHR_R0, RC_GR_RMW); tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
@ -1645,30 +1690,33 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block)
emith_or_r_imm(tmp, op & 0xff); emith_or_r_imm(tmp, op & 0xff);
goto end_op; goto end_op;
case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
tmp2 = rcache_get_reg(SHR_SR, RC_GR_RMW); sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
emith_bic_r_imm(tmp2, T); emith_bic_r_imm(sr, T);
emith_tst_r_imm(tmp, op & 0xff); emith_tst_r_imm(tmp, op & 0xff);
emit_or_t_if_eq(tmp2); emit_or_t_if_eq(sr);
rcache_free_tmp(tmp); rcache_free_tmp(tmp);
cycles += 2; cycles += 2;
goto end_op; goto end_op;
case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
emith_and_r_imm(tmp, op & 0xff); emith_and_r_imm(tmp, op & 0xff);
emit_indirect_indexed_write(SHR_R0, SHR_GBR, tmp, 0); goto end_rmw_op;
cycles += 2;
goto end_op;
case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
emith_eor_r_imm(tmp, op & 0xff); emith_eor_r_imm(tmp, op & 0xff);
emit_indirect_indexed_write(SHR_R0, SHR_GBR, tmp, 0); goto end_rmw_op;
cycles += 2;
goto end_op;
case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0); tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
emith_or_r_imm(tmp, op & 0xff); emith_or_r_imm(tmp, op & 0xff);
emit_indirect_indexed_write(SHR_R0, SHR_GBR, tmp, 0); end_rmw_op:
tmp2 = rcache_get_tmp_arg(1);
emith_move_r_r(tmp2, tmp);
rcache_free_tmp(tmp);
tmp3 = rcache_get_reg_arg(0, SHR_GBR);
tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
emith_add_r_r(tmp3, tmp4);
emit_memhandler_write(0);
cycles += 2; cycles += 2;
goto end_op; goto end_op;
} }
@ -1837,7 +1885,7 @@ void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2)
if (bd != NULL) if (bd != NULL)
bd->refcount++; bd->refcount++;
#endif #endif
sh2_drc_entry(sh2, block); sh2_drc_entry(block, sh2);
} }
} }
@ -1969,8 +2017,11 @@ int sh2_drc_init(SH2 *sh2)
if (block_tables[0] == NULL) if (block_tables[0] == NULL)
return -1; return -1;
tcache_ptr = tcache;
sh2_generate_utils();
memset(block_counts, 0, sizeof(block_counts)); memset(block_counts, 0, sizeof(block_counts));
tcache_bases[0] = tcache_ptrs[0] = tcache; tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
for (i = 1; i < ARRAY_SIZE(block_tables); i++) { for (i = 1; i < ARRAY_SIZE(block_tables); i++) {
block_tables[i] = block_tables[i - 1] + block_max_counts[i - 1]; block_tables[i] = block_tables[i - 1] + block_max_counts[i - 1];
@ -1983,6 +2034,9 @@ int sh2_drc_init(SH2 *sh2)
#if (DRC_DEBUG & 2) #if (DRC_DEBUG & 2)
for (i = 0; i < ARRAY_SIZE(block_tables); i++) for (i = 0; i < ARRAY_SIZE(block_tables); i++)
tcache_dsm_ptrs[i] = tcache_bases[i]; tcache_dsm_ptrs[i] = tcache_bases[i];
// disasm the utils
tcache_dsm_ptrs[0] = tcache;
do_host_disasm(0);
#endif #endif
#if (DRC_DEBUG & 1) #if (DRC_DEBUG & 1)
hash_collisions = 0; hash_collisions = 0;

16
cpu/sh2/stub_arm.s
View file

@ -1,16 +0,0 @@
@ vim:filetype=armasm
.text
.global sh2_drc_entry @ SH2 *sh2, void *block
sh2_drc_entry:
stmfd sp!, {r7,lr}
mov r7, r0
bx r1
.global sh2_drc_exit
sh2_drc_exit:
ldmfd sp!, {r7,pc}

18
cpu/sh2/stub_x86.asm
View file

@ -1,18 +0,0 @@
section .text
global sh2_drc_entry ; SH2 *sh2, void *block
sh2_drc_entry:
push ebx
push ebp
mov ebp, [esp+8+4] ; context
mov eax, [esp+8+8]
jmp eax
global sh2_drc_exit
sh2_drc_exit:
pop ebp
pop ebx
ret

1
platform/common/common.mak
View file

@ -37,7 +37,6 @@ OBJS += cpu/drc/cmn.o
ifeq "$(use_sh2drc)" "1" ifeq "$(use_sh2drc)" "1"
DEFINES += DRC_SH2 DEFINES += DRC_SH2
OBJS += cpu/sh2/compiler.o OBJS += cpu/sh2/compiler.o
OBJS += cpu/sh2/stub_$(ARCH).o
ifdef drc_debug ifdef drc_debug
DEFINES += DRC_DEBUG=$(drc_debug) DEFINES += DRC_DEBUG=$(drc_debug)
OBJS += cpu/sh2/mame/sh2dasm.o OBJS += cpu/sh2/mame/sh2dasm.o

1
platform/linux/host_dasm.c
View file

@ -144,6 +144,7 @@ static int insn_printf(void *f, const char *format, ...)
static void host_dasm_init(void) static void host_dasm_init(void)
{ {
bfd_init();
slurp_symtab(g_argv[0]); slurp_symtab(g_argv[0]);
init_disassemble_info(&di, NULL, insn_printf); init_disassemble_info(&di, NULL, insn_printf);