mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
split memories away from Pico
saves ~3k of code on ARM because Pico no longer crosses ldr limit
This commit is contained in:
notaz
parent
e64886365d
commit
88fd63ad10
30 changed files with 633 additions and 587 deletions
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@ -1,259 +0,0 @@
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/*
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* PicoDrive
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* (C) notaz, 2006-2009
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*
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* This work is licensed under the terms of MAME license.
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* See COPYING file in the top-level directory.
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*/
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.equ SRR_MAPPED, (1 << 0)
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.equ SRR_READONLY, (1 << 1)
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.equ SRF_EEPROM, (1 << 1)
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.equ POPT_EN_32X, (1 << 20)
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.text
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.align 4
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.global PicoRead8_sram
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.global PicoRead8_io
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.global PicoRead16_sram
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.global PicoRead16_io
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.global PicoWrite8_io
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.global PicoWrite16_io
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PicoRead8_sram: @ u32 a, u32 d
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ldr r2, =(SRam)
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ldr r3, =(Pico+0x22200)
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ldr r1, [r2, #8] @ SRam.end
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cmp r0, r1
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bgt m_read8_nosram
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ldr r1, [r2, #4] @ SRam.start
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cmp r0, r1
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blt m_read8_nosram
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ldrb r1, [r3, #0x11] @ Pico.m.sram_reg
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tst r1, #SRR_MAPPED
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beq m_read8_nosram
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ldr r1, [r2, #0x0c]
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tst r1, #SRF_EEPROM
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bne m_read8_eeprom
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ldr r1, [r2, #4] @ SRam.start
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ldr r2, [r2] @ SRam.data
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sub r0, r0, r1
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add r0, r0, r2
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ldrb r0, [r0]
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bx lr
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m_read8_nosram:
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ldr r1, [r3, #4] @ romsize
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cmp r0, r1
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movgt r0, #0
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bxgt lr @ bad location
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@ XXX: banking unfriendly
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ldr r1, [r3]
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eor r0, r0, #1
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ldrb r0, [r1, r0]
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bx lr
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m_read8_eeprom:
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stmfd sp!,{r0,lr}
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bl EEPROM_read
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ldmfd sp!,{r1,lr}
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tst r1, #1
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moveq r0, r0, lsr #8
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bx lr
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PicoRead8_io: @ u32 a, u32 d
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bic r2, r0, #0x001f @ most commonly we get i/o port read,
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cmp r2, #0xa10000 @ so check for it first
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beq io_ports_read
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m_read8_not_io:
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and r2, r0, #0xfc00
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cmp r2, #0x1000
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bne m_read8_not_brq
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ldr r3, =(Pico+0x22200)
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mov r1, r0
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ldr r0, [r3, #8] @ Pico.m.rotate
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add r0, r0, #1
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strb r0, [r3, #8]
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eor r0, r0, r0, lsl #6
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tst r1, #1
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bxne lr @ odd addr -> open bus
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bic r0, r0, #1 @ bit0 defined in this area
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and r2, r1, #0xff00
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cmp r2, #0x1100
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bxne lr @ not busreq
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ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run
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ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset
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orr r0, r0, r1
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orr r0, r0, r2
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bx lr
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m_read8_not_brq:
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ldr r2, =PicoOpt
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ldr r2, [r2]
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tst r2, #POPT_EN_32X
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bne PicoRead8_32x
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mov r0, #0
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bx lr
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@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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PicoRead16_sram: @ u32 a, u32 d
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ldr r2, =(SRam)
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ldr r3, =(Pico+0x22200)
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ldr r1, [r2, #8] @ SRam.end
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cmp r0, r1
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bgt m_read16_nosram
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ldr r1, [r2, #4] @ SRam.start
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cmp r0, r1
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blt m_read16_nosram
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ldrb r1, [r3, #0x11] @ Pico.m.sram_reg
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tst r1, #SRR_MAPPED
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beq m_read16_nosram
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ldr r1, [r2, #0x0c]
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tst r1, #SRF_EEPROM
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bne EEPROM_read
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ldr r1, [r2, #4] @ SRam.start
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ldr r2, [r2] @ SRam.data
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sub r0, r0, r1
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add r0, r0, r2
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ldrb r1, [r0], #1
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ldrb r0, [r0]
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orr r0, r0, r1, lsl #8
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bx lr
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m_read16_nosram:
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ldr r1, [r3, #4] @ romsize
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cmp r0, r1
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movgt r0, #0
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bxgt lr @ bad location
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@ XXX: banking unfriendly
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ldr r1, [r3]
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ldrh r0, [r1, r0]
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bx lr
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PicoRead16_io: @ u32 a, u32 d
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bic r2, r0, #0x001f @ most commonly we get i/o port read,
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cmp r2, #0xa10000 @ so check for it first
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bne m_read16_not_io
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stmfd sp!,{lr}
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bl io_ports_read @ same as read8
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orr r0, r0, r0, lsl #8 @ only has bytes mirrored
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ldmfd sp!,{pc}
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m_read16_not_io:
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and r2, r0, #0xfc00
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cmp r2, #0x1000
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bne m_read16_not_brq
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ldr r3, =(Pico+0x22200)
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and r2, r0, #0xff00
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ldr r0, [r3, #8] @ Pico.m.rotate
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add r0, r0, #1
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strb r0, [r3, #8]
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eor r0, r0, r0, lsl #5
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eor r0, r0, r0, lsl #8
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bic r0, r0, #0x100 @ bit8 defined in this area
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cmp r2, #0x1100
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bxne lr @ not busreq
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ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run
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ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset
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orr r0, r0, r1, lsl #8
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orr r0, r0, r2, lsl #8
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bx lr
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m_read16_not_brq:
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ldr r2, =PicoOpt
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ldr r2, [r2]
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tst r2, #POPT_EN_32X
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bne PicoRead16_32x
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mov r0, #0
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bx lr
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@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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PicoWrite8_io: @ u32 a, u32 d
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bic r2, r0, #0x1e @ most commonly we get i/o port write,
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eor r2, r2, #0xa10000 @ so check for it first
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eors r2, r2, #1
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beq io_ports_write
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m_write8_not_io:
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tst r0, #1
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bne m_write8_not_z80ctl @ even addrs only
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and r2, r0, #0xff00
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cmp r2, #0x1100
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moveq r0, r1
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beq ctl_write_z80busreq
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cmp r2, #0x1200
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moveq r0, r1
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beq ctl_write_z80reset
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m_write8_not_z80ctl:
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@ unlikely
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eor r2, r0, #0xa10000
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eor r2, r2, #0x003000
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eors r2, r2, #0x0000f1
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bne m_write8_not_sreg
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ldr r3, =(Pico+0x22200)
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ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg
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and r1, r1, #(SRR_MAPPED|SRR_READONLY)
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bic r2, r2, #(SRR_MAPPED|SRR_READONLY)
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orr r2, r2, r1
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strb r2, [r3, #(8+9)]
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bx lr
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m_write8_not_sreg:
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ldr r2, =PicoOpt
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ldr r2, [r2]
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tst r2, #POPT_EN_32X
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bne PicoWrite8_32x
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bx lr
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@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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PicoWrite16_io: @ u32 a, u32 d
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bic r2, r0, #0x1f @ most commonly we get i/o port write,
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cmp r2, #0xa10000 @ so check for it first
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beq io_ports_write
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m_write16_not_io:
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and r2, r0, #0xff00
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cmp r2, #0x1100
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moveq r0, r1, lsr #8
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beq ctl_write_z80busreq
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cmp r2, #0x1200
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moveq r0, r1, lsr #8
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beq ctl_write_z80reset
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m_write16_not_z80ctl:
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@ unlikely
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eor r2, r0, #0xa10000
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eor r2, r2, #0x003000
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eors r2, r2, #0x0000f0
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bne m_write16_not_sreg
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ldr r3, =(Pico+0x22200)
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ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg
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and r1, r1, #(SRR_MAPPED|SRR_READONLY)
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bic r2, r2, #(SRR_MAPPED|SRR_READONLY)
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orr r2, r2, r1
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strb r2, [r3, #(8+9)]
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bx lr
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m_write16_not_sreg:
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ldr r2, =PicoOpt
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ldr r2, [r2]
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tst r2, #POPT_EN_32X
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bne PicoWrite16_32x
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bx lr
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.pool
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@ vim:filetype=armasm
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