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https://github.com/RaySollium99/picodrive.git
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audio: added SSG-EG to YM2612, plus some timing changes for SN76496+YM2612
This commit is contained in:
kub
parent
2a942f0d41
commit
8ac9ab7fcb
13 changed files with 571 additions and 455 deletions
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@ -1,6 +1,7 @@
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/*
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* PicoDrive
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* (C) notaz, 2006
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* (C) kub, 2020 added SSG-EG and simple output rate interpolation
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*
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* This work is licensed under the terms of MAME license.
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* See COPYING file in the top-level directory.
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@ -18,7 +19,7 @@
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.equiv SLOT2, 2
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.equiv SLOT3, 1
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.equiv SLOT4, 3
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.equiv SLOT_STRUCT_SIZE, 0x30
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.equiv SLOT_STRUCT_SIZE, 0x38
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.equiv TL_TAB_LEN, 0x1A00
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@ -28,11 +29,11 @@
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.equiv EG_REL, 1
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.equiv EG_OFF, 0
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.equiv EG_SH, 16 @ 16.16 fixed point (envelope generator timing)
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.equiv EG_SH, 16 @ 16.16 fixed point (envelope generator timing)
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.equiv EG_TIMER_OVERFLOW, (3*(1<<EG_SH)) @ envelope generator timer overflows every 3 samples (on real chip)
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.equiv LFO_SH, 24 /* 8.24 fixed point (LFO calculations) */
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.equiv ENV_QUIET, (2*13*256/8)
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.equiv ENV_QUIET, (2*13*256/8)
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.text
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.align 2
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@ -41,8 +42,10 @@
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@ r5=slot, r1=eg_cnt, trashes: r0,r2,r3
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@ writes output to routp, but only if vol_out changes
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.macro update_eg_phase_slot slot
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ldrh r0, [r5,#0x32] @ vol_out
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ldrb r2, [r5,#0x17] @ state
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add r3, r5, #0x1c
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strh r0, [r5,#0x34] @ vol_ipol
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tst r2, r2
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beq 0f @ EG_OFF
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@ -60,11 +63,17 @@
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add r3, r3, r3, lsl #1
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mov r3, r2, lsr r3
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and r3, r3, #7 @ eg_inc_val shift, may be 0
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ldrb r0, [r5,#0x30] @ ssg
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ldrb r2, [r5,#0x17] @ state
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ldrh r0, [r5,#0x1a] @ volume, unsigned (0-1023)
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tst r0, #0x08 @ ssg enabled?
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bne 9f
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@ non-SSG-EG mode
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cmp r2, #4 @ EG_ATT
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ldrh r0, [r5,#0x1a] @ volume, unsigned (0-1023)
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beq 4f
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cmp r2, #2
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mov r2, #1
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mov r2, r2, lsl r3
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@ -82,10 +91,9 @@
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4: @ EG_ATT
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subs r3, r3, #1 @ eg_inc_val_shift - 1
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mov r2, #0
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mvnpl r2, r0
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mov r2, r2, lsl r3
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add r0, r0, r2, asr #4
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movpl r2, r2, lsl r3
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addpl r0, r0, r2, asr #4
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cmp r0, #0 @ if (volume <= MIN_ATT_INDEX)
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bgt 10f
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ldr r2, [r5,#0x1c]
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@ -112,24 +120,81 @@
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strgeb r3, [r5,#0x17] @ state
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10: @ finish
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ldrh r3, [r5,#0x18] @ tl
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strh r0, [r5,#0x1a] @ volume
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b 11f
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9: @ SSG-EG mode
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cmp r2, #4 @ EG_ATT
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ldrh r0, [r5,#0x1a] @ volume, unsigned (0-1023)
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beq 4f
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cmp r0, #0x200 @ if ( volume < 0x200 )
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movlt r0, #1
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movlt r3, r0, lsl r3
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ldrlth r0, [r5,#0x1a] @ volume, unsigned (0-1023)
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movlt r3, r3, lsr #1 @ eg_inc_val
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addlt r0, r0, r3, lsr #2
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cmp r2, #2
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blt 1f @ EG_REL
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beq 10f @ EG_SUS - nothing more to do
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3: @ EG_DEC
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ldr r2, [r5,#0x1c] @ sl (can be 16bit?)
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mov r3, #EG_SUS
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cmp r0, r2 @ if ( volume >= (INT32) SLOT->sl )
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strgeb r3, [r5,#0x17] @ state
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b 10f
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4: @ EG_ATT
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subs r3, r3, #1 @ eg_inc_val_shift - 1
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mvnpl r2, r0
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movpl r2, r2, lsl r3
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addpl r0, r0, r2, asr #4
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cmp r0, #0 @ if (volume <= MIN_ATT_INDEX)
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bgt 10f
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ldr r2, [r5,#0x1c]
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mov r0, #0
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cmp r2, #0
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movne r3, #EG_DEC
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moveq r3, #EG_SUS
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strb r3, [r5,#0x17] @ state
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b 10f
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1: @ EG_REL
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mov r2, #0x200
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cmp r0, r2 @ if ( volume >= 0x200 )
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movge r0, #1024
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subge r0, #1
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movge r3, #EG_OFF
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strgeb r3, [r5,#0x17] @ state
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10: @ finish
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strh r0, [r5,#0x1a] @ volume
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ldrb r2, [r5,#0x30] @ ssg
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ldrb r3, [r5,#0x17] @ state
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cmp r2, #0x0c @ if ( ssg&0x04 && state > EG_REL )
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cmpge r3, #EG_REL+1
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rsbge r0, r0, #0x200 @ volume = (0x200-volume) & MAX_ATT
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lslge r0, r0, #10
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lsrge r0, r0, #10
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11:
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ldrh r3, [r5,#0x18] @ tl
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add r0, r0, r3 @ volume += tl
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strh r0, [r5,#0x32] @ vol_out
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.if \slot == SLOT1
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mov r6, r6, lsr #16
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add r0, r0, r3
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orr r6, r0, r6, lsl #16
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.elseif \slot == SLOT2
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mov r6, r6, lsl #16
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add r0, r0, r3
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mov r0, r0, lsl #16
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orr r6, r0, r6, lsr #16
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.elseif \slot == SLOT3
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mov r7, r7, lsr #16
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add r0, r0, r3
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orr r7, r0, r7, lsl #16
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.elseif \slot == SLOT4
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mov r7, r7, lsl #16
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add r0, r0, r3
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mov r0, r0, lsl #16
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orr r7, r0, r7, lsr #16
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.endif
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@ -137,6 +202,63 @@
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0: @ EG_OFF
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.endm
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@ r5=slot, trashes: r0,r2,r3
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.macro update_ssg_eg
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ldrh r0, [r5,#0x30] @ ssg+ssgn
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ldrb r2, [r5,#0x17] @ state
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ldrh r3, [r5,#0x1a] @ volume
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tst r0, #0x08 @ ssg enabled?
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beq 9f
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cmp r2, #EG_REL @ state > EG_REL?
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ble 9f
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cmp r3, #0x200 @ volume >= 0x200?
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blt 9f
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tst r0, #0x01
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beq 1f
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tst r0, #0x02
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eorne r0, r0, lsr #8 @ ssg ^= ssgn ^ 4
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eorne r0, r0, #0x4
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orrne r0, r0, #0x400 @ ssgn = 4
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strneh r0, [r5,#0x30]
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eor r0, r0, #0x4 @ if ( !(ssg&0x04 )
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tst r0, #0x4
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cmpne r2, #EG_ATT @ if ( state != EG_ATT )
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movne r0, #0x400
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subne r0, r0, #1
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strneh r0, [r5,#0x1a] @ volume = MAX_ATT
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b 9f
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1: tst r0, #0x02
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eorne r0, r0, #0x4 @ ssg ^= 4
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eorne r0, r0, #0x400 @ ssgn ^= 4
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strneh r0, [r5,#0x30]
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moveq r3, #0
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streq r3, [r5,#0x0c] @ phase = 0
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cmp r2, #EG_ATT @ if ( state != EG_ATT )
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beq 9f
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ldr r3, [r5,#0x1c] @ sl
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mov r2, #EG_SUS @ state = sl==MIN_ATT ? EG_SUS:EG_DEC
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cmp r3, #0
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ldr r0, [r5,#0x04] @ ar
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ldr r3, [r5,#0x14] @ ksr
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movne r2, #EG_DEC
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add r0, r0, r3
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cmp r0, #32+62 @ if ( ar+ksr >= 32+62 )
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ldrlt r0, [r5,#0x1a]
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movge r0, #0
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strgeh r0, [r5,#0x1a] @ volume = MIN_ATT
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cmp r0, #0
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movgt r2, #EG_ATT
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strb r2, [r5,#0x17] @ state
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9:
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.endm
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@ r12=lfo_ampm[31:16], r1=lfo_cnt_old, r2=lfo_cnt, r3=scratch
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.macro advance_lfo_m
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@ -532,187 +654,6 @@
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.endm
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/*
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.global update_eg_phase @ FM_SLOT *SLOT, UINT32 eg_cnt
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update_eg_phase:
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stmfd sp!, {r5,r6}
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mov r5, r0 @ slot
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ldrh r3, [r5,#0x18] @ tl
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ldrh r6, [r5,#0x1a] @ volume
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add r6, r6, r3
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update_eg_phase_slot SLOT1
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mov r0, r6
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ldmfd sp!, {r5,r6}
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bx lr
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.pool
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.global advance_lfo @ int lfo_ampm, UINT32 lfo_cnt_old, UINT32 lfo_cnt
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advance_lfo:
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mov r12, r0, lsl #16
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advance_lfo_m
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mov r0, r12, lsr #16
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bx lr
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.pool
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.global upd_algo0 @ chan_rend_context *c
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upd_algo0:
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stmfd sp!, {r4-r10,lr}
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mov lr, r0
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PIC_LDR(r3, ip, ym_sin_tab)
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PIC_LDR(r5, ip, ym_tl_tab)
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ldmia lr, {r6-r7}
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ldr r10, [lr, #0x54]
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ldr r12, [lr, #0x4c]
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upd_algo0_m
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ldmfd sp!, {r4-r10,pc}
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.pool
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.global upd_algo1 @ chan_rend_context *c
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upd_algo1:
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stmfd sp!, {r4-r10,lr}
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mov lr, r0
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PIC_LDR(r3, ip, ym_sin_tab)
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PIC_LDR(r5, ip, ym_tl_tab)
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ldmia lr, {r6-r7}
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ldr r10, [lr, #0x54]
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ldr r12, [lr, #0x4c]
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upd_algo1_m
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ldmfd sp!, {r4-r10,pc}
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.pool
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.global upd_algo2 @ chan_rend_context *c
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upd_algo2:
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stmfd sp!, {r4-r10,lr}
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mov lr, r0
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PIC_LDR(r3, ip, ym_sin_tab)
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PIC_LDR(r5, ip, ym_tl_tab)
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ldmia lr, {r6-r7}
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ldr r10, [lr, #0x54]
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ldr r12, [lr, #0x4c]
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upd_algo2_m
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ldmfd sp!, {r4-r10,pc}
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.pool
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.global upd_algo3 @ chan_rend_context *c
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upd_algo3:
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stmfd sp!, {r4-r10,lr}
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mov lr, r0
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PIC_LDR(r3, ip, ym_sin_tab)
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PIC_LDR(r5, ip, ym_tl_tab)
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ldmia lr, {r6-r7}
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ldr r10, [lr, #0x54]
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ldr r12, [lr, #0x4c]
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upd_algo3_m
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ldmfd sp!, {r4-r10,pc}
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.pool
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.global upd_algo4 @ chan_rend_context *c
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upd_algo4:
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stmfd sp!, {r4-r10,lr}
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mov lr, r0
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PIC_LDR(r3, ip, ym_sin_tab)
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PIC_LDR(r5, ip, ym_tl_tab)
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ldmia lr, {r6-r7}
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ldr r10, [lr, #0x54]
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ldr r12, [lr, #0x4c]
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upd_algo4_m
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ldmfd sp!, {r4-r10,pc}
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.pool
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.global upd_algo5 @ chan_rend_context *c
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upd_algo5:
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stmfd sp!, {r4-r10,lr}
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mov lr, r0
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PIC_LDR(r3, ip, ym_sin_tab)
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PIC_LDR(r5, ip, ym_tl_tab)
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ldmia lr, {r6-r7}
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ldr r10, [lr, #0x54]
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ldr r12, [lr, #0x4c]
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upd_algo5_m
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ldmfd sp!, {r4-r10,pc}
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.pool
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.global upd_algo6 @ chan_rend_context *c
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upd_algo6:
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stmfd sp!, {r4-r10,lr}
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mov lr, r0
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PIC_LDR(r3, ip, ym_sin_tab)
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PIC_LDR(r5, ip, ym_tl_tab)
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ldmia lr, {r6-r7}
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ldr r10, [lr, #0x54]
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ldr r12, [lr, #0x4c]
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upd_algo6_m
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ldmfd sp!, {r4-r10,pc}
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.pool
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.global upd_algo7 @ chan_rend_context *c
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upd_algo7:
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stmfd sp!, {r4-r10,lr}
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mov lr, r0
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PIC_LDR(r3, ip, ym_sin_tab)
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PIC_LDR(r5, ip, ym_tl_tab)
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ldmia lr, {r6-r7}
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ldr r10, [lr, #0x54]
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ldr r12, [lr, #0x4c]
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upd_algo7_m
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ldmfd sp!, {r4-r10,pc}
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.pool
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.global upd_slot1 @ chan_rend_context *c
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upd_slot1:
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stmfd sp!, {r4-r10,lr}
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mov lr, r0
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PIC_LDR(r3, ip, ym_sin_tab)
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PIC_LDR(r5, ip, ym_tl_tab)
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ldmia lr, {r6-r7}
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ldr r10, [lr, #0x54]
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ldr r12, [lr, #0x4c]
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upd_slot1_m
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str r10, [lr, #0x38]
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ldmfd sp!, {r4-r10,pc}
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.pool
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*/
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@ lr=context, r12=pack (stereo, lastchan, disabled, lfo_enabled | pan_r, pan_l, ams[2] | AMmasks[4] | FB[4] | lfo_ampm[16])
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@ r0-r2=scratch, r3=sin_tab/scratch, r4=(length<<8)|unused[4],was_update,algo[3], r5=tl_tab/slot,
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@ r6-r7=vol_out[4], r8=eg_timer, r9=eg_timer_add[31:16], r10=op1_out, r11=buffer
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@ -730,14 +671,21 @@ chan_render_loop:
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add r0, lr, #0x44
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ldmia r0, {r8,r9} @ eg_timer, eg_timer_add
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ldr r10, [lr, #0x54] @ op1_out
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ldmia lr, {r6,r7} @ load volumes
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@ ldmia lr, {r6,r7} @ load volumes
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ldr r5, [lr, #0x40] @ CH
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ldrh r6, [r5, #0x32] @ vol_out values for all slots
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ldrh r2, [r5, #0x32+SLOT_STRUCT_SIZE*2]
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ldrh r7, [r5, #0x32+SLOT_STRUCT_SIZE]
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ldrh r3, [r5, #0x32+SLOT_STRUCT_SIZE*3]
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orr r6, r6, r2, lsl #16
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orr r7, r7, r3, lsl #16
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tst r12, #8 @ lfo?
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beq crl_loop
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crl_loop_lfo:
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add r0, lr, #0x30
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ldmia r0, {r1,r2}
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ldmia r0, {r1,r2} @ lfo_cnt, lfo_inc
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|
||||
subs r4, r4, #0x100
|
||||
bmi crl_loop_end
|
||||
|
|
@ -754,15 +702,29 @@ crl_loop:
|
|||
subs r4, r4, #0x100
|
||||
bmi crl_loop_end
|
||||
|
||||
@ -- SSG --
|
||||
add r0, lr, #0x3c
|
||||
ldmia r0, {r1,r5} @ eg_cnt, CH
|
||||
|
||||
@ r5=slot, trashes: r0,r2,r3
|
||||
update_ssg_eg
|
||||
add r5, r5, #SLOT_STRUCT_SIZE*2 @ SLOT2 (2)
|
||||
update_ssg_eg
|
||||
sub r5, r5, #SLOT_STRUCT_SIZE @ SLOT3 (1)
|
||||
update_ssg_eg
|
||||
add r5, r5, #SLOT_STRUCT_SIZE*2 @ SLOT4 (3)
|
||||
update_ssg_eg
|
||||
sub r5, r5, #SLOT_STRUCT_SIZE*3
|
||||
|
||||
@ -- EG --
|
||||
add r8, r8, r9
|
||||
cmp r8, #EG_TIMER_OVERFLOW
|
||||
bcc eg_done
|
||||
add r0, lr, #0x3c
|
||||
ldmia r0, {r1,r5} @ eg_cnt, CH
|
||||
eg_loop:
|
||||
sub r8, r8, #EG_TIMER_OVERFLOW
|
||||
add r1, r1, #1
|
||||
cmp r1, #4096
|
||||
movge r1, #1
|
||||
@ SLOT1 (0)
|
||||
@ r5=slot, r1=eg_cnt, trashes: r0,r2,r3
|
||||
update_eg_phase_slot SLOT1
|
||||
|
|
@ -774,8 +736,8 @@ eg_loop:
|
|||
update_eg_phase_slot SLOT4
|
||||
|
||||
cmp r8, #EG_TIMER_OVERFLOW
|
||||
subcs r5, r5, #SLOT_STRUCT_SIZE*3
|
||||
bcs eg_loop
|
||||
sub r5, r5, #SLOT_STRUCT_SIZE*3
|
||||
bhs eg_loop
|
||||
str r1, [lr, #0x3c]
|
||||
|
||||
eg_done:
|
||||
|
|
@ -787,6 +749,66 @@ eg_done:
|
|||
cmp r0, #0x4
|
||||
beq crl_loop
|
||||
|
||||
@ output interpolation
|
||||
#if 0
|
||||
@ basic interpolator, interpolate in middle region, else use closer value
|
||||
mov r3, r8, lsr #EG_SH @ eg_timer, [0..3<<EG_SH) after loop
|
||||
cmp r3, #(EG_TIMER_OVERFLOW>>EG_SH)/2
|
||||
bgt 0f @ mix is vol_out
|
||||
|
||||
ldrh r0, [r5,#0x34] @ SLOT1 vol_ipol
|
||||
lsleq r2, r6, #16
|
||||
addeq r0, r0, r2, lsr #16
|
||||
lsreq r0, r0, #1
|
||||
mov r6, r6, lsr #16
|
||||
orr r6, r0, r6, lsl #16
|
||||
|
||||
ldrh r0, [r5,#0x34+SLOT_STRUCT_SIZE*2] @ SLOT2 vol_ipol
|
||||
addeq r0, r0, r6, lsr #16
|
||||
lsreq r0, r0, #1
|
||||
mov r6, r6, lsl #16
|
||||
orr r6, r6, r0
|
||||
ror r6, r6, #16
|
||||
|
||||
ldrh r0, [r5,#0x34+SLOT_STRUCT_SIZE] @ SLOT3 vol_ipol
|
||||
lsleq r2, r7, #16
|
||||
addeq r0, r0, r2, lsr #16
|
||||
lsreq r0, r0, #1
|
||||
mov r7, r7, lsr #16
|
||||
orr r7, r0, r7, lsl #16
|
||||
|
||||
ldrh r0, [r5,#0x34+SLOT_STRUCT_SIZE*3] @ SLOT4 vol_ipol
|
||||
addeq r0, r0, r7, lsr #16
|
||||
lsreq r0, r0, #1
|
||||
mov r7, r7, lsl #16
|
||||
orr r7, r7, r0
|
||||
ror r7, r7, #16
|
||||
#elif 0
|
||||
@ super-basic... just take value closest to sample point
|
||||
mov r3, r8, lsr #EG_SH-1 @ eg_timer, [0..3<<EG_SH) after loop
|
||||
cmp r3, #(EG_TIMER_OVERFLOW>>EG_SH)
|
||||
bgt 0f @ mix is vol_out
|
||||
|
||||
ldrh r0, [r5,#0x34] @ SLOT1 vol_ipol
|
||||
mov r6, r6, lsr #16
|
||||
orr r6, r0, r6, lsl #16
|
||||
|
||||
ldrh r0, [r5,#0x34+SLOT_STRUCT_SIZE*2] @ SLOT2 vol_ipol
|
||||
mov r6, r6, lsl #16
|
||||
orr r6, r6, r0
|
||||
ror r6, r6, #16
|
||||
|
||||
ldrh r0, [r5,#0x34+SLOT_STRUCT_SIZE] @ SLOT3 vol_ipol
|
||||
mov r7, r7, lsr #16
|
||||
orr r7, r0, r7, lsl #16
|
||||
|
||||
ldrh r0, [r5,#0x34+SLOT_STRUCT_SIZE*3] @ SLOT4 vol_ipol
|
||||
mov r7, r7, lsl #16
|
||||
orr r7, r7, r0
|
||||
ror r7, r7, #16
|
||||
#endif
|
||||
0:
|
||||
|
||||
@ -- SLOT1 --
|
||||
PIC_LDR(r3, r2, ym_tl_tab)
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue