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https://github.com/RaySollium99/picodrive.git
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import SPI EEPROM from Genesis-Plus-GX
Author: EkeEke
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notaz
parent
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2 changed files with 405 additions and 0 deletions
358
pico/carthw/eeprom_spi.c
Normal file
358
pico/carthw/eeprom_spi.c
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/****************************************************************************
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* Genesis Plus
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* SPI Serial EEPROM (25xxx/95xxx) support
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*
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* Copyright (C) 2012 Eke-Eke (Genesis Plus GX)
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*
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* Redistribution and use of this code or any derivative works are permitted
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* provided that the following conditions are met:
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*
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* - Redistributions may not be sold, nor may they be used in a commercial
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* product or activity.
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*
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* - Redistributions that are modified from the original source must include the
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* complete source code, including the source code for all components used by a
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* binary built from the modified sources. However, as a special exception, the
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* source code distributed need not include anything that is normally distributed
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* (in either source or binary form) with the major components (compiler, kernel,
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* and so on) of the operating system on which the executable runs, unless that
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* component itself accompanies the executable.
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*
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* - Redistributions must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#include "shared.h"
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/* max supported size 64KB (25x512/95x512) */
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#define SIZE_MASK 0xffff
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#define PAGE_MASK 0x7f
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/* hard-coded board implementation (!WP pin not used) */
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#define BIT_DATA (0)
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#define BIT_CLK (1)
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#define BIT_HOLD (2)
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#define BIT_CS (3)
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typedef enum
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{
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STANDBY,
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GET_OPCODE,
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GET_ADDRESS,
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WRITE_BYTE,
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READ_BYTE
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} T_STATE_SPI;
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typedef struct
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{
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uint8 cs; /* !CS line state */
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uint8 clk; /* SCLK line state */
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uint8 out; /* SO line state */
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uint8 status; /* status register */
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uint8 opcode; /* 8-bit opcode */
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uint8 buffer; /* 8-bit data buffer */
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uint16 addr; /* 16-bit address */
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uint32 cycles; /* current operation cycle */
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T_STATE_SPI state; /* current operation state */
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} T_EEPROM_SPI;
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static T_EEPROM_SPI spi_eeprom;
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void eeprom_spi_init()
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{
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/* reset eeprom state */
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memset(&spi_eeprom, 0, sizeof(T_EEPROM_SPI));
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spi_eeprom.out = 1;
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spi_eeprom.state = GET_OPCODE;
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/* enable backup RAM */
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sram.custom = 2;
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sram.on = 1;
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}
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void eeprom_spi_write(unsigned char data)
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{
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/* Make sure !HOLD is high */
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if (data & (1 << BIT_HOLD))
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{
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/* Check !CS state */
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if (data & (1 << BIT_CS))
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{
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/* !CS high -> end of current operation */
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spi_eeprom.cycles = 0;
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spi_eeprom.out = 1;
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spi_eeprom.opcode = 0;
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spi_eeprom.state = GET_OPCODE;
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}
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else
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{
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/* !CS low -> process current operation */
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switch (spi_eeprom.state)
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{
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case GET_OPCODE:
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{
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/* latch data on CLK positive edge */
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if ((data & (1 << BIT_CLK)) && !spi_eeprom.clk)
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{
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/* 8-bit opcode buffer */
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spi_eeprom.opcode |= ((data >> BIT_DATA) & 1);
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spi_eeprom.cycles++;
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/* last bit ? */
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if (spi_eeprom.cycles == 8)
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{
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/* reset cycles count */
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spi_eeprom.cycles = 0;
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/* Decode instruction */
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switch (spi_eeprom.opcode)
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{
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case 0x01:
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{
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/* WRITE STATUS */
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spi_eeprom.buffer = 0;
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spi_eeprom.state = WRITE_BYTE;
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break;
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}
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case 0x02:
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{
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/* WRITE BYTE */
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spi_eeprom.addr = 0;
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spi_eeprom.state = GET_ADDRESS;
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break;
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}
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case 0x03:
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{
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/* READ BYTE */
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spi_eeprom.addr = 0;
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spi_eeprom.state = GET_ADDRESS;
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break;
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}
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case 0x04:
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{
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/* WRITE DISABLE */
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spi_eeprom.status &= ~0x02;
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spi_eeprom.state = STANDBY;
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break;
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}
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case 0x05:
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{
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/* READ STATUS */
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spi_eeprom.buffer = spi_eeprom.status;
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spi_eeprom.state = READ_BYTE;
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break;
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}
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case 0x06:
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{
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/* WRITE ENABLE */
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spi_eeprom.status |= 0x02;
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spi_eeprom.state = STANDBY;
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break;
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}
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default:
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{
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/* specific instructions (not supported) */
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spi_eeprom.state = STANDBY;
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break;
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}
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}
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}
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else
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{
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/* shift opcode value */
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spi_eeprom.opcode = spi_eeprom.opcode << 1;
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}
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}
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break;
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}
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case GET_ADDRESS:
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{
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/* latch data on CLK positive edge */
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if ((data & (1 << BIT_CLK)) && !spi_eeprom.clk)
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{
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/* 16-bit address */
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spi_eeprom.addr |= ((data >> BIT_DATA) & 1);
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spi_eeprom.cycles++;
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/* last bit ? */
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if (spi_eeprom.cycles == 16)
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{
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/* reset cycles count */
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spi_eeprom.cycles = 0;
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/* mask unused address bits */
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spi_eeprom.addr &= SIZE_MASK;
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/* operation type */
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if (spi_eeprom.opcode & 0x01)
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{
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/* READ operation */
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spi_eeprom.buffer = sram.sram[spi_eeprom.addr];
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spi_eeprom.state = READ_BYTE;
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}
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else
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{
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/* WRITE operation */
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spi_eeprom.buffer = 0;
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spi_eeprom.state = WRITE_BYTE;
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}
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}
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else
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{
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/* shift address value */
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spi_eeprom.addr = spi_eeprom.addr << 1;
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}
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}
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break;
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}
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case WRITE_BYTE:
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{
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/* latch data on CLK positive edge */
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if ((data & (1 << BIT_CLK)) && !spi_eeprom.clk)
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{
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/* 8-bit data buffer */
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spi_eeprom.buffer |= ((data >> BIT_DATA) & 1);
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spi_eeprom.cycles++;
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/* last bit ? */
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if (spi_eeprom.cycles == 8)
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{
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/* reset cycles count */
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spi_eeprom.cycles = 0;
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/* write data to destination */
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if (spi_eeprom.opcode & 0x01)
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{
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/* update status register */
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spi_eeprom.status = (spi_eeprom.status & 0x02) | (spi_eeprom.buffer & 0x0c);
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/* wait for operation end */
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spi_eeprom.state = STANDBY;
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}
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else
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{
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/* Memory Array (write-protected) */
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if (spi_eeprom.status & 2)
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{
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/* check array protection bits (BP0, BP1) */
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switch ((spi_eeprom.status >> 2) & 0x03)
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{
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case 0x01:
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{
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/* $C000-$FFFF (sector #3) is protected */
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if (spi_eeprom.addr < 0xC000)
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{
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sram.sram[spi_eeprom.addr] = spi_eeprom.buffer;
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}
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break;
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}
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case 0x02:
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{
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/* $8000-$FFFF (sectors #2 and #3) is protected */
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if (spi_eeprom.addr < 0x8000)
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{
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sram.sram[spi_eeprom.addr] = spi_eeprom.buffer;
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}
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break;
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}
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case 0x03:
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{
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/* $0000-$FFFF (all sectors) is protected */
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break;
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}
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default:
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{
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/* no sectors protected */
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sram.sram[spi_eeprom.addr] = spi_eeprom.buffer;
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break;
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}
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}
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}
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/* reset data buffer */
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spi_eeprom.buffer = 0;
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/* increase array address (sequential writes are limited within the same page) */
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spi_eeprom.addr = (spi_eeprom.addr & ~PAGE_MASK) | ((spi_eeprom.addr + 1) & PAGE_MASK);
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}
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}
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else
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{
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/* shift data buffer value */
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spi_eeprom.buffer = spi_eeprom.buffer << 1;
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}
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}
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break;
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}
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case READ_BYTE:
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{
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/* output data on CLK positive edge */
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if ((data & (1 << BIT_CLK)) && !spi_eeprom.clk)
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{
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/* read out bits */
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spi_eeprom.out = (spi_eeprom.buffer >> (7 - spi_eeprom.cycles)) & 1;
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spi_eeprom.cycles++;
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/* last bit ? */
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if (spi_eeprom.cycles == 8)
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{
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/* reset cycles count */
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spi_eeprom.cycles = 0;
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/* read from memory array ? */
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if (spi_eeprom.opcode == 0x03)
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{
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/* read next array byte */
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spi_eeprom.addr = (spi_eeprom.addr + 1) & SIZE_MASK;
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spi_eeprom.buffer = sram.sram[spi_eeprom.addr];
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}
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}
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}
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break;
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}
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default:
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{
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/* wait for !CS low->high transition */
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break;
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}
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}
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}
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}
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/* update input lines */
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spi_eeprom.cs = (data >> BIT_CS) & 1;
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spi_eeprom.clk = (data >> BIT_CLK) & 1;
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}
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unsigned int eeprom_spi_read(unsigned int address)
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{
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return (spi_eeprom.out << BIT_DATA);
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}
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47
pico/carthw/eeprom_spi.h
Normal file
47
pico/carthw/eeprom_spi.h
Normal file
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@ -0,0 +1,47 @@
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/****************************************************************************
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* Genesis Plus
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* SPI Serial EEPROM (25XX512 only) support
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*
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* Copyright (C) 2012 Eke-Eke (Genesis Plus GX)
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*
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* Redistribution and use of this code or any derivative works are permitted
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||||
* provided that the following conditions are met:
|
||||
*
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||||
* - Redistributions may not be sold, nor may they be used in a commercial
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||||
* product or activity.
|
||||
*
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||||
* - Redistributions that are modified from the original source must include the
|
||||
* complete source code, including the source code for all components used by a
|
||||
* binary built from the modified sources. However, as a special exception, the
|
||||
* source code distributed need not include anything that is normally distributed
|
||||
* (in either source or binary form) with the major components (compiler, kernel,
|
||||
* and so on) of the operating system on which the executable runs, unless that
|
||||
* component itself accompanies the executable.
|
||||
*
|
||||
* - Redistributions must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
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****************************************************************************************/
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#ifndef _EEPROM_SPI_H_
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#define _EEPROM_SPI_H_
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/* Function prototypes */
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extern void eeprom_spi_init();
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extern void eeprom_spi_write(unsigned char data);
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extern unsigned int eeprom_spi_read(unsigned int address);
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#endif
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