mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
add 32bit memory access functions for SH2
This commit is contained in:
kub
parent
1db36a7a07
commit
9031406131
4 changed files with 150 additions and 48 deletions
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@ -2906,7 +2906,6 @@ static void sh2_generate_utils(void)
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{
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int arg0, arg1, arg2, sr, tmp;
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sh2_drc_write32 = p32x_sh2_write32;
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sh2_drc_read8 = p32x_sh2_read8;
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sh2_drc_read16 = p32x_sh2_read16;
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sh2_drc_read32 = p32x_sh2_read32;
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@ -3015,6 +3014,11 @@ static void sh2_generate_utils(void)
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emith_ctx_read_ptr(arg2, offsetof(SH2, write16_tab));
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emith_sh2_wcall(arg0, arg2);
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// sh2_drc_write32(u32 a, u32 d)
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sh2_drc_write32 = (void *)tcache_ptr;
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emith_ctx_read_ptr(arg2, offsetof(SH2, write32_tab));
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emith_sh2_wcall(arg0, arg2);
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#ifdef PDB_NET
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// debug
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#define MAKE_READ_WRAPPER(func) { \
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@ -3053,7 +3057,6 @@ static void sh2_generate_utils(void)
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host_dasm_new_symbol(sh2_drc_read8);
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host_dasm_new_symbol(sh2_drc_read16);
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host_dasm_new_symbol(sh2_drc_read32);
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host_dasm_new_symbol(sh2_drc_write32);
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#endif
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#endif
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@ -3065,6 +3068,7 @@ static void sh2_generate_utils(void)
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host_dasm_new_symbol(sh2_drc_test_irq);
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host_dasm_new_symbol(sh2_drc_write8);
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host_dasm_new_symbol(sh2_drc_write16);
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host_dasm_new_symbol(sh2_drc_write32);
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#endif
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}
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@ -12,6 +12,7 @@ typedef enum {
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typedef struct SH2_
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{
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// registers. this MUST correlate with enum sh2_reg_e.
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unsigned int r[16]; // 00
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unsigned int pc; // 40
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unsigned int ppc;
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@ -21,17 +22,19 @@ typedef struct SH2_
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unsigned int mach, macl; // 58
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// common
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const void *read8_map; // 60
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const void *read8_map;
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const void *read16_map;
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const void *read32_map;
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const void **write8_tab;
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const void **write16_tab;
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const void **write32_tab;
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// drc stuff
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int drc_tmp; // 70
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int drc_tmp;
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int irq_cycles;
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void *p_bios; // convenience pointers
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void *p_da;
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void *p_sdram; // 80
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void *p_sdram;
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void *p_rom;
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unsigned int pdb_io_csum[2];
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@ -1087,8 +1087,8 @@ static void m68k_write8_dram1_ow(u32 a, u32 d)
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return; \
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} \
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/* overwrite */ \
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if (!(d & 0xff00)) d |= *pd & 0xff00; \
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if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
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if (!(d & 0xff00)) d |= *pd & 0xff00; \
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*pd = d;
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static void m68k_write16_dram0_ow(u32 a, u32 d)
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@ -1344,6 +1344,31 @@ static u32 sh2_read16_rom(u32 a, SH2 *sh2)
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return *(u16 *)(Pico.rom + bank + (a & 0x7fffe));
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}
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static u32 sh2_read32_unmapped(u32 a, SH2 *sh2)
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{
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elprintf_sh2(sh2, EL_32X, "unmapped r32 [%08x] %08x @%06x",
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a, 0, sh2_pc(sh2));
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return 0;
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}
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static u32 sh2_read32_cs0(u32 a, SH2 *sh2)
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{
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return (sh2_read16_cs0(a, sh2) << 16) | sh2_read16_cs0(a + 2, sh2);
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}
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static u32 sh2_read32_da(u32 a, SH2 *sh2)
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{
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u32 d = *(u32 *)(sh2->data_array + (a & 0xfff));
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return (d << 16) | (d >> 16);
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}
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static u32 sh2_read32_rom(u32 a, SH2 *sh2)
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{
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u32 bank = carthw_ssf2_banks[(a >> 19) & 7] << 19;
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u32 d = *(u32 *)(Pico.rom + bank + (a & 0x7fffc));
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return (d << 16) | (d >> 16);
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}
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// writes
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static void REGPARM(3) sh2_write_ignore(u32 a, u32 d, SH2 *sh2)
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{
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@ -1501,6 +1526,73 @@ static void REGPARM(3) sh2_write16_rom(u32 a, u32 d, SH2 *sh2)
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sh2_write16_unmapped(a, d, sh2);
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}
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static void REGPARM(3) sh2_write32_unmapped(u32 a, u32 d, SH2 *sh2)
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{
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elprintf_sh2(sh2, EL_32X, "unmapped w32 [%08x] %08x @%06x",
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a, d, sh2_pc(sh2));
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}
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static void REGPARM(3) sh2_write32_cs0(u32 a, u32 d, SH2 *sh2)
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{
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sh2_write16_cs0(a, d >> 16, sh2);
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sh2_write16_cs0(a + 2, d, sh2);
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}
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#define sh2_write32_dramN(n) \
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u32 *pd = (u32 *)&Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
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if (!(a & 0x20000)) { \
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*pd = (d << 16) | (d >> 16); \
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return; \
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} \
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/* overwrite */ \
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u8 *pb = (u8 *)pd; \
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if (d & 0x000000ff) pb[2] = d; \
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if (d & 0x0000ff00) pb[3] = d >> 8; \
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if (d & 0x00ff0000) pb[0] = d >> 16; \
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if (d & 0xff000000) pb[1] = d >> 24; \
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static void REGPARM(3) sh2_write32_dram0(u32 a, u32 d, SH2 *sh2)
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{
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sh2_write32_dramN(0);
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}
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static void REGPARM(3) sh2_write32_dram1(u32 a, u32 d, SH2 *sh2)
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{
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sh2_write32_dramN(1);
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}
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static void REGPARM(3) sh2_write32_sdram(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0x3ffff;
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*(u32 *)(sh2->p_sdram + a1) = (d << 16) | (d >> 16);
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#ifdef DRC_SH2
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unsigned short *p = &Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
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if (p[0])
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sh2_drc_wcheck_ram(a, p[0], sh2->is_slave);
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if (p[1])
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sh2_drc_wcheck_ram(a, p[1], sh2->is_slave);
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#endif
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}
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static void REGPARM(3) sh2_write32_da(u32 a, u32 d, SH2 *sh2)
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{
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u32 a1 = a & 0xfff;
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*(u32 *)(sh2->data_array + a1) = (d << 16) | (d >> 16);
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#ifdef DRC_SH2
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int id = sh2->is_slave;
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unsigned short *p = &Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
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if (p[0])
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sh2_drc_wcheck_da(a, p[0], id);
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if (p[1])
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sh2_drc_wcheck_da(a, p[1], id);
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#endif
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}
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static void REGPARM(3) sh2_write32_rom(u32 a, u32 d, SH2 *sh2)
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{
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sh2_write16_rom(a, d >> 16, sh2);
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sh2_write16_rom(a + 2, d, sh2);
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}
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typedef u32 (sh2_read_handler)(u32 a, SH2 *sh2);
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typedef void REGPARM(3) (sh2_write_handler)(u32 a, u32 d, SH2 *sh2);
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@ -1534,30 +1626,21 @@ u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
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if (map_flag_set(p))
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return ((sh2_read_handler *)(p << 1))(a, sh2);
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else
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return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
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return *(u16 *)((p << 1) + (a & sh2_map->mask));
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}
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u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
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{
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const sh2_memmap *sh2_map = sh2->read16_map;
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sh2_read_handler *handler;
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u32 offs;
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const sh2_memmap *sh2_map = sh2->read32_map;
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uptr p;
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offs = SH2MAP_ADDR2OFFS_R(a);
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sh2_map += offs;
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sh2_map += SH2MAP_ADDR2OFFS_R(a);
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p = sh2_map->addr;
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if (!map_flag_set(p)) {
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// XXX: maybe 32bit access instead with ror?
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u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
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return (pd[0] << 16) | pd[1];
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}
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if (offs == SH2MAP_ADDR2OFFS_R(0xffffc000))
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return sh2_peripheral_read32(a, sh2);
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handler = (sh2_read_handler *)(p << 1);
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return (handler(a, sh2) << 16) | handler(a + 2, sh2);
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u32 *pd = (u32 *)((p << 1) + (a & sh2_map->mask));
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return (*pd << 16) | (*pd >> 16);
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} else
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return ((sh2_read_handler *)(p << 1))(a, sh2);
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}
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void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
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@ -1580,20 +1663,11 @@ void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
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void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
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{
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const void **sh2_wmap = sh2->write16_tab;
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const void **sh2_wmap = sh2->write32_tab;
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sh2_write_handler *wh;
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u32 offs;
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offs = SH2MAP_ADDR2OFFS_W(a);
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if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
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sh2_peripheral_write32(a, d, sh2);
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return;
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}
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wh = sh2_wmap[offs];
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wh(a, d >> 16, sh2);
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wh(a + 2, d, sh2);
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wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
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wh(a, d, sh2);
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}
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// -----------------------------------------------------------------
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@ -1801,9 +1875,9 @@ static void get_bios(void)
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#define MAP_MEMORY(m) ((uptr)(m) >> 1)
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#define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
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static sh2_memmap sh2_read8_map[0x80], sh2_read16_map[0x80];
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static sh2_memmap sh2_read8_map[0x80], sh2_read16_map[0x80], sh2_read32_map[0x80];
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// for writes we are using handlers only
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static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
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static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80], *sh2_write32_map[0x80];
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void Pico32xSwapDRAM(int b)
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{
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@ -1818,10 +1892,12 @@ void Pico32xSwapDRAM(int b)
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// SH2
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sh2_read8_map[0x04/2].addr = sh2_read8_map[0x24/2].addr =
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sh2_read16_map[0x04/2].addr = sh2_read16_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]);
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sh2_read16_map[0x04/2].addr = sh2_read16_map[0x24/2].addr =
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sh2_read32_map[0x04/2].addr = sh2_read32_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]);
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sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
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sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
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sh2_write32_map[0x04/2] = sh2_write32_map[0x24/2] = b ? sh2_write32_dram1 : sh2_write32_dram0;
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}
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static void bank_switch_rom_sh2(void)
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@ -1829,11 +1905,13 @@ static void bank_switch_rom_sh2(void)
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if (!carthw_ssf2_active) {
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// easy
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sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr =
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sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_MEMORY(Pico.rom);
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sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr =
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sh2_read32_map[0x02/2].addr = sh2_read32_map[0x22/2].addr = MAP_MEMORY(Pico.rom);
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}
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else {
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sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr = MAP_HANDLER(sh2_read8_rom);
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sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_HANDLER(sh2_read16_rom);
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sh2_read32_map[0x02/2].addr = sh2_read32_map[0x22/2].addr = MAP_HANDLER(sh2_read32_rom);
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}
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}
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@ -1903,58 +1981,75 @@ void PicoMemSetup32x(void)
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for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
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sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped);
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sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped);
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sh2_read32_map[i].addr = MAP_HANDLER(sh2_read32_unmapped);
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}
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for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
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sh2_write8_map[i] = sh2_write8_unmapped;
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sh2_write16_map[i] = sh2_write16_unmapped;
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sh2_write32_map[i] = sh2_write32_unmapped;
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}
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// "purge area"
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for (i = 0x40; i <= 0x5f; i++) {
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sh2_write8_map[i >> 1] =
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sh2_write16_map[i >> 1] = sh2_write_ignore;
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sh2_write16_map[i >> 1] =
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sh2_write32_map[i >> 1] = sh2_write_ignore;
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}
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// CS0
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sh2_read8_map[0x00/2].addr = sh2_read8_map[0x20/2].addr = MAP_HANDLER(sh2_read8_cs0);
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sh2_read16_map[0x00/2].addr = sh2_read16_map[0x20/2].addr = MAP_HANDLER(sh2_read16_cs0);
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sh2_read32_map[0x00/2].addr = sh2_read32_map[0x20/2].addr = MAP_HANDLER(sh2_read32_cs0);
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sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
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sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
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sh2_write32_map[0x00/2] = sh2_write32_map[0x20/2] = sh2_write32_cs0;
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// CS1 - ROM
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bank_switch_rom_sh2();
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sh2_read8_map[0x02/2].mask = sh2_read8_map[0x22/2].mask =
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sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3fffff; // FIXME
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sh2_read8_map[0x02/2].mask = sh2_read8_map[0x22/2].mask = 0x3fffff; // FIXME
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sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3ffffe; // FIXME
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sh2_read32_map[0x02/2].mask = sh2_read32_map[0x22/2].mask = 0x3ffffc; // FIXME
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sh2_write16_map[0x02/2] = sh2_write16_map[0x22/2] = sh2_write16_rom;
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sh2_write32_map[0x02/2] = sh2_write32_map[0x22/2] = sh2_write32_rom;
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// CS2 - DRAM - done by Pico32xSwapDRAM()
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sh2_read8_map[0x04/2].mask = sh2_read8_map[0x24/2].mask =
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sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01ffff;
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sh2_read8_map[0x04/2].mask = sh2_read8_map[0x24/2].mask = 0x01ffff;
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sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01fffe;
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sh2_read32_map[0x04/2].mask = sh2_read32_map[0x24/2].mask = 0x01fffc;
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// CS3 - SDRAM
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sh2_read8_map[0x06/2].addr = sh2_read8_map[0x26/2].addr =
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sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram);
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sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr =
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sh2_read32_map[0x06/2].addr = sh2_read32_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram);
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sh2_write8_map[0x06/2] = sh2_write8_sdram;
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sh2_write8_map[0x26/2] = sh2_write8_sdram_wt;
|
||||
sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
|
||||
sh2_read8_map[0x06/2].mask = sh2_read8_map[0x26/2].mask =
|
||||
sh2_read16_map[0x06/2].mask = sh2_read16_map[0x26/2].mask = 0x03ffff;
|
||||
sh2_write32_map[0x06/2] = sh2_write32_map[0x26/2] = sh2_write32_sdram;
|
||||
sh2_read8_map[0x06/2].mask = sh2_read8_map[0x26/2].mask = 0x03ffff;
|
||||
sh2_read16_map[0x06/2].mask = sh2_read16_map[0x26/2].mask = 0x03fffe;
|
||||
sh2_read32_map[0x06/2].mask = sh2_read32_map[0x26/2].mask = 0x03fffc;
|
||||
// SH2 data array
|
||||
sh2_read8_map[0xc0/2].addr = MAP_HANDLER(sh2_read8_da);
|
||||
sh2_read16_map[0xc0/2].addr = MAP_HANDLER(sh2_read16_da);
|
||||
sh2_read32_map[0xc0/2].addr = MAP_HANDLER(sh2_read32_da);
|
||||
sh2_write8_map[0xc0/2] = sh2_write8_da;
|
||||
sh2_write16_map[0xc0/2] = sh2_write16_da;
|
||||
sh2_write32_map[0xc0/2] = sh2_write32_da;
|
||||
// SH2 IO
|
||||
sh2_read8_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read8);
|
||||
sh2_read16_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read16);
|
||||
sh2_read32_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read32);
|
||||
sh2_write8_map[0xff/2] = sh2_peripheral_write8;
|
||||
sh2_write16_map[0xff/2] = sh2_peripheral_write16;
|
||||
sh2_write32_map[0xff/2] = sh2_peripheral_write32;
|
||||
|
||||
// map DRAM area, both 68k and SH2
|
||||
Pico32xSwapDRAM(1);
|
||||
|
||||
msh2.read8_map = ssh2.read8_map = sh2_read8_map;
|
||||
msh2.read16_map = ssh2.read16_map = sh2_read16_map;
|
||||
msh2.read32_map = ssh2.read32_map = sh2_read32_map;
|
||||
msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map;
|
||||
msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
|
||||
msh2.write32_tab = ssh2.write32_tab = (const void **)(void *)sh2_write32_map;
|
||||
|
||||
sh2_drc_mem_setup(&msh2);
|
||||
sh2_drc_mem_setup(&ssh2);
|
||||
|
|
|
|||
|
|
@ -244,7 +244,7 @@ u32 sh2_peripheral_read16(u32 a, SH2 *sh2)
|
|||
u16 *r = (void *)sh2->peri_regs;
|
||||
u32 d;
|
||||
|
||||
a &= 0x1ff;
|
||||
a &= 0x1fe;
|
||||
d = r[(a / 2) ^ 1];
|
||||
|
||||
elprintf_sh2(sh2, EL_32XP, "peri r16 [%08x] %04x @%06x",
|
||||
|
|
@ -343,7 +343,7 @@ void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
|
|||
elprintf_sh2(sh2, EL_32XP, "peri w16 [%08x] %04x @%06x",
|
||||
a, d, sh2_pc(sh2));
|
||||
|
||||
a &= 0x1ff;
|
||||
a &= 0x1fe;
|
||||
|
||||
// evil WDT
|
||||
if (a == 0x80) {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue