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sh2 drc: cleanup, fix for drc crash, for mips code emitter
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kub
parent
9760505eaf
commit
90b1c9db91
12 changed files with 151 additions and 120 deletions
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@ -20,6 +20,9 @@
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#define STATIC_SH2_REGS { SHR_SR,22 , SHR_R0,21 , SHR_R0+1,20 }
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// NB: the ubiquitous JZ74[46]0 uses MIPS32 Release 1, a slight MIPS II superset
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#ifndef __mips_isa_rev
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#define __mips_isa_rev 1 // surprisingly not always defined
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#endif
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// registers usable for user code: r1-r25, others reserved or special
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#define Z0 0 // zero register
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@ -333,32 +336,49 @@ static int emith_is_b(u32 op) // B
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{ return ((op>>26) & 074) == OP_BEQ ||
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((op>>26) == OP__RT && ((op>>16) & 036) == RT_BLTZ); }
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// register usage for dependency evaluation XXX better do this as in emit_arm?
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static uint64_t emith_has_rs[3] = // OP__FN, OP__RT, others
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{ 0x00fffffffffa0ff0ULL, 0x000fff0fUL, 0xffffffff0f007ff0ULL };
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static uint64_t emith_has_rt[3] = // OP__FN, OP__RT, others
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{ 0xff00fffffff00cffULL, 0x00000000UL, 0x8000ff0000000030ULL };
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static uint64_t emith_has_rd[3] = // OP__FN, OP__RT, others (rt instead of rd)
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{ 0xff00fffffff50fffULL, 0x00000000UL, 0x119100ff0f00ff00ULL };
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static uint64_t emith_has_rs[5] = // OP__FN1-3, OP__RT, others
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{ 0x005ffcffffda0fd2ULL, 0x0000003300000037ULL, 0x00000000000000ffULL,
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0x800f5f0fUL, 0xf7ffffff0ff07ff0ULL };
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static uint64_t emith_has_rt[5] = // OP__FN1-3, OP__RT, others
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{ 0xdd5ffcffffd00cddULL, 0x0000000000000037ULL, 0x0000001100000000ULL,
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0x00000000UL, 0x80007f440c300030ULL };
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static uint64_t emith_has_rd[5] = // OP__FN1-3, OP__RT, others(rt instead of rd)
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{ 0xdd00fcff00d50edfULL, 0x0000003300000004ULL, 0x08000011000000ffULL,
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0x00000000UL, 0x119100ff0f00ff00ULL };
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#define emith_has_(rx,ix,op,sa,m) \
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(emith_has_##rx[ix] & (1ULL << (((op)>>(sa)) & (m))))
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static int emith_rs(u32 op)
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{ if ((op>>26) == OP__FN)
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return emith_has_(rs,0,op, 0,0x3f) ? (op>>21)&0x1f : 0;
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if ((op>>26) == OP__FN2)
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return emith_has_(rs,1,op, 0,0x3f) ? (op>>21)&0x1f : 0;
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if ((op>>26) == OP__FN3)
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return emith_has_(rs,2,op, 0,0x3f) ? (op>>21)&0x1f : 0;
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if ((op>>26) == OP__RT)
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return emith_has_(rs,1,op,16,0x1f) ? (op>>21)&0x1f : 0;
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return emith_has_(rs,2,op,26,0x3f) ? (op>>21)&0x1f : 0;
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return emith_has_(rs,3,op,16,0x1f) ? (op>>21)&0x1f : 0;
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return emith_has_(rs,4,op,26,0x3f) ? (op>>21)&0x1f : 0;
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}
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static int emith_rt(u32 op)
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{ if ((op>>26) == OP__FN)
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return emith_has_(rt,0,op, 0,0x3f) ? (op>>16)&0x1f : 0;
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if ((op>>26) == OP__FN2)
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return emith_has_(rt,1,op, 0,0x3f) ? (op>>16)&0x1f : 0;
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if ((op>>26) == OP__FN3)
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return emith_has_(rt,2,op, 0,0x3f) ? (op>>16)&0x1f : 0;
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if ((op>>26) == OP__RT)
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return 0;
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return emith_has_(rt,2,op,26,0x3f) ? (op>>16)&0x1f : 0;
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return emith_has_(rt,4,op,26,0x3f) ? (op>>16)&0x1f : 0;
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}
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static int emith_rd(u32 op)
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{ int ret = emith_has_(rd,2,op,26,0x3f) ? (op>>16)&0x1f :-1;
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{ int ret = emith_has_(rd,4,op,26,0x3f) ? (op>>16)&0x1f :-1;
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if ((op>>26) == OP__FN)
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ret = emith_has_(rd,0,op, 0,0x3f) ? (op>>11)&0x1f :-1;
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if ((op>>26) == OP__FN2)
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ret = emith_has_(rd,1,op, 0,0x3f) ? (op>>11)&0x1f :-1;
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if ((op>>26) == OP__FN3 && (op&0x3f) == FN3_BSHFL)
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ret = emith_has_(rd,2,op, 0,0x3f) ? (op>>11)&0x1f :-1;
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if ((op>>26) == OP__FN3 && (op&0x3f) != FN3_BSHFL)
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ret = emith_has_(rd,2,op, 0,0x3f) ? (op>>16)&0x1f :-1;
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if ((op>>26) == OP__RT)
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ret = -1;
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return (ret ?: -1); // Z0 doesn't have dependencies
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@ -970,29 +990,23 @@ static void emith_log_imm(int op, int rd, int rs, u32 imm)
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#define emith_asr(d, s, cnt) \
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EMIT(MIPS_ASR_IMM(d, s, cnt))
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#if defined(__mips_isa_rev) && __mips_isa_rev >= 2
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#define emith_ror(d, s, cnt) \
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EMIT(MIPS_ROR_IMM(d, s, cnt))
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#else
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#define emith_ror(d, s, cnt) do { \
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EMIT(MIPS_LSL_IMM(AT, s, 32-(cnt))); \
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EMIT(MIPS_LSR_IMM(d, s, cnt)); \
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EMIT(MIPS_OR_REG(d, d, AT)); \
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if (__mips_isa_rev < 2) { \
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EMIT(MIPS_LSL_IMM(AT, s, 32-(cnt))); \
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EMIT(MIPS_LSR_IMM(d, s, cnt)); \
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EMIT(MIPS_OR_REG(d, d, AT)); \
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} else EMIT(MIPS_ROR_IMM(d, s, cnt)); \
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} while (0)
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#endif
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#define emith_ror_c(cond, d, s, cnt) \
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emith_ror(d, s, cnt)
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#if defined(__mips_isa_rev) && __mips_isa_rev >= 2
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#define emith_rol(d, s, cnt) \
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EMIT(MIPS_ROR_IMM(d, s, 32-(cnt)))
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#else
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#define emith_rol(d, s, cnt) do { \
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EMIT(MIPS_LSR_IMM(AT, s, 32-(cnt))); \
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EMIT(MIPS_LSL_IMM(d, s, cnt)); \
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EMIT(MIPS_OR_REG(d, d, AT)); \
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if (__mips_isa_rev < 2) { \
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EMIT(MIPS_LSR_IMM(AT, s, 32-(cnt))); \
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EMIT(MIPS_LSL_IMM(d, s, cnt)); \
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EMIT(MIPS_OR_REG(d, d, AT)); \
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} else EMIT(MIPS_ROR_IMM(d, s, 32-(cnt))); \
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} while (0)
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#endif
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#define emith_rorc(d) do { \
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emith_lsr(d, d, 1); \
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@ -1082,13 +1096,11 @@ static void emith_log_imm(int op, int rd, int rs, u32 imm)
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} while (0)
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// signed/unsigned extend
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#if defined(__mips_isa_rev) && __mips_isa_rev >= 2
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#define emith_clear_msb(d, s, count) /* bits to clear */ \
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EMIT(MIPS_EXT_IMM(d, s, 0, 32-(count)))
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#else
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#define emith_clear_msb(d, s, count) /* bits to clear */ do { \
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u32 t; \
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if ((count) >= 16) { \
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if (__mips_isa_rev >= 2) \
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EMIT(MIPS_EXT_IMM(d, s, 0, 32-(count))); \
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else if ((count) >= 16) { \
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t = (count) - 16; \
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t = 0xffff >> t; \
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emith_and_r_r_imm(d, s, t); \
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@ -1097,27 +1109,19 @@ static void emith_log_imm(int op, int rd, int rs, u32 imm)
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emith_lsr(d, d, count); \
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} \
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} while (0)
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#endif
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#define emith_clear_msb_c(cond, d, s, count) \
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emith_clear_msb(d, s, count)
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#if defined(__mips_isa_rev) && __mips_isa_rev >= 2
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#define emith_sext(d, s, count) /* bits to keep */ do { \
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if (count == 8) \
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if (__mips_isa_rev >= 2 && count == 8) \
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EMIT(MIPS_SEB_REG(d, s)); \
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else if (count == 16) \
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else if (__mips_isa_rev >= 2 && count == 16) \
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EMIT(MIPS_SEH_REG(d, s)); \
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else { \
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emith_lsl(d, s, 32-(count)); \
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emith_asr(d, d, 32-(count)); \
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} \
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} while (0)
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#else
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#define emith_sext(d, s, count) /* bits to keep */ do { \
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emith_lsl(d, s, 32-(count)); \
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emith_asr(d, d, 32-(count)); \
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} while (0)
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#endif
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// multiply Rd = Rn*Rm (+ Ra); NB: next 2 insns after MFLO/MFHI mustn't be MULT
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static u8 *last_lohi;
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@ -1716,26 +1720,20 @@ static int emith_cond_check(int cond, int *r)
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EMITH_SJMP_END(DCOND_EQ); \
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} while (0)
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#if defined(__mips_isa_rev) && __mips_isa_rev >= 2
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#define emith_write_sr(sr, srcr) \
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EMIT(MIPS_INS_IMM(sr, srcr, 0, 10))
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#else
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#define emith_write_sr(sr, srcr) do { \
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emith_lsr(sr, sr , 10); emith_lsl(sr, sr, 10); \
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emith_lsl(AT, srcr, 22); emith_lsr(AT, AT, 22); \
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emith_or_r_r(sr, AT); \
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if (__mips_isa_rev < 2) { \
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emith_lsr(sr, sr , 10); emith_lsl(sr, sr, 10); \
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emith_lsl(AT, srcr, 22); emith_lsr(AT, AT, 22); \
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emith_or_r_r(sr, AT); \
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} else EMIT(MIPS_INS_IMM(sr, srcr, 0, 10)); \
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} while (0)
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#endif
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#if defined(__mips_isa_rev) && __mips_isa_rev >= 2
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#define emith_carry_to_t(sr, is_sub) \
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EMIT(MIPS_INS_IMM(sr, FC, 0, 1))
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#else
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#define emith_carry_to_t(sr, is_sub) do { \
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emith_and_r_imm(sr, 0xfffffffe); \
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emith_or_r_r(sr, FC); \
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if (__mips_isa_rev < 2) { \
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emith_and_r_imm(sr, 0xfffffffe); \
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emith_or_r_r(sr, FC); \
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} else EMIT(MIPS_INS_IMM(sr, FC, 0, 1)); \
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} while (0)
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#endif
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#define emith_t_to_carry(sr, is_sub) do { \
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emith_and_r_r_imm(FC, sr, 1); \
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