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https://github.com/RaySollium99/picodrive.git
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sh2 drc: cleanup, fix for drc crash, for mips code emitter
This commit is contained in:
kub
parent
9760505eaf
commit
90b1c9db91
12 changed files with 151 additions and 120 deletions
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@ -440,7 +440,7 @@ static int rcache_get_tmp(void);
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static void rcache_free_tmp(int hr);
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// Note: Register assignment goes by ABI convention. Caller save registers are
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// TEMPORARY, the others are PRESERVED. Unusable regs are omitted.
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// TEMPORARY, callee save registers are PRESERVED. Unusable regs are omitted.
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// there must be at least the free (not context or statically mapped) amount of
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// PRESERVED/TEMPORARY registers used by handlers in worst case (currently 4).
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// there must be at least 3 PARAM, and PARAM+TEMPORARY must be at least 4.
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@ -496,6 +496,11 @@ static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
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static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
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static void REGPARM(2) (*sh2_drc_write32)(u32 a, u32 d);
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#ifdef DRC_SR_REG
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void REGPARM(1) (*sh2_drc_save_sr)(SH2 *sh2);
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void REGPARM(1) (*sh2_drc_restore_sr)(SH2 *sh2);
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#endif
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// flags for memory access
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#define MF_SIZEMASK 0x03 // size of access
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#define MF_POSTINCR 0x10 // post increment (for read_rr)
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@ -1578,7 +1583,7 @@ static void rcache_unmap_vreg(int x)
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FOR_ALL_BITS_SET_DO(cache_regs[x].gregs, i,
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if (guest_regs[i].flags & GRF_DIRTY) {
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// if a dirty reg is unmapped save its value to context
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if ((~rcache_regs_discard | rcache_regs_now) & (1 << i))
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if (~rcache_regs_discard & (1 << i))
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emith_ctx_write(cache_regs[x].hreg, i * 4);
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guest_regs[i].flags &= ~GRF_DIRTY;
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}
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@ -3107,6 +3112,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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op_flags[i+1] |= OF_BTARGET; // RTE entrypoint in case of SR.IMASK change
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// unify T and SR since rcache doesn't know about "virtual" guest regs
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if (ops[i].source & BITMASK1(SHR_T)) ops[i].source |= BITMASK1(SHR_SR);
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if (ops[i].dest & BITMASK1(SHR_T)) ops[i].source |= BITMASK1(SHR_SR);
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if (ops[i].dest & BITMASK1(SHR_T)) ops[i].dest |= BITMASK1(SHR_SR);
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#if LOOP_DETECTION
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// loop types detected:
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@ -5028,7 +5034,6 @@ static void sh2_generate_utils(void)
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emith_move_r_r_ptr(arg0, CONTEXT_REG);
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emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
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emith_call(sh2_translate);
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/* just after lookup function, jump to address returned */
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emith_tst_r_r_ptr(RET_REG, RET_REG);
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EMITH_SJMP_START(DCOND_EQ);
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emith_jump_reg_c(DCOND_NE, RET_REG);
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@ -5057,8 +5062,8 @@ static void sh2_generate_utils(void)
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emith_ctx_read(arg2, offsetof(SH2, rts_cache_idx));
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emith_add_r_r_r_lsl_ptr(arg1, CONTEXT_REG, arg2, 0);
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emith_read_r_r_offs(arg3, arg1, offsetof(SH2, rts_cache));
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#if (DRC_DEBUG & 128)
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emith_cmp_r_r(arg0, arg3);
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#if (DRC_DEBUG & 128)
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EMITH_SJMP_START(DCOND_EQ);
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emith_move_r_ptr_imm(arg3, (uptr)&rcmiss);
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emith_read_r_r_offs_c(DCOND_NE, arg1, arg3, 0);
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@ -5067,7 +5072,6 @@ static void sh2_generate_utils(void)
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emith_jump_cond(DCOND_NE, sh2_drc_dispatcher);
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EMITH_SJMP_END(DCOND_EQ);
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#else
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emith_cmp_r_r(arg0, arg3);
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emith_jump_cond(DCOND_NE, sh2_drc_dispatcher);
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#endif
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emith_read_r_r_offs_ptr(arg0, arg1, offsetof(SH2, rts_cache) + sizeof(void *));
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@ -5109,7 +5113,7 @@ static void sh2_generate_utils(void)
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emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
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// push PC
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rcache_get_reg_arg(0, SHR_SP, NULL);
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emith_ctx_read(arg1, SHR_PC * 4);
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rcache_get_reg_arg(1, SHR_PC, NULL);
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emith_move_r_r_ptr(arg2, CONTEXT_REG);
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rcache_invalidate_tmp();
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emith_call(p32x_sh2_write32);
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@ -5143,6 +5147,24 @@ static void sh2_generate_utils(void)
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emith_jump(sh2_drc_dispatcher);
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emith_flush();
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#ifdef DRC_SR_REG
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// sh2_drc_save_sr(SH2 *sh2)
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sh2_drc_save_sr = (void *)tcache_ptr;
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tmp = rcache_get_reg(SHR_SR, RC_GR_READ, NULL);
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emith_write_r_r_offs(tmp, arg0, SHR_SR * 4);
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rcache_invalidate();
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emith_ret();
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emith_flush();
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// sh2_drc_restore_sr(SH2 *sh2)
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sh2_drc_restore_sr = (void *)tcache_ptr;
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tmp = rcache_get_reg(SHR_SR, RC_GR_WRITE, NULL);
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emith_read_r_r_offs(tmp, arg0, SHR_SR * 4);
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rcache_flush();
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emith_ret();
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emith_flush();
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#endif
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#ifdef PDB_NET
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// debug
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#define MAKE_READ_WRAPPER(func) { \
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@ -5204,6 +5226,10 @@ static void sh2_generate_utils(void)
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host_dasm_new_symbol(sh2_drc_read8_poll);
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host_dasm_new_symbol(sh2_drc_read16_poll);
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host_dasm_new_symbol(sh2_drc_read32_poll);
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#ifdef DRC_SR_REG
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host_dasm_new_symbol(sh2_drc_save_sr);
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host_dasm_new_symbol(sh2_drc_restore_sr);
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#endif
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#endif
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#if DRC_DEBUG
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@ -5273,12 +5299,12 @@ static void sh2_smc_rm_blocks(u32 a, int len, int tcache_id, u32 shift)
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#endif
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}
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void sh2_drc_wcheck_ram(unsigned int a, unsigned len, SH2 *sh2)
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void sh2_drc_wcheck_ram(u32 a, unsigned len, SH2 *sh2)
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{
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sh2_smc_rm_blocks(a, len, 0, SH2_DRCBLK_RAM_SHIFT);
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}
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void sh2_drc_wcheck_da(unsigned int a, unsigned len, SH2 *sh2)
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void sh2_drc_wcheck_da(u32 a, unsigned len, SH2 *sh2)
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{
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sh2_smc_rm_blocks(a, len, 1 + sh2->is_slave, SH2_DRCBLK_DA_SHIFT);
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}
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@ -5295,7 +5321,7 @@ int sh2_execute_drc(SH2 *sh2c, int cycles)
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sh2_drc_entry(sh2c);
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// TODO: irq cycles
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ret_cycles = (signed int)sh2c->sr >> 12;
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ret_cycles = (int32_t)sh2c->sr >> 12;
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if (ret_cycles > 0)
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dbg(1, "warning: drc returned with cycles: %d", ret_cycles);
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@ -5777,6 +5803,7 @@ u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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break;
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case 1: // DIV0U 0000000000011001
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CHECK_UNHANDLED_BITS(0xf00, undefined);
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opd->source = BITMASK1(SHR_SR);
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opd->dest = BITMASK2(SHR_SR, SHR_T);
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break;
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case 2: // MOVT Rn 0000nnnn00101001
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@ -5877,7 +5904,7 @@ u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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opd->dest = BITMASK2(GET_Rn(), SHR_MEM);
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break;
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case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
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opd->source = BITMASK2(GET_Rm(), GET_Rn());
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opd->source = BITMASK3(SHR_SR, GET_Rm(), GET_Rn());
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opd->dest = BITMASK2(SHR_SR, SHR_T);
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break;
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case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
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@ -6470,6 +6497,9 @@ end:
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last_btarget = 0;
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op = 0; // delay/poll insns counter
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for (i = 0, pc = base_pc; i < i_end; i++, pc += 2) {
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int null;
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if ((op_flags[i] & OF_BTARGET) && dr_get_entry(pc, is_slave, &null))
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break; // branch target already compiled
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opd = &ops[i];
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crc += FETCH_OP(pc);
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@ -1,7 +1,7 @@
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int sh2_drc_init(SH2 *sh2);
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void sh2_drc_finish(SH2 *sh2);
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void sh2_drc_wcheck_ram(unsigned int a, unsigned len, SH2 *sh2);
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void sh2_drc_wcheck_da(unsigned int a, unsigned len, SH2 *sh2);
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void sh2_drc_wcheck_ram(uint32_t a, unsigned len, SH2 *sh2);
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void sh2_drc_wcheck_da(uint32_t a, unsigned len, SH2 *sh2);
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#ifdef DRC_SH2
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void sh2_drc_mem_setup(SH2 *sh2);
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@ -28,13 +28,13 @@ void sh2_drc_frame(void);
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#define OF_DELAY_LOOP (2 << 2)
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#define OF_POLL_LOOP (3 << 2)
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unsigned short scan_block(unsigned int base_pc, int is_slave,
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unsigned char *op_flags, unsigned int *end_pc,
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unsigned int *base_literals, unsigned int *end_literals);
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unsigned short scan_block(uint32_t base_pc, int is_slave,
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unsigned char *op_flags, uint32_t *end_pc,
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uint32_t *base_literals, uint32_t *end_literals);
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#if defined(DRC_SH2)
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// direct access to some host CPU registers used by the DRC
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// XXX MUST match definitions for SHR_SR in cpu/sh2/compiler.c
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#if defined(DRC_SH2) && defined(__GNUC__)
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// direct access to some host CPU registers used by the DRC
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// XXX MUST match definitions for SHR_SR in cpu/drc/emit_*.c
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#if defined(__arm__)
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#define DRC_SR_REG "r10"
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#elif defined(__aarch64__)
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@ -47,19 +47,20 @@ unsigned short scan_block(unsigned int base_pc, int is_slave,
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#define DRC_SR_REG "edi"
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#elif defined(__x86_64__)
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#define DRC_SR_REG "ebx"
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#else
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#warning "direct DRC register access not available for this host"
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#endif
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#endif
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#ifdef DRC_SR_REG
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#define DRC_DECLARE_SR register int sh2_sr asm(DRC_SR_REG)
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extern void REGPARM(1) (*sh2_drc_save_sr)(SH2 *sh2);
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extern void REGPARM(1) (*sh2_drc_restore_sr)(SH2 *sh2);
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#define DRC_DECLARE_SR register int32_t sh2_sr asm(DRC_SR_REG)
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#define DRC_SAVE_SR(sh2) \
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if ((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN) \
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sh2->sr = sh2_sr;
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if (likely((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN)) \
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sh2_drc_save_sr(sh2)
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#define DRC_RESTORE_SR(sh2) \
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if ((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN) \
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sh2_sr = sh2->sr;
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if (likely((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN)) \
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sh2_drc_restore_sr(sh2)
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#else
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#define DRC_DECLARE_SR
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#define DRC_SAVE_SR(sh2)
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@ -14,13 +14,13 @@ typedef enum {
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typedef struct SH2_
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{
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// registers. this MUST correlate with enum sh2_reg_e.
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unsigned int r[16] ALIGNED(32);
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unsigned int pc; // 40
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unsigned int ppc;
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unsigned int pr;
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unsigned int sr;
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unsigned int gbr, vbr; // 50
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unsigned int mach, macl; // 58
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uint32_t r[16] ALIGNED(32);
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uint32_t pc; // 40
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uint32_t ppc;
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uint32_t pr;
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uint32_t sr;
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uint32_t gbr, vbr; // 50
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uint32_t mach, macl; // 58
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// common
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const void *read8_map;
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@ -48,14 +48,14 @@ typedef struct SH2_
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#define SH2_STATE_VPOLL (1 << 3) // polling VDP
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#define SH2_STATE_RPOLL (1 << 4) // polling address in SDRAM
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unsigned int state;
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unsigned int poll_addr;
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uint32_t poll_addr;
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int poll_cycles;
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int poll_cnt;
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// DRC branch cache. size must be 2^n and <=128
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int rts_cache_idx;
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struct { unsigned int pc; void *code; } rts_cache[16];
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struct { unsigned int pc; void *code; } branch_cache[128];
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struct { uint32_t pc; void *code; } rts_cache[16];
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struct { uint32_t pc; void *code; } branch_cache[128];
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// interpreter stuff
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int icount; // cycles left in current timeslice
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@ -79,15 +79,15 @@ typedef struct SH2_
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unsigned int mult_m68k_to_sh2;
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unsigned int mult_sh2_to_m68k;
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unsigned char data_array[0x1000]; // cache (can be used as RAM)
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unsigned int peri_regs[0x200/4]; // periphereal regs
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uint8_t data_array[0x1000]; // cache (can be used as RAM)
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uint32_t peri_regs[0x200/4]; // periphereal regs
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} SH2;
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#define CYCLE_MULT_SHIFT 10
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#define C_M68K_TO_SH2(xsh2, c) \
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(int)(((unsigned long long)(c) * (xsh2)->mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)
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(int)(((uint64_t)(c) * (xsh2)->mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)
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#define C_SH2_TO_M68K(xsh2, c) \
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(int)(((unsigned long long)(c+3U) * (xsh2)->mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)
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(int)(((uint64_t)(c+3U) * (xsh2)->mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)
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int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2);
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void sh2_finish(SH2 *sh2);
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