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sh2 drc: cleanup, fix for drc crash, for mips code emitter

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This commit is contained in:
kub 2019-12-11 20:16:14 +01:00
parent 9760505eaf
commit 90b1c9db91
12 changed files with 151 additions and 120 deletions
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31
cpu/sh2/compiler.h
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@ -1,7 +1,7 @@
int sh2_drc_init(SH2 *sh2);
void sh2_drc_finish(SH2 *sh2);
void sh2_drc_wcheck_ram(unsigned int a, unsigned len, SH2 *sh2);
void sh2_drc_wcheck_da(unsigned int a, unsigned len, SH2 *sh2);
void sh2_drc_wcheck_ram(uint32_t a, unsigned len, SH2 *sh2);
void sh2_drc_wcheck_da(uint32_t a, unsigned len, SH2 *sh2);
#ifdef DRC_SH2
void sh2_drc_mem_setup(SH2 *sh2);
@ -28,13 +28,13 @@ void sh2_drc_frame(void);
#define OF_DELAY_LOOP (2 << 2)
#define OF_POLL_LOOP (3 << 2)
unsigned short scan_block(unsigned int base_pc, int is_slave,
unsigned char *op_flags, unsigned int *end_pc,
unsigned int *base_literals, unsigned int *end_literals);
unsigned short scan_block(uint32_t base_pc, int is_slave,
unsigned char *op_flags, uint32_t *end_pc,
uint32_t *base_literals, uint32_t *end_literals);
#if defined(DRC_SH2)
// direct access to some host CPU registers used by the DRC
// XXX MUST match definitions for SHR_SR in cpu/sh2/compiler.c
#if defined(DRC_SH2) && defined(__GNUC__)
// direct access to some host CPU registers used by the DRC
// XXX MUST match definitions for SHR_SR in cpu/drc/emit_*.c
#if defined(__arm__)
#define DRC_SR_REG "r10"
#elif defined(__aarch64__)
@ -47,19 +47,20 @@ unsigned short scan_block(unsigned int base_pc, int is_slave,
#define DRC_SR_REG "edi"
#elif defined(__x86_64__)
#define DRC_SR_REG "ebx"
#else
#warning "direct DRC register access not available for this host"
#endif
#endif
#ifdef DRC_SR_REG
#define DRC_DECLARE_SR register int sh2_sr asm(DRC_SR_REG)
extern void REGPARM(1) (*sh2_drc_save_sr)(SH2 *sh2);
extern void REGPARM(1) (*sh2_drc_restore_sr)(SH2 *sh2);
#define DRC_DECLARE_SR register int32_t sh2_sr asm(DRC_SR_REG)
#define DRC_SAVE_SR(sh2) \
if ((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN) \
sh2->sr = sh2_sr;
if (likely((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN)) \
sh2_drc_save_sr(sh2)
#define DRC_RESTORE_SR(sh2) \
if ((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN) \
sh2_sr = sh2->sr;
if (likely((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN)) \
sh2_drc_restore_sr(sh2)
#else
#define DRC_DECLARE_SR
#define DRC_SAVE_SR(sh2)