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https://github.com/RaySollium99/picodrive.git
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sh2 drc: cleanup, fix for drc crash, for mips code emitter
This commit is contained in:
kub
parent
9760505eaf
commit
90b1c9db91
12 changed files with 151 additions and 120 deletions
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@ -20,6 +20,9 @@
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#define STATIC_SH2_REGS { SHR_SR,22 , SHR_R0,21 , SHR_R0+1,20 }
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// NB: the ubiquitous JZ74[46]0 uses MIPS32 Release 1, a slight MIPS II superset
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#ifndef __mips_isa_rev
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#define __mips_isa_rev 1 // surprisingly not always defined
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#endif
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// registers usable for user code: r1-r25, others reserved or special
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#define Z0 0 // zero register
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@ -333,32 +336,49 @@ static int emith_is_b(u32 op) // B
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{ return ((op>>26) & 074) == OP_BEQ ||
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((op>>26) == OP__RT && ((op>>16) & 036) == RT_BLTZ); }
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// register usage for dependency evaluation XXX better do this as in emit_arm?
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static uint64_t emith_has_rs[3] = // OP__FN, OP__RT, others
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{ 0x00fffffffffa0ff0ULL, 0x000fff0fUL, 0xffffffff0f007ff0ULL };
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static uint64_t emith_has_rt[3] = // OP__FN, OP__RT, others
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{ 0xff00fffffff00cffULL, 0x00000000UL, 0x8000ff0000000030ULL };
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static uint64_t emith_has_rd[3] = // OP__FN, OP__RT, others (rt instead of rd)
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{ 0xff00fffffff50fffULL, 0x00000000UL, 0x119100ff0f00ff00ULL };
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static uint64_t emith_has_rs[5] = // OP__FN1-3, OP__RT, others
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{ 0x005ffcffffda0fd2ULL, 0x0000003300000037ULL, 0x00000000000000ffULL,
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0x800f5f0fUL, 0xf7ffffff0ff07ff0ULL };
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static uint64_t emith_has_rt[5] = // OP__FN1-3, OP__RT, others
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{ 0xdd5ffcffffd00cddULL, 0x0000000000000037ULL, 0x0000001100000000ULL,
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0x00000000UL, 0x80007f440c300030ULL };
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static uint64_t emith_has_rd[5] = // OP__FN1-3, OP__RT, others(rt instead of rd)
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{ 0xdd00fcff00d50edfULL, 0x0000003300000004ULL, 0x08000011000000ffULL,
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0x00000000UL, 0x119100ff0f00ff00ULL };
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#define emith_has_(rx,ix,op,sa,m) \
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(emith_has_##rx[ix] & (1ULL << (((op)>>(sa)) & (m))))
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static int emith_rs(u32 op)
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{ if ((op>>26) == OP__FN)
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return emith_has_(rs,0,op, 0,0x3f) ? (op>>21)&0x1f : 0;
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if ((op>>26) == OP__FN2)
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return emith_has_(rs,1,op, 0,0x3f) ? (op>>21)&0x1f : 0;
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if ((op>>26) == OP__FN3)
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return emith_has_(rs,2,op, 0,0x3f) ? (op>>21)&0x1f : 0;
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if ((op>>26) == OP__RT)
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return emith_has_(rs,1,op,16,0x1f) ? (op>>21)&0x1f : 0;
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return emith_has_(rs,2,op,26,0x3f) ? (op>>21)&0x1f : 0;
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return emith_has_(rs,3,op,16,0x1f) ? (op>>21)&0x1f : 0;
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return emith_has_(rs,4,op,26,0x3f) ? (op>>21)&0x1f : 0;
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}
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static int emith_rt(u32 op)
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{ if ((op>>26) == OP__FN)
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return emith_has_(rt,0,op, 0,0x3f) ? (op>>16)&0x1f : 0;
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if ((op>>26) == OP__FN2)
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return emith_has_(rt,1,op, 0,0x3f) ? (op>>16)&0x1f : 0;
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if ((op>>26) == OP__FN3)
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return emith_has_(rt,2,op, 0,0x3f) ? (op>>16)&0x1f : 0;
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if ((op>>26) == OP__RT)
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return 0;
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return emith_has_(rt,2,op,26,0x3f) ? (op>>16)&0x1f : 0;
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return emith_has_(rt,4,op,26,0x3f) ? (op>>16)&0x1f : 0;
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}
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static int emith_rd(u32 op)
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{ int ret = emith_has_(rd,2,op,26,0x3f) ? (op>>16)&0x1f :-1;
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{ int ret = emith_has_(rd,4,op,26,0x3f) ? (op>>16)&0x1f :-1;
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if ((op>>26) == OP__FN)
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ret = emith_has_(rd,0,op, 0,0x3f) ? (op>>11)&0x1f :-1;
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if ((op>>26) == OP__FN2)
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ret = emith_has_(rd,1,op, 0,0x3f) ? (op>>11)&0x1f :-1;
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if ((op>>26) == OP__FN3 && (op&0x3f) == FN3_BSHFL)
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ret = emith_has_(rd,2,op, 0,0x3f) ? (op>>11)&0x1f :-1;
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if ((op>>26) == OP__FN3 && (op&0x3f) != FN3_BSHFL)
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ret = emith_has_(rd,2,op, 0,0x3f) ? (op>>16)&0x1f :-1;
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if ((op>>26) == OP__RT)
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ret = -1;
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return (ret ?: -1); // Z0 doesn't have dependencies
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@ -970,29 +990,23 @@ static void emith_log_imm(int op, int rd, int rs, u32 imm)
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#define emith_asr(d, s, cnt) \
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EMIT(MIPS_ASR_IMM(d, s, cnt))
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#if defined(__mips_isa_rev) && __mips_isa_rev >= 2
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#define emith_ror(d, s, cnt) \
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EMIT(MIPS_ROR_IMM(d, s, cnt))
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#else
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#define emith_ror(d, s, cnt) do { \
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EMIT(MIPS_LSL_IMM(AT, s, 32-(cnt))); \
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EMIT(MIPS_LSR_IMM(d, s, cnt)); \
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EMIT(MIPS_OR_REG(d, d, AT)); \
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if (__mips_isa_rev < 2) { \
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EMIT(MIPS_LSL_IMM(AT, s, 32-(cnt))); \
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EMIT(MIPS_LSR_IMM(d, s, cnt)); \
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EMIT(MIPS_OR_REG(d, d, AT)); \
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} else EMIT(MIPS_ROR_IMM(d, s, cnt)); \
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} while (0)
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#endif
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#define emith_ror_c(cond, d, s, cnt) \
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emith_ror(d, s, cnt)
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#if defined(__mips_isa_rev) && __mips_isa_rev >= 2
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#define emith_rol(d, s, cnt) \
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EMIT(MIPS_ROR_IMM(d, s, 32-(cnt)))
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#else
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#define emith_rol(d, s, cnt) do { \
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EMIT(MIPS_LSR_IMM(AT, s, 32-(cnt))); \
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EMIT(MIPS_LSL_IMM(d, s, cnt)); \
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EMIT(MIPS_OR_REG(d, d, AT)); \
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if (__mips_isa_rev < 2) { \
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EMIT(MIPS_LSR_IMM(AT, s, 32-(cnt))); \
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EMIT(MIPS_LSL_IMM(d, s, cnt)); \
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EMIT(MIPS_OR_REG(d, d, AT)); \
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} else EMIT(MIPS_ROR_IMM(d, s, 32-(cnt))); \
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} while (0)
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#endif
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#define emith_rorc(d) do { \
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emith_lsr(d, d, 1); \
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@ -1082,13 +1096,11 @@ static void emith_log_imm(int op, int rd, int rs, u32 imm)
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} while (0)
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// signed/unsigned extend
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#if defined(__mips_isa_rev) && __mips_isa_rev >= 2
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#define emith_clear_msb(d, s, count) /* bits to clear */ \
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EMIT(MIPS_EXT_IMM(d, s, 0, 32-(count)))
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#else
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#define emith_clear_msb(d, s, count) /* bits to clear */ do { \
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u32 t; \
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if ((count) >= 16) { \
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if (__mips_isa_rev >= 2) \
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EMIT(MIPS_EXT_IMM(d, s, 0, 32-(count))); \
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else if ((count) >= 16) { \
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t = (count) - 16; \
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t = 0xffff >> t; \
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emith_and_r_r_imm(d, s, t); \
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@ -1097,27 +1109,19 @@ static void emith_log_imm(int op, int rd, int rs, u32 imm)
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emith_lsr(d, d, count); \
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} \
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} while (0)
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#endif
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#define emith_clear_msb_c(cond, d, s, count) \
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emith_clear_msb(d, s, count)
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#if defined(__mips_isa_rev) && __mips_isa_rev >= 2
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#define emith_sext(d, s, count) /* bits to keep */ do { \
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if (count == 8) \
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if (__mips_isa_rev >= 2 && count == 8) \
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EMIT(MIPS_SEB_REG(d, s)); \
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else if (count == 16) \
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else if (__mips_isa_rev >= 2 && count == 16) \
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EMIT(MIPS_SEH_REG(d, s)); \
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else { \
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emith_lsl(d, s, 32-(count)); \
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emith_asr(d, d, 32-(count)); \
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} \
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} while (0)
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#else
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#define emith_sext(d, s, count) /* bits to keep */ do { \
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emith_lsl(d, s, 32-(count)); \
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emith_asr(d, d, 32-(count)); \
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} while (0)
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#endif
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// multiply Rd = Rn*Rm (+ Ra); NB: next 2 insns after MFLO/MFHI mustn't be MULT
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static u8 *last_lohi;
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@ -1716,26 +1720,20 @@ static int emith_cond_check(int cond, int *r)
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EMITH_SJMP_END(DCOND_EQ); \
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} while (0)
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#if defined(__mips_isa_rev) && __mips_isa_rev >= 2
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#define emith_write_sr(sr, srcr) \
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EMIT(MIPS_INS_IMM(sr, srcr, 0, 10))
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#else
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#define emith_write_sr(sr, srcr) do { \
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emith_lsr(sr, sr , 10); emith_lsl(sr, sr, 10); \
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emith_lsl(AT, srcr, 22); emith_lsr(AT, AT, 22); \
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emith_or_r_r(sr, AT); \
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if (__mips_isa_rev < 2) { \
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emith_lsr(sr, sr , 10); emith_lsl(sr, sr, 10); \
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emith_lsl(AT, srcr, 22); emith_lsr(AT, AT, 22); \
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emith_or_r_r(sr, AT); \
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} else EMIT(MIPS_INS_IMM(sr, srcr, 0, 10)); \
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} while (0)
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#endif
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#if defined(__mips_isa_rev) && __mips_isa_rev >= 2
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#define emith_carry_to_t(sr, is_sub) \
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EMIT(MIPS_INS_IMM(sr, FC, 0, 1))
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#else
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#define emith_carry_to_t(sr, is_sub) do { \
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emith_and_r_imm(sr, 0xfffffffe); \
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emith_or_r_r(sr, FC); \
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if (__mips_isa_rev < 2) { \
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emith_and_r_imm(sr, 0xfffffffe); \
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emith_or_r_r(sr, FC); \
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} else EMIT(MIPS_INS_IMM(sr, FC, 0, 1)); \
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} while (0)
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#endif
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#define emith_t_to_carry(sr, is_sub) do { \
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emith_and_r_r_imm(FC, sr, 1); \
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@ -440,7 +440,7 @@ static int rcache_get_tmp(void);
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static void rcache_free_tmp(int hr);
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// Note: Register assignment goes by ABI convention. Caller save registers are
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// TEMPORARY, the others are PRESERVED. Unusable regs are omitted.
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// TEMPORARY, callee save registers are PRESERVED. Unusable regs are omitted.
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// there must be at least the free (not context or statically mapped) amount of
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// PRESERVED/TEMPORARY registers used by handlers in worst case (currently 4).
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// there must be at least 3 PARAM, and PARAM+TEMPORARY must be at least 4.
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@ -496,6 +496,11 @@ static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
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static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
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static void REGPARM(2) (*sh2_drc_write32)(u32 a, u32 d);
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#ifdef DRC_SR_REG
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void REGPARM(1) (*sh2_drc_save_sr)(SH2 *sh2);
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void REGPARM(1) (*sh2_drc_restore_sr)(SH2 *sh2);
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#endif
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// flags for memory access
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#define MF_SIZEMASK 0x03 // size of access
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#define MF_POSTINCR 0x10 // post increment (for read_rr)
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@ -1578,7 +1583,7 @@ static void rcache_unmap_vreg(int x)
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FOR_ALL_BITS_SET_DO(cache_regs[x].gregs, i,
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if (guest_regs[i].flags & GRF_DIRTY) {
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// if a dirty reg is unmapped save its value to context
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if ((~rcache_regs_discard | rcache_regs_now) & (1 << i))
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if (~rcache_regs_discard & (1 << i))
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emith_ctx_write(cache_regs[x].hreg, i * 4);
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guest_regs[i].flags &= ~GRF_DIRTY;
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}
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@ -3107,6 +3112,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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op_flags[i+1] |= OF_BTARGET; // RTE entrypoint in case of SR.IMASK change
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// unify T and SR since rcache doesn't know about "virtual" guest regs
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if (ops[i].source & BITMASK1(SHR_T)) ops[i].source |= BITMASK1(SHR_SR);
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if (ops[i].dest & BITMASK1(SHR_T)) ops[i].source |= BITMASK1(SHR_SR);
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if (ops[i].dest & BITMASK1(SHR_T)) ops[i].dest |= BITMASK1(SHR_SR);
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#if LOOP_DETECTION
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// loop types detected:
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@ -5028,7 +5034,6 @@ static void sh2_generate_utils(void)
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emith_move_r_r_ptr(arg0, CONTEXT_REG);
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emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
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emith_call(sh2_translate);
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/* just after lookup function, jump to address returned */
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emith_tst_r_r_ptr(RET_REG, RET_REG);
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EMITH_SJMP_START(DCOND_EQ);
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emith_jump_reg_c(DCOND_NE, RET_REG);
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@ -5057,8 +5062,8 @@ static void sh2_generate_utils(void)
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emith_ctx_read(arg2, offsetof(SH2, rts_cache_idx));
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emith_add_r_r_r_lsl_ptr(arg1, CONTEXT_REG, arg2, 0);
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emith_read_r_r_offs(arg3, arg1, offsetof(SH2, rts_cache));
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#if (DRC_DEBUG & 128)
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emith_cmp_r_r(arg0, arg3);
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#if (DRC_DEBUG & 128)
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EMITH_SJMP_START(DCOND_EQ);
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emith_move_r_ptr_imm(arg3, (uptr)&rcmiss);
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emith_read_r_r_offs_c(DCOND_NE, arg1, arg3, 0);
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@ -5067,7 +5072,6 @@ static void sh2_generate_utils(void)
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emith_jump_cond(DCOND_NE, sh2_drc_dispatcher);
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EMITH_SJMP_END(DCOND_EQ);
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#else
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emith_cmp_r_r(arg0, arg3);
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emith_jump_cond(DCOND_NE, sh2_drc_dispatcher);
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#endif
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emith_read_r_r_offs_ptr(arg0, arg1, offsetof(SH2, rts_cache) + sizeof(void *));
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@ -5109,7 +5113,7 @@ static void sh2_generate_utils(void)
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emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
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// push PC
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rcache_get_reg_arg(0, SHR_SP, NULL);
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emith_ctx_read(arg1, SHR_PC * 4);
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rcache_get_reg_arg(1, SHR_PC, NULL);
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emith_move_r_r_ptr(arg2, CONTEXT_REG);
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rcache_invalidate_tmp();
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emith_call(p32x_sh2_write32);
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@ -5143,6 +5147,24 @@ static void sh2_generate_utils(void)
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emith_jump(sh2_drc_dispatcher);
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emith_flush();
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#ifdef DRC_SR_REG
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// sh2_drc_save_sr(SH2 *sh2)
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sh2_drc_save_sr = (void *)tcache_ptr;
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tmp = rcache_get_reg(SHR_SR, RC_GR_READ, NULL);
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emith_write_r_r_offs(tmp, arg0, SHR_SR * 4);
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rcache_invalidate();
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emith_ret();
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emith_flush();
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// sh2_drc_restore_sr(SH2 *sh2)
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sh2_drc_restore_sr = (void *)tcache_ptr;
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tmp = rcache_get_reg(SHR_SR, RC_GR_WRITE, NULL);
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emith_read_r_r_offs(tmp, arg0, SHR_SR * 4);
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rcache_flush();
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emith_ret();
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emith_flush();
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#endif
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#ifdef PDB_NET
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// debug
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#define MAKE_READ_WRAPPER(func) { \
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@ -5204,6 +5226,10 @@ static void sh2_generate_utils(void)
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host_dasm_new_symbol(sh2_drc_read8_poll);
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host_dasm_new_symbol(sh2_drc_read16_poll);
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host_dasm_new_symbol(sh2_drc_read32_poll);
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#ifdef DRC_SR_REG
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host_dasm_new_symbol(sh2_drc_save_sr);
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host_dasm_new_symbol(sh2_drc_restore_sr);
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#endif
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#endif
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#if DRC_DEBUG
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@ -5273,12 +5299,12 @@ static void sh2_smc_rm_blocks(u32 a, int len, int tcache_id, u32 shift)
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#endif
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}
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void sh2_drc_wcheck_ram(unsigned int a, unsigned len, SH2 *sh2)
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void sh2_drc_wcheck_ram(u32 a, unsigned len, SH2 *sh2)
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{
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sh2_smc_rm_blocks(a, len, 0, SH2_DRCBLK_RAM_SHIFT);
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}
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void sh2_drc_wcheck_da(unsigned int a, unsigned len, SH2 *sh2)
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void sh2_drc_wcheck_da(u32 a, unsigned len, SH2 *sh2)
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{
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sh2_smc_rm_blocks(a, len, 1 + sh2->is_slave, SH2_DRCBLK_DA_SHIFT);
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}
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@ -5295,7 +5321,7 @@ int sh2_execute_drc(SH2 *sh2c, int cycles)
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sh2_drc_entry(sh2c);
|
||||
|
||||
// TODO: irq cycles
|
||||
ret_cycles = (signed int)sh2c->sr >> 12;
|
||||
ret_cycles = (int32_t)sh2c->sr >> 12;
|
||||
if (ret_cycles > 0)
|
||||
dbg(1, "warning: drc returned with cycles: %d", ret_cycles);
|
||||
|
||||
|
|
@ -5777,6 +5803,7 @@ u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
break;
|
||||
case 1: // DIV0U 0000000000011001
|
||||
CHECK_UNHANDLED_BITS(0xf00, undefined);
|
||||
opd->source = BITMASK1(SHR_SR);
|
||||
opd->dest = BITMASK2(SHR_SR, SHR_T);
|
||||
break;
|
||||
case 2: // MOVT Rn 0000nnnn00101001
|
||||
|
|
@ -5877,7 +5904,7 @@ u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
opd->dest = BITMASK2(GET_Rn(), SHR_MEM);
|
||||
break;
|
||||
case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
|
||||
opd->source = BITMASK2(GET_Rm(), GET_Rn());
|
||||
opd->source = BITMASK3(SHR_SR, GET_Rm(), GET_Rn());
|
||||
opd->dest = BITMASK2(SHR_SR, SHR_T);
|
||||
break;
|
||||
case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
|
||||
|
|
@ -6470,6 +6497,9 @@ end:
|
|||
last_btarget = 0;
|
||||
op = 0; // delay/poll insns counter
|
||||
for (i = 0, pc = base_pc; i < i_end; i++, pc += 2) {
|
||||
int null;
|
||||
if ((op_flags[i] & OF_BTARGET) && dr_get_entry(pc, is_slave, &null))
|
||||
break; // branch target already compiled
|
||||
opd = &ops[i];
|
||||
crc += FETCH_OP(pc);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
int sh2_drc_init(SH2 *sh2);
|
||||
void sh2_drc_finish(SH2 *sh2);
|
||||
void sh2_drc_wcheck_ram(unsigned int a, unsigned len, SH2 *sh2);
|
||||
void sh2_drc_wcheck_da(unsigned int a, unsigned len, SH2 *sh2);
|
||||
void sh2_drc_wcheck_ram(uint32_t a, unsigned len, SH2 *sh2);
|
||||
void sh2_drc_wcheck_da(uint32_t a, unsigned len, SH2 *sh2);
|
||||
|
||||
#ifdef DRC_SH2
|
||||
void sh2_drc_mem_setup(SH2 *sh2);
|
||||
|
|
@ -28,13 +28,13 @@ void sh2_drc_frame(void);
|
|||
#define OF_DELAY_LOOP (2 << 2)
|
||||
#define OF_POLL_LOOP (3 << 2)
|
||||
|
||||
unsigned short scan_block(unsigned int base_pc, int is_slave,
|
||||
unsigned char *op_flags, unsigned int *end_pc,
|
||||
unsigned int *base_literals, unsigned int *end_literals);
|
||||
unsigned short scan_block(uint32_t base_pc, int is_slave,
|
||||
unsigned char *op_flags, uint32_t *end_pc,
|
||||
uint32_t *base_literals, uint32_t *end_literals);
|
||||
|
||||
#if defined(DRC_SH2)
|
||||
#if defined(DRC_SH2) && defined(__GNUC__)
|
||||
// direct access to some host CPU registers used by the DRC
|
||||
// XXX MUST match definitions for SHR_SR in cpu/sh2/compiler.c
|
||||
// XXX MUST match definitions for SHR_SR in cpu/drc/emit_*.c
|
||||
#if defined(__arm__)
|
||||
#define DRC_SR_REG "r10"
|
||||
#elif defined(__aarch64__)
|
||||
|
|
@ -47,19 +47,20 @@ unsigned short scan_block(unsigned int base_pc, int is_slave,
|
|||
#define DRC_SR_REG "edi"
|
||||
#elif defined(__x86_64__)
|
||||
#define DRC_SR_REG "ebx"
|
||||
#else
|
||||
#warning "direct DRC register access not available for this host"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef DRC_SR_REG
|
||||
#define DRC_DECLARE_SR register int sh2_sr asm(DRC_SR_REG)
|
||||
extern void REGPARM(1) (*sh2_drc_save_sr)(SH2 *sh2);
|
||||
extern void REGPARM(1) (*sh2_drc_restore_sr)(SH2 *sh2);
|
||||
|
||||
#define DRC_DECLARE_SR register int32_t sh2_sr asm(DRC_SR_REG)
|
||||
#define DRC_SAVE_SR(sh2) \
|
||||
if ((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN) \
|
||||
sh2->sr = sh2_sr;
|
||||
if (likely((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN)) \
|
||||
sh2_drc_save_sr(sh2)
|
||||
#define DRC_RESTORE_SR(sh2) \
|
||||
if ((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN) \
|
||||
sh2_sr = sh2->sr;
|
||||
if (likely((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN)) \
|
||||
sh2_drc_restore_sr(sh2)
|
||||
#else
|
||||
#define DRC_DECLARE_SR
|
||||
#define DRC_SAVE_SR(sh2)
|
||||
|
|
|
|||
|
|
@ -14,13 +14,13 @@ typedef enum {
|
|||
typedef struct SH2_
|
||||
{
|
||||
// registers. this MUST correlate with enum sh2_reg_e.
|
||||
unsigned int r[16] ALIGNED(32);
|
||||
unsigned int pc; // 40
|
||||
unsigned int ppc;
|
||||
unsigned int pr;
|
||||
unsigned int sr;
|
||||
unsigned int gbr, vbr; // 50
|
||||
unsigned int mach, macl; // 58
|
||||
uint32_t r[16] ALIGNED(32);
|
||||
uint32_t pc; // 40
|
||||
uint32_t ppc;
|
||||
uint32_t pr;
|
||||
uint32_t sr;
|
||||
uint32_t gbr, vbr; // 50
|
||||
uint32_t mach, macl; // 58
|
||||
|
||||
// common
|
||||
const void *read8_map;
|
||||
|
|
@ -48,14 +48,14 @@ typedef struct SH2_
|
|||
#define SH2_STATE_VPOLL (1 << 3) // polling VDP
|
||||
#define SH2_STATE_RPOLL (1 << 4) // polling address in SDRAM
|
||||
unsigned int state;
|
||||
unsigned int poll_addr;
|
||||
uint32_t poll_addr;
|
||||
int poll_cycles;
|
||||
int poll_cnt;
|
||||
|
||||
// DRC branch cache. size must be 2^n and <=128
|
||||
int rts_cache_idx;
|
||||
struct { unsigned int pc; void *code; } rts_cache[16];
|
||||
struct { unsigned int pc; void *code; } branch_cache[128];
|
||||
struct { uint32_t pc; void *code; } rts_cache[16];
|
||||
struct { uint32_t pc; void *code; } branch_cache[128];
|
||||
|
||||
// interpreter stuff
|
||||
int icount; // cycles left in current timeslice
|
||||
|
|
@ -79,15 +79,15 @@ typedef struct SH2_
|
|||
unsigned int mult_m68k_to_sh2;
|
||||
unsigned int mult_sh2_to_m68k;
|
||||
|
||||
unsigned char data_array[0x1000]; // cache (can be used as RAM)
|
||||
unsigned int peri_regs[0x200/4]; // periphereal regs
|
||||
uint8_t data_array[0x1000]; // cache (can be used as RAM)
|
||||
uint32_t peri_regs[0x200/4]; // periphereal regs
|
||||
} SH2;
|
||||
|
||||
#define CYCLE_MULT_SHIFT 10
|
||||
#define C_M68K_TO_SH2(xsh2, c) \
|
||||
(int)(((unsigned long long)(c) * (xsh2)->mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)
|
||||
(int)(((uint64_t)(c) * (xsh2)->mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)
|
||||
#define C_SH2_TO_M68K(xsh2, c) \
|
||||
(int)(((unsigned long long)(c+3U) * (xsh2)->mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)
|
||||
(int)(((uint64_t)(c+3U) * (xsh2)->mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)
|
||||
|
||||
int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2);
|
||||
void sh2_finish(SH2 *sh2);
|
||||
|
|
|
|||
|
|
@ -60,9 +60,8 @@
|
|||
|
||||
// load data address (LDR) either via literal pool or via GOT
|
||||
#ifdef __PIC__
|
||||
// can't use pool loads since ldr= only allows symbol or constants, not expr :-(
|
||||
// can't use pool loads since ldr= only allows a symbol or a constant expr :-(
|
||||
#define PIC_LDR_INIT() \
|
||||
.ifndef PIC_LDR_DEF; PIC_LDR_DEF=1; \
|
||||
.macro pic_ldr r t a; \
|
||||
ldr \r, [pc, $.LD\@-.-8]; \
|
||||
ldr \t, [pc, $.LD\@-.-4]; \
|
||||
|
|
@ -71,14 +70,11 @@
|
|||
add pc, $4; \
|
||||
.LD\@:.word _GLOBAL_OFFSET_TABLE_-.LP\@-8; \
|
||||
.word \a(GOT); \
|
||||
.endm; \
|
||||
.endif;
|
||||
#define PIC_LDR(r,t,a) \
|
||||
pic_ldr r, t, a
|
||||
.endm;
|
||||
#define PIC_LDR(r,t,a) pic_ldr r, t, a
|
||||
#else
|
||||
#define PIC_LDR_INIT()
|
||||
#define PIC_LDR(r,t,a) \
|
||||
ldr r, =a
|
||||
#define PIC_LDR(r,t,a) ldr r, =a
|
||||
#endif
|
||||
|
||||
#endif /* __ARM_FEATURES_H__ */
|
||||
|
|
|
|||
|
|
@ -17,10 +17,12 @@
|
|||
#define NOINLINE __attribute__((noinline))
|
||||
#define ALIGNED(n) __attribute__((aligned(n)))
|
||||
#define unlikely(x) __builtin_expect((x), 0)
|
||||
#define likely(x) __builtin_expect(!!(x), 1)
|
||||
#else
|
||||
#define NOINLINE
|
||||
#define ALIGNED(n)
|
||||
#define unlikely(x) (x)
|
||||
#define likely(x) (x)
|
||||
#endif
|
||||
|
||||
#ifdef _MSC_VER
|
||||
|
|
|
|||
|
|
@ -435,7 +435,7 @@ static int software_interrupt(unsigned int pc, unsigned int insn, char *buf, siz
|
|||
return 1;
|
||||
}
|
||||
|
||||
int disarm(uintptr_t pc, uint32_t insn, char *buf, size_t buf_len, uintptr_t *addr)
|
||||
int disarm(uintptr_t pc, uint32_t insn, char *buf, size_t buf_len, unsigned long *addr)
|
||||
{
|
||||
*addr = 0;
|
||||
|
||||
|
|
@ -467,7 +467,7 @@ int disarm(uintptr_t pc, uint32_t insn, char *buf, size_t buf_len, uintptr_t *ad
|
|||
return block_data_transfer(pc, insn, buf, buf_len);
|
||||
|
||||
if ((insn & 0x0e000000) == 0x0a000000) {
|
||||
*addr = (long)pc + 8 + ((long)(insn << 8) >> 6);
|
||||
*addr = (unsigned long)pc+8 + ((unsigned long)(insn << 8) >> 6);
|
||||
return branch(pc, insn, buf, buf_len);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,6 @@
|
|||
#ifndef DISARM_H
|
||||
#define DISARM_H
|
||||
|
||||
int disarm(uintptr_t pc, uint32_t insn, char *buf, size_t buf_len, uintptr_t *sym);
|
||||
int disarm(uintptr_t pc, uint32_t insn, char *buf, size_t buf_len, unsigned long *sym);
|
||||
|
||||
#endif /* DISARM_H */
|
||||
|
|
|
|||
|
|
@ -6,8 +6,9 @@
|
|||
* See COPYING file in the top-level directory.
|
||||
*/
|
||||
|
||||
// XXX unimplemented: SYSCALL, BREAK, SYNC, SDBBP, T*, CACHE, PREF,
|
||||
// MOVF/MOVT, LWC*/LDC*, SWC*/SDC*, COP*.
|
||||
// unimplemented insns: MOV[FT], SYSCALL, BREAK, SYNC, SYNCI, T*, SDBBP, RDHWR,
|
||||
// CACHE, PREF, LWC*/LDC*, SWC*/SDC*, and all of COP* (fpu, mmu, irq, exc, ...)
|
||||
// unimplemented variants of insns: EHB, SSNOP (both SLL zero), JALR.HB, JR.HB
|
||||
// however, it's certainly good enough for anything picodrive DRC throws at it.
|
||||
|
||||
#include <stdio.h>
|
||||
|
|
@ -79,6 +80,7 @@ struct insn {
|
|||
#define OP_SPECIAL 0x00
|
||||
static const struct insn special_insns[] = {
|
||||
{0x00, S_IMM_DT, "sll"},
|
||||
// {0x01, , "movf\0movt"},
|
||||
{0x02, S_IMM_DT|SR_BIT, "srl\0rotr"},
|
||||
{0x03, S_IMM_DT, "sra"},
|
||||
{0x04, REG_DTS, "sllv"},
|
||||
|
|
@ -146,6 +148,7 @@ static const struct insn special2_insns[] = {
|
|||
{0x21, REG_DS, "clo" },
|
||||
{0x24, REG_DS, "dclz" },
|
||||
{0x25, REG_DS, "dclo" },
|
||||
// {0x37, , "sdbbp" },
|
||||
};
|
||||
|
||||
// instructions with opcode SPECIAL3 (R-type)
|
||||
|
|
@ -159,6 +162,7 @@ static const struct insn special3_insns[] = {
|
|||
{0x05, F_IMM_TS, "dinsm" },
|
||||
{0x06, F_IMM_TS, "dinsu" },
|
||||
{0x07, F_IMM_TS, "dins" },
|
||||
// {0x3b, , "rdhwr" },
|
||||
};
|
||||
|
||||
// instruction with opcode SPECIAL3 and function *BSHFL
|
||||
|
|
@ -192,6 +196,7 @@ static const struct insn regimm_insns[] = {
|
|||
{0x12, B_IMM_S, "bltzall"},
|
||||
{0x13, B_IMM_S, "bgezall"},
|
||||
{0x13, B_IMM_S, "bgezall"},
|
||||
// {0x1f, , "synci" },
|
||||
};
|
||||
|
||||
// instructions with other opcodes (I-type)
|
||||
|
|
@ -316,7 +321,7 @@ static unsigned long j_target(unsigned long pc, uint32_t insn)
|
|||
}
|
||||
|
||||
// main disassembler function
|
||||
int dismips(uintptr_t pc, uint32_t insn, char *buf, size_t buflen, uintptr_t *sym)
|
||||
int dismips(uintptr_t pc, uint32_t insn, char *buf, size_t buflen, unsigned long *sym)
|
||||
{
|
||||
const struct insn *pi = decode_insn(insn);
|
||||
char *rs = register_names[(insn >> 21) & 0x1f];
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#ifndef DISMIPS_H
|
||||
#define DISMIPS_H
|
||||
|
||||
int dismips(uintptr_t pc, uint32_t insn, char *buf, size_t buf_len, uintptr_t *sym);
|
||||
int dismips(uintptr_t pc, uint32_t insn, char *buf, size_t buf_len, unsigned long *sym);
|
||||
|
||||
#endif /* DISMIPS_H */
|
||||
|
|
|
|||
|
|
@ -37,14 +37,14 @@ void host_dasm(void *addr, int len)
|
|||
void *end = (char *)addr + len;
|
||||
const char *name;
|
||||
char buf[64];
|
||||
long insn, symaddr;
|
||||
unsigned long insn, symaddr;
|
||||
|
||||
while (addr < end) {
|
||||
name = lookup_name(addr);
|
||||
if (name != NULL)
|
||||
printf("%s:\n", name);
|
||||
|
||||
insn = *(long *)addr;
|
||||
insn = *(unsigned long *)addr;
|
||||
printf(" %08lx %08lx ", (long)addr, insn);
|
||||
if(disasm((unsigned)addr, insn, buf, sizeof(buf), &symaddr))
|
||||
{
|
||||
|
|
|
|||
|
|
@ -12,15 +12,12 @@ ENDIAN=
|
|||
compile_rodata ()
|
||||
{
|
||||
$CC $CFLAGS -I .. -c /tmp/getoffs.c -o /tmp/getoffs.o || exit 1
|
||||
# echo 'void dummy(void) { asm(""::"r" (&val)); }' >> /tmp/getoffs.c
|
||||
# $CC $CFLAGS -I .. -nostdlib -Wl,-edummy /tmp/getoffs.c \
|
||||
# -o /tmp/getoffs.o || exit 1
|
||||
# find the name of the .rodata section (in case -fdata-sections is used)
|
||||
rosect=$(readelf -S /tmp/getoffs.o | grep '\.rodata\|\.sdata' |
|
||||
sed 's/^[^.]*././;s/ .*//')
|
||||
# read out .rodata section as hex string (should be only 4 or 8 bytes)
|
||||
# read out .rodata section as hex string (should be only 4 bytes)
|
||||
ro=$(readelf -x $rosect /tmp/getoffs.o | grep '0x' | cut -c14-48 |
|
||||
tr -d ' \n')
|
||||
tr -d ' \n' | cut -c1-8)
|
||||
if [ "$ENDIAN" = "le" ]; then
|
||||
# swap needed for le target
|
||||
hex=""
|
||||
|
|
@ -41,16 +38,18 @@ get_define () # prefix struct member member...
|
|||
struct=$1; shift
|
||||
field=$(echo $* | sed 's/ /./g')
|
||||
name=$(echo $* | sed 's/ /_/g')
|
||||
echo '#include "pico/pico_int.h"' > /tmp/getoffs.c
|
||||
echo '#include <stdint.h>' > /tmp/getoffs.c
|
||||
echo '#include "pico/pico_int.h"' >> /tmp/getoffs.c
|
||||
echo "static const struct $struct p;" >> /tmp/getoffs.c
|
||||
echo "const int val = (char *)&p.$field - (char*)&p;" >>/tmp/getoffs.c
|
||||
echo "const int32_t val = (char *)&p.$field - (char*)&p;" >>/tmp/getoffs.c
|
||||
compile_rodata
|
||||
line=$(printf "#define %-20s 0x%04x" $prefix$name $rodata)
|
||||
}
|
||||
|
||||
if echo $CFLAGS | grep -qe -flto; then CFLAGS="$CFLAGS -fno-lto"; fi
|
||||
# determine endianess
|
||||
echo "const int val = 1;" >/tmp/getoffs.c
|
||||
echo '#include <stdint.h>' >/tmp/getoffs.c
|
||||
echo "const int32_t val = 1;" >>/tmp/getoffs.c
|
||||
compile_rodata
|
||||
ENDIAN=$(if [ "$rodata" -eq 1 ]; then echo be; else echo le; fi)
|
||||
# output header
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue