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Merge branch 'dev'

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This commit is contained in:
notaz 2013-08-31 21:10:56 +03:00
commit 9a1f192a14
89 changed files with 3226 additions and 4002 deletions
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149
pico/32x/32x.c
View file

@ -17,12 +17,12 @@ SH2 sh2s[2];
static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
{
if (sh2->pending_irl > sh2->pending_int_irq) {
elprintf(EL_32X, "%csh2 ack/irl %d @ %08x",
sh2->is_slave ? 's' : 'm', level, sh2->pc);
elprintf_sh2(sh2, EL_32X, "ack/irl %d @ %08x",
level, sh2_pc(sh2));
return 64 + sh2->pending_irl / 2;
} else {
elprintf(EL_32X, "%csh2 ack/int %d/%d @ %08x",
sh2->is_slave ? 's' : 'm', level, sh2->pending_int_vector, sh2->pc);
elprintf_sh2(sh2, EL_32X, "ack/int %d/%d @ %08x",
level, sh2->pending_int_vector, sh2_pc(sh2));
sh2->pending_int_irq = 0; // auto-clear
sh2->pending_level = sh2->pending_irl;
return sh2->pending_int_vector;
@ -39,13 +39,13 @@ void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
m68k_cycles = sh2_cycles_done_m68k(active_sh2);
// msh2
irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES);
irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[0];
while ((irqs >>= 1))
mlvl++;
mlvl *= 2;
// ssh2
irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES);
irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[1];
while ((irqs >>= 1))
slvl++;
slvl *= 2;
@ -67,6 +67,33 @@ void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
}
// the mask register is inconsistent, CMD is supposed to be a mask,
// while others are actually irq trigger enables?
// TODO: test on hw..
void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask)
{
Pico32x.sh2irqs |= mask & P32XI_VRES;
Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3);
Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3);
p32x_update_irls(sh2, m68k_cycles);
}
void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles)
{
if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1))
Pico32x.sh2irqi[0] |= P32XI_CMD;
else
Pico32x.sh2irqi[0] &= ~P32XI_CMD;
if ((Pico32x.sh2irq_mask[1] & 2) && (Pico32x.regs[2 / 2] & 2))
Pico32x.sh2irqi[1] |= P32XI_CMD;
else
Pico32x.sh2irqi[1] &= ~P32XI_CMD;
p32x_update_irls(sh2, m68k_cycles);
}
void Pico32xStartup(void)
{
elprintf(EL_STATUS|EL_32X, "32X startup");
@ -85,9 +112,6 @@ void Pico32xStartup(void)
if (!Pico.m.pal)
Pico32x.vdp_regs[0] |= P32XV_nPAL;
PREG8(msh2.peri_regs, 4) =
PREG8(ssh2.peri_regs, 4) = 0x84; // SCI SSR
rendstatus_old = -1;
emu_32x_startup();
@ -100,6 +124,8 @@ void p32x_reset_sh2s(void)
sh2_reset(&msh2);
sh2_reset(&ssh2);
sh2_peripheral_reset(&msh2);
sh2_peripheral_reset(&ssh2);
// if we don't have BIOS set, perform it's work here.
// MSH2
@ -140,7 +166,7 @@ void p32x_reset_sh2s(void)
// program will set S_OK
}
msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT();
msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone();
}
void Pico32xInit(void)
@ -156,7 +182,7 @@ void PicoPower32x(void)
memset(&Pico32x, 0, sizeof(Pico32x));
Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified
Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN;
Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_PEN;
Pico32x.sh2_regs[0] = P32XS2_ADEN;
}
@ -174,8 +200,8 @@ void PicoUnload32x(void)
void PicoReset32x(void)
{
if (PicoAHW & PAHW_32X) {
Pico32x.sh2irqs |= P32XI_VRES;
p32x_update_irls(NULL, SekCyclesDoneT2());
msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone();
p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VRES);
p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
p32x_pwm_ctl_changed();
@ -222,19 +248,29 @@ static void p32x_start_blank(void)
Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
}
Pico32x.sh2irqs |= P32XI_VINT;
p32x_update_irls(NULL, SekCyclesDoneT2());
p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VINT);
p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
}
// compare cycles, handling overflows
// check if a > b
#define CYCLES_GT(a, b) \
((int)((a) - (b)) > 0)
// check if a >= b
#define CYCLES_GE(a, b) \
((int)((a) - (b)) >= 0)
void p32x_schedule_hint(SH2 *sh2, int m68k_cycles)
{
// rather rough, 32x hint is useless in practice
int after;
if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 4))
return; // nobody cares
// note: when Pico.m.scanline is 224, SH2s might
// still be at scanline 93 (or so)
if (!(Pico32x.sh2_regs[0] & 0x80) && Pico.m.scanline > 224)
return;
after = (Pico32x.sh2_regs[4 / 2] + 1) * 488;
if (sh2 != NULL)
p32x_event_schedule_sh2(sh2, P32X_EVENT_HINT, after);
else
p32x_event_schedule(m68k_cycles, P32X_EVENT_HINT, after);
}
/* events */
static void fillend_event(unsigned int now)
@ -244,13 +280,21 @@ static void fillend_event(unsigned int now)
p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now);
}
static void hint_event(unsigned int now)
{
p32x_trigger_irq(NULL, now, P32XI_HINT);
p32x_schedule_hint(NULL, now);
}
typedef void (event_cb)(unsigned int now);
unsigned int event_times[P32X_EVENT_COUNT];
/* times are in m68k (7.6MHz) cycles */
unsigned int p32x_event_times[P32X_EVENT_COUNT];
static unsigned int event_time_next;
static event_cb *event_cbs[] = {
static event_cb *p32x_event_cbs[P32X_EVENT_COUNT] = {
[P32X_EVENT_PWM] = p32x_pwm_irq_event,
[P32X_EVENT_FILLEND] = fillend_event,
[P32X_EVENT_HINT] = hint_event,
};
// schedule event at some time 'after', in m68k clocks
@ -260,8 +304,8 @@ void p32x_event_schedule(unsigned int now, enum p32x_event event, int after)
when = (now + after) | 1;
elprintf(EL_32X, "new event #%u %u->%u", event, now, when);
event_times[event] = when;
elprintf(EL_32X, "32x: new event #%u %u->%u", event, now, when);
p32x_event_times[event] = when;
if (event_time_next == 0 || CYCLES_GT(event_time_next, when))
event_time_next = when;
@ -278,7 +322,7 @@ void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after)
sh2_end_run(sh2, left_to_next);
}
static void run_events(unsigned int until)
static void p32x_run_events(unsigned int until)
{
int oldest, oldest_diff, time;
int i, diff;
@ -287,8 +331,8 @@ static void run_events(unsigned int until)
oldest = -1, oldest_diff = 0x7fffffff;
for (i = 0; i < P32X_EVENT_COUNT; i++) {
if (event_times[i]) {
diff = event_times[i] - until;
if (p32x_event_times[i]) {
diff = p32x_event_times[i] - until;
if (diff < oldest_diff) {
oldest_diff = diff;
oldest = i;
@ -297,13 +341,13 @@ static void run_events(unsigned int until)
}
if (oldest_diff <= 0) {
time = event_times[oldest];
event_times[oldest] = 0;
elprintf(EL_32X, "run event #%d %u", oldest, time);
event_cbs[oldest](time);
time = p32x_event_times[oldest];
p32x_event_times[oldest] = 0;
elprintf(EL_32X, "32x: run event #%d %u", oldest, time);
p32x_event_cbs[oldest](time);
}
else if (oldest_diff < 0x7fffffff) {
event_time_next = event_times[oldest];
event_time_next = p32x_event_times[oldest];
break;
}
else {
@ -313,7 +357,8 @@ static void run_events(unsigned int until)
}
if (oldest != -1)
elprintf(EL_32X, "next event #%d at %u", oldest, event_time_next);
elprintf(EL_32X, "32x: next event #%d at %u",
oldest, event_time_next);
}
static inline void run_sh2(SH2 *sh2, int m68k_cycles)
@ -323,16 +368,16 @@ static inline void run_sh2(SH2 *sh2, int m68k_cycles)
pevt_log_sh2_o(sh2, EVT_RUN_START);
sh2->state |= SH2_STATE_RUN;
cycles = C_M68K_TO_SH2(*sh2, m68k_cycles);
elprintf(EL_32X, "%csh2 +run %u %d",
sh2->is_slave?'s':'m', sh2->m68krcycles_done, cycles);
elprintf_sh2(sh2, EL_32X, "+run %u %d @%08x",
sh2->m68krcycles_done, cycles, sh2->pc);
done = sh2_execute(sh2, cycles);
done = sh2_execute(sh2, cycles, PicoOpt & POPT_EN_DRC);
sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done);
sh2->state &= ~SH2_STATE_RUN;
pevt_log_sh2_o(sh2, EVT_RUN_END);
elprintf(EL_32X, "%csh2 -run %u %d",
sh2->is_slave?'s':'m', sh2->m68krcycles_done, done);
elprintf_sh2(sh2, EL_32X, "-run %u %d",
sh2->m68krcycles_done, done);
}
// sync other sh2 to this one
@ -355,8 +400,8 @@ void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
return;
}
elprintf(EL_32X, "%csh2 sync to %u %d",
osh2->is_slave?'s':'m', m68k_target, m68k_cycles);
elprintf_sh2(osh2, EL_32X, "sync to %u %d",
m68k_target, m68k_cycles);
run_sh2(osh2, m68k_cycles);
@ -396,7 +441,7 @@ void sync_sh2s_normal(unsigned int m68k_target)
while (CYCLES_GT(m68k_target, now))
{
if (event_time_next && CYCLES_GE(now, event_time_next))
run_events(now);
p32x_run_events(now);
target = m68k_target;
if (event_time_next && CYCLES_GT(target, event_time_next))
@ -470,10 +515,13 @@ void sync_sh2s_lockstep(unsigned int m68k_target)
}
}
#define CPUS_RUN(m68k_cycles,s68k_cycles) do { \
#define CPUS_RUN(m68k_cycles) do { \
SekRunM68k(m68k_cycles); \
if ((Pico32x.emu_flags & P32XF_Z80_32X_IO) && Pico.m.z80Run \
&& !Pico.m.z80_reset && (PicoOpt & POPT_EN_Z80)) \
PicoSyncZ80(SekCyclesDone()); \
if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \
p32x_sync_sh2s(SekCyclesDoneT2()); \
p32x_sync_sh2s(SekCyclesDone()); \
} while (0)
#define PICO_32X
@ -481,10 +529,14 @@ void sync_sh2s_lockstep(unsigned int m68k_target)
void PicoFrame32x(void)
{
Pico.m.scanline = 0;
Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
if (!(Pico32x.sh2_regs[0] & 0x80))
p32x_schedule_hint(NULL, SekCyclesDone());
p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
@ -519,11 +571,10 @@ void Pico32xStateLoaded(int is_early)
return;
}
SekCycleCnt = 0;
sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCycleCntT;
p32x_update_irls(NULL, SekCycleCntT);
sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCyclesDone();
p32x_update_irls(NULL, SekCyclesDone());
p32x_pwm_state_loaded();
run_events(SekCycleCntT);
p32x_run_events(SekCyclesDone());
}
// vim:shiftwidth=2:ts=2:expandtab

6
pico/32x/draw.c
View file

@ -43,7 +43,7 @@ static void convert_pal555(int invert_prio)
\
for (i = 320; i > 0; i--, pd++, p32x++, pmd++) { \
unsigned short t = *p32x; \
if (*pmd != mdbg && !((t ^ inv) & 0x8000)) { \
if ((*pmd & 0x3f) != mdbg && !((t ^ inv) & 0x8000)) { \
pmd_draw_code; \
continue; \
} \
@ -59,7 +59,7 @@ static void convert_pal555(int invert_prio)
int i; \
for (i = 320; i > 0; i--, pd++, p32x++, pmd++) { \
t = pal[*(unsigned char *)((long)p32x ^ 1)]; \
if ((t & 0x20) || *pmd == mdbg) \
if ((t & 0x20) || (*pmd & 0x3f) == mdbg) \
*pd = t; \
else \
pmd_draw_code; \
@ -74,7 +74,7 @@ static void convert_pal555(int invert_prio)
for (i = 320; i > 0; p32x++) { \
t = pal[*p32x & 0xff]; \
for (len = (*p32x >> 8) + 1; len > 0 && i > 0; len--, i--, pd++, pmd++) { \
if (*pmd == mdbg || (t & 0x20)) \
if ((*pmd & 0x3f) == mdbg || (t & 0x20)) \
*pd = t; \
else \
pmd_draw_code; \

19
pico/32x/draw_arm.s
View file

@ -77,6 +77,7 @@ Pico32xNativePal:
ldr r9, =HighPal @ palmd
and r4, r2, #0xff
mov r5, #328
lsl r3, #26 @ mdbg << 26
mla r11,r4,r5,r11 @ r11 = pmd = PicoDraw2FB + offs*328: md data
tst r10,#P32XV_PRI
moveq r10,#0
@ -107,7 +108,7 @@ Pico32xNativePal:
subs r6, r6, #1
blt 0b @ loop_outer
ldrh r8, [r5], #2 @ 32x pixel
cmp r7, r3 @ MD has bg pixel?
cmp r3, r7, lsl #26 @ MD has bg pixel?
beq 3f @ draw32x
eor r12,r8, r10
ands r12,r12,#0x8000 @ !((t ^ inv) & 0x8000)
@ -145,6 +146,7 @@ Pico32xNativePal:
ldr r9, =HighPal @ palmd
and r4, r2, #0xff
mov r5, #328
lsl r3, #26 @ mdbg << 26
mla r11,r4,r5,r11 @ r11 = pmd = PicoDraw2FB + offs*328: md data
call_scan_prep \call_scan
@ -191,14 +193,14 @@ Pico32xNativePal:
tst r12,#0x20
ldrneb r12,[r11,#-2] @ MD pixel 0
eor lr, r8, #0x20
cmpne r12,r3 @ MD has bg pixel?
cmpne r3, r12, lsl #26 @ MD has bg pixel?
.if \do_md
mov r12,r12,lsl #1
ldrneh r7, [r9, r12] @ t = palmd[pmd[0]]
tst lr, #0x20
ldrneb lr, [r11,#-1] @ MD pixel 1
strh r7, [r0], #2
cmpne lr, r3 @ MD has bg pixel?
cmpne r3, lr, lsl #26 @ MD has bg pixel?
mov lr, lr, lsl #1
ldrneh r8, [r9, lr] @ t = palmd[pmd[1]]
strh r8, [r0], #2
@ -207,7 +209,7 @@ Pico32xNativePal:
tst lr, #0x20
ldrneb lr, [r11,#-1] @ MD pixel 1
add r0, r0, #4
cmpne lr, r3 @ MD has bg pixel?
cmpne r3, lr, lsl #26 @ MD has bg pixel?
streqh r8, [r0, #-2]
.endif
b 2b @ loop_inner
@ -265,12 +267,12 @@ Pico32xNativePal:
9: @ bg_mode:
ldrb r12,[r11],#1 @ MD pixel
ldrb lr, [r11],#1
cmp r12,r3 @ MD has bg pixel?
cmp r3, lr, lsl #26 @ MD has bg pixel?
.if \do_md
mov r12,r12,lsl #1
ldrneh r12,[r9, r12] @ t = palmd[*pmd]
moveq r12,r7
cmp lr, r3
cmp r3, lr, lsl #26
mov lr, lr, lsl #1
ldrneh lr, [r9, lr]
moveq lr, r7
@ -278,7 +280,7 @@ Pico32xNativePal:
strh lr, [r0], #2
.else
streqh r7, [r0]
cmp lr, r3
cmp r3, lr, lsl #26
streqh r7, [r0, #2]
add r0, r0, #4
.endif
@ -302,6 +304,7 @@ Pico32xNativePal:
ldr r9, =HighPal @ palmd
and r4, r2, #0xff
mov r5, #328
lsl r3, #26 @ mdbg << 26
mla r11,r4,r5,r11 @ r11 = pmd = PicoDraw2FB + offs*328: md data
call_scan_prep \call_scan
@ -335,7 +338,7 @@ Pico32xNativePal:
ldrb r7, [r11], #1 @ MD pixel
subs r6, r6, #1
blt 0b @ loop_outer
cmp r7, r3 @ MD has bg pixel?
cmp r3, r7, lsl #26 @ MD has bg pixel?
mov r7, r7, lsl #1
tstne lr, #0x20
.if \do_md

601
pico/32x/memory.c
View file

File diff suppressed because it is too large Load diff

126
pico/32x/pwm.c
View file

@ -11,6 +11,8 @@ static int pwm_cycles;
static int pwm_mult;
static int pwm_ptr;
static int pwm_irq_reload;
static int pwm_doing_fifo;
static int pwm_silent;
void p32x_pwm_ctl_changed(void)
{
@ -19,7 +21,12 @@ void p32x_pwm_ctl_changed(void)
cycles = (cycles - 1) & 0x0fff;
pwm_cycles = cycles;
pwm_mult = 0x10000 / cycles;
// supposedly we should stop FIFO when xMd is 0,
// but mars test disagrees
pwm_mult = 0;
if ((control & 0x0f) != 0)
pwm_mult = 0x10000 / cycles;
pwm_irq_reload = (control & 0x0f00) >> 8;
pwm_irq_reload = ((pwm_irq_reload - 1) & 0x0f) + 1;
@ -30,8 +37,7 @@ void p32x_pwm_ctl_changed(void)
static void do_pwm_irq(SH2 *sh2, unsigned int m68k_cycles)
{
Pico32x.sh2irqs |= P32XI_PWM;
p32x_update_irls(sh2, m68k_cycles);
p32x_trigger_irq(sh2, m68k_cycles, P32XI_PWM);
if (Pico32x.regs[0x30 / 2] & P32XP_RTP) {
p32x_event_schedule(m68k_cycles, P32X_EVENT_PWM, pwm_cycles / 3 + 1);
@ -40,6 +46,15 @@ static void do_pwm_irq(SH2 *sh2, unsigned int m68k_cycles)
}
}
static int convert_sample(unsigned int v)
{
if (v == 0)
return 0;
if (v > pwm_cycles)
v = pwm_cycles;
return ((int)v - pwm_cycles / 2) * pwm_mult;
}
#define consume_fifo(sh2, m68k_cycles) { \
int cycles_diff = ((m68k_cycles) * 3) - Pico32x.pwm_cycle_p; \
if (cycles_diff >= pwm_cycles) \
@ -49,57 +64,53 @@ static void do_pwm_irq(SH2 *sh2, unsigned int m68k_cycles)
static void consume_fifo_do(SH2 *sh2, unsigned int m68k_cycles,
int sh2_cycles_diff)
{
int do_irq = 0;
struct Pico32xMem *mem = Pico32xMem;
unsigned short *fifo_l = mem->pwm_fifo[0];
unsigned short *fifo_r = mem->pwm_fifo[1];
int sum = 0;
if (pwm_cycles == 0)
if (pwm_cycles == 0 || pwm_doing_fifo)
return;
elprintf(EL_PWM, "pwm: %u: consume %d/%d, %d,%d ptr %d",
m68k_cycles, sh2_cycles_diff, sh2_cycles_diff / pwm_cycles,
Pico32x.pwm_p[0], Pico32x.pwm_p[1], pwm_ptr);
if (sh2_cycles_diff >= pwm_cycles * 17) {
// silence/skip
Pico32x.pwm_cycle_p = m68k_cycles * 3;
Pico32x.pwm_p[0] = Pico32x.pwm_p[1] = 0;
return;
}
while (sh2_cycles_diff >= pwm_cycles) {
struct Pico32xMem *mem = Pico32xMem;
short *fifo_l = mem->pwm_fifo[0];
short *fifo_r = mem->pwm_fifo[1];
// this is for recursion from dreq1 writes
pwm_doing_fifo = 1;
for (; sh2_cycles_diff >= pwm_cycles; sh2_cycles_diff -= pwm_cycles)
{
if (Pico32x.pwm_p[0] > 0) {
fifo_l[0] = fifo_l[1];
fifo_l[1] = fifo_l[2];
fifo_l[2] = fifo_l[3];
Pico32x.pwm_p[0]--;
mem->pwm_current[0] = convert_sample(fifo_l[0]);
sum += mem->pwm_current[0];
}
if (Pico32x.pwm_p[1] > 0) {
fifo_r[0] = fifo_r[1];
fifo_r[1] = fifo_r[2];
fifo_r[2] = fifo_r[3];
Pico32x.pwm_p[1]--;
mem->pwm_current[1] = convert_sample(fifo_r[0]);
sum += mem->pwm_current[1];
}
mem->pwm[pwm_ptr * 2 ] = fifo_l[0];
mem->pwm[pwm_ptr * 2 + 1] = fifo_r[0];
mem->pwm[pwm_ptr * 2 ] = mem->pwm_current[0];
mem->pwm[pwm_ptr * 2 + 1] = mem->pwm_current[1];
pwm_ptr = (pwm_ptr + 1) & (PWM_BUFF_LEN - 1);
sh2_cycles_diff -= pwm_cycles;
if (--Pico32x.pwm_irq_cnt == 0) {
Pico32x.pwm_irq_cnt = pwm_irq_reload;
// irq also does dreq1, so call it after cycle update
do_irq = 1;
break;
do_pwm_irq(sh2, m68k_cycles);
}
}
Pico32x.pwm_cycle_p = m68k_cycles * 3 - sh2_cycles_diff;
if (do_irq)
do_pwm_irq(sh2, m68k_cycles);
pwm_doing_fifo = 0;
if (sum != 0)
pwm_silent = 0;
}
static int p32x_pwm_schedule_(SH2 *sh2, unsigned int m68k_now)
@ -114,8 +125,6 @@ static int p32x_pwm_schedule_(SH2 *sh2, unsigned int m68k_now)
if (cycles_diff_sh2 >= pwm_cycles)
consume_fifo_do(sh2, m68k_now, cycles_diff_sh2);
if (Pico32x.sh2irqs & P32XI_PWM)
return 0; // previous not acked
if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 1))
return 0; // masked by everyone
@ -138,6 +147,12 @@ void p32x_pwm_schedule_sh2(SH2 *sh2)
p32x_event_schedule_sh2(sh2, P32X_EVENT_PWM, after);
}
void p32x_pwm_sync_to_sh2(SH2 *sh2)
{
int m68k_cycles = sh2_cycles_done_m68k(sh2);
consume_fifo(sh2, m68k_cycles);
}
void p32x_pwm_irq_event(unsigned int m68k_now)
{
p32x_pwm_schedule(m68k_now);
@ -188,8 +203,9 @@ void p32x_pwm_write16(unsigned int a, unsigned int d,
a &= 0x0e;
if (a == 0) { // control
// supposedly we should stop FIFO when xMd is 0,
// but mars test disagrees
// avoiding pops..
if ((Pico32x.regs[0x30 / 2] & 0x0f) == 0)
Pico32xMem->pwm_fifo[0][0] = Pico32xMem->pwm_fifo[1][0] = 0;
Pico32x.regs[0x30 / 2] = d;
p32x_pwm_ctl_changed();
Pico32x.pwm_irq_cnt = pwm_irq_reload; // ?
@ -200,12 +216,9 @@ void p32x_pwm_write16(unsigned int a, unsigned int d,
}
else if (a <= 8) {
d = (d - 1) & 0x0fff;
if (d > pwm_cycles)
d = pwm_cycles;
d = (d - pwm_cycles / 2) * pwm_mult;
if (a == 4 || a == 8) { // L ch or MONO
short *fifo = Pico32xMem->pwm_fifo[0];
unsigned short *fifo = Pico32xMem->pwm_fifo[0];
if (Pico32x.pwm_p[0] < 3)
Pico32x.pwm_p[0]++;
else {
@ -215,7 +228,7 @@ void p32x_pwm_write16(unsigned int a, unsigned int d,
fifo[Pico32x.pwm_p[0]] = d;
}
if (a == 6 || a == 8) { // R ch or MONO
short *fifo = Pico32xMem->pwm_fifo[1];
unsigned short *fifo = Pico32xMem->pwm_fifo[1];
if (Pico32x.pwm_p[1] < 3)
Pico32x.pwm_p[1]++;
else {
@ -234,16 +247,31 @@ void p32x_pwm_update(int *buf32, int length, int stereo)
int p = 0;
int xmd;
xmd = Pico32x.regs[0x30 / 2] & 0x0f;
if ((xmd != 0x05 && xmd != 0x0a) || pwm_ptr <= 16)
goto out;
consume_fifo(NULL, SekCyclesDone());
step = (pwm_ptr << 16) / length; // FIXME: division..
xmd = Pico32x.regs[0x30 / 2] & 0x0f;
if (xmd == 0 || xmd == 0x06 || xmd == 0x09 || xmd == 0x0f)
goto out; // invalid?
if (pwm_silent)
return;
step = (pwm_ptr << 16) / length;
pwmb = Pico32xMem->pwm;
if (stereo)
{
if (xmd == 0x0a) {
if (xmd == 0x05) {
// normal
while (length-- > 0) {
*buf32++ += pwmb[0];
*buf32++ += pwmb[1];
p += step;
pwmb += (p >> 16) * 2;
p &= 0xffff;
}
}
else if (xmd == 0x0a) {
// channel swap
while (length-- > 0) {
*buf32++ += pwmb[1];
@ -255,18 +283,24 @@ void p32x_pwm_update(int *buf32, int length, int stereo)
}
}
else {
// mono - LMD, RMD specify dst
if (xmd & 0x06) // src is R
pwmb++;
if (xmd & 0x0c) // dst is R
buf32++;
while (length-- > 0) {
*buf32++ += pwmb[0];
*buf32++ += pwmb[1];
*buf32 += *pwmb;
p += step;
pwmb += (p >> 16) * 2;
p &= 0xffff;
buf32 += 2;
}
}
}
else
{
// mostly unused
while (length-- > 0) {
*buf32++ += pwmb[0];
@ -281,6 +315,8 @@ void p32x_pwm_update(int *buf32, int length, int stereo)
out:
pwm_ptr = 0;
pwm_silent = Pico32xMem->pwm_current[0] == 0
&& Pico32xMem->pwm_current[1] == 0;
}
void p32x_pwm_state_loaded(void)
@ -290,11 +326,11 @@ void p32x_pwm_state_loaded(void)
p32x_pwm_ctl_changed();
// for old savestates
cycles_diff_sh2 = SekCycleCntT * 3 - Pico32x.pwm_cycle_p;
cycles_diff_sh2 = SekCycleCnt * 3 - Pico32x.pwm_cycle_p;
if (cycles_diff_sh2 >= pwm_cycles || cycles_diff_sh2 < 0) {
Pico32x.pwm_irq_cnt = pwm_irq_reload;
Pico32x.pwm_cycle_p = SekCycleCntT * 3;
p32x_pwm_schedule(SekCycleCntT);
Pico32x.pwm_cycle_p = SekCycleCnt * 3;
p32x_pwm_schedule(SekCycleCnt);
}
}

168
pico/32x/sh2soc.c
View file

@ -73,7 +73,7 @@ static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan)
{
chan->chcr |= DMA_TE; // DMA has ended normally
p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDoneT());
p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDone());
if (chan->chcr & DMA_IE)
dmac_te_irq(sh2, chan);
}
@ -128,7 +128,7 @@ static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan)
// DMA trigger by SH2 register write
static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
{
elprintf(EL_32XP, "sh2 DMA %08x->%08x, cnt %d, chcr %04x @%06x",
elprintf_sh2(sh2, EL_32XP, "DMA %08x->%08x, cnt %d, chcr %04x @%06x",
chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
chan->tcr &= 0xffffff;
@ -142,7 +142,7 @@ static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
// DREQ0 is only sent after first 4 words are written.
// we do multiple of 4 words to avoid messing up alignment
if (chan->sar == 0x20004012) {
if ((chan->sar & ~0x20000000) == 0x00004012) {
if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) {
elprintf(EL_32XP, "68k -> sh2 DMA");
p32x_dreq0_trigger();
@ -150,6 +150,10 @@ static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
return;
}
// DREQ1
if ((chan->dar & 0xc7fffff0) == 0x00004030)
return;
elprintf(EL_32XP|EL_ANOMALY, "unhandled DMA: "
"%08x->%08x, cnt %d, chcr %04x @%06x",
chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
@ -207,6 +211,16 @@ void p32x_timers_do(unsigned int m68k_slice)
}
}
void sh2_peripheral_reset(SH2 *sh2)
{
memset(sh2->peri_regs, 0, sizeof(sh2->peri_regs)); // ?
PREG8(sh2->peri_regs, 0x001) = 0xff; // SCI BRR
PREG8(sh2->peri_regs, 0x003) = 0xff; // SCI TDR
PREG8(sh2->peri_regs, 0x004) = 0x84; // SCI SSR
PREG8(sh2->peri_regs, 0x011) = 0x01; // TIER
PREG8(sh2->peri_regs, 0x017) = 0xe0; // TOCR
}
// ------------------------------------------------------------------
// SH2 internal peripheral memhandlers
// we keep them in little endian format
@ -219,8 +233,8 @@ u32 sh2_peripheral_read8(u32 a, SH2 *sh2)
a &= 0x1ff;
d = PREG8(r, a);
elprintf(EL_32XP, "%csh2 peri r8 [%08x] %02x @%06x",
sh2->is_slave ? 's' : 'm', a | ~0x1ff, d, sh2_pc(sh2));
elprintf_sh2(sh2, EL_32XP, "peri r8 [%08x] %02x @%06x",
a | ~0x1ff, d, sh2_pc(sh2));
return d;
}
@ -232,8 +246,8 @@ u32 sh2_peripheral_read16(u32 a, SH2 *sh2)
a &= 0x1ff;
d = r[(a / 2) ^ 1];
elprintf(EL_32XP, "%csh2 peri r16 [%08x] %04x @%06x",
sh2->is_slave ? 's' : 'm', a | ~0x1ff, d, sh2_pc(sh2));
elprintf_sh2(sh2, EL_32XP, "peri r16 [%08x] %04x @%06x",
a | ~0x1ff, d, sh2_pc(sh2));
return d;
}
@ -243,40 +257,90 @@ u32 sh2_peripheral_read32(u32 a, SH2 *sh2)
a &= 0x1fc;
d = sh2->peri_regs[a / 4];
elprintf(EL_32XP, "%csh2 peri r32 [%08x] %08x @%06x",
sh2->is_slave ? 's' : 'm', a | ~0x1ff, d, sh2_pc(sh2));
elprintf_sh2(sh2, EL_32XP, "peri r32 [%08x] %08x @%06x",
a | ~0x1ff, d, sh2_pc(sh2));
return d;
}
static void sci_trigger(SH2 *sh2, u8 *r)
{
u8 *oregs;
if (!(PREG8(r, 2) & 0x20))
return; // transmitter not enabled
if ((PREG8(r, 4) & 0x80)) // TDRE - TransmitDataR Empty
return;
oregs = (u8 *)sh2->other_sh2->peri_regs;
if (!(PREG8(oregs, 2) & 0x10))
return; // receiver not enabled
PREG8(oregs, 5) = PREG8(r, 3); // other.RDR = this.TDR
PREG8(r, 4) |= 0x80; // TDRE - TDR empty
PREG8(oregs, 4) |= 0x40; // RDRF - RDR Full
// might need to delay these a bit..
if (PREG8(r, 2) & 0x80) { // TIE - tx irq enabled
int level = PREG8(oregs, 0x60) >> 4;
int vector = PREG8(oregs, 0x64) & 0x7f;
elprintf_sh2(sh2, EL_32XP, "SCI tx irq (%d, %d)",
level, vector);
sh2_internal_irq(sh2, level, vector);
}
// TODO: TEIE
if (PREG8(oregs, 2) & 0x40) { // RIE - rx irq enabled
int level = PREG8(oregs, 0x60) >> 4;
int vector = PREG8(oregs, 0x63) & 0x7f;
elprintf_sh2(sh2->other_sh2, EL_32XP, "SCI rx irq (%d, %d)",
level, vector);
sh2_internal_irq(sh2->other_sh2, level, vector);
}
}
void REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, SH2 *sh2)
{
u8 *r = (void *)sh2->peri_regs;
elprintf(EL_32XP, "%csh2 peri w8 [%08x] %02x @%06x",
sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
u8 old;
elprintf_sh2(sh2, EL_32XP, "peri w8 [%08x] %02x @%06x",
a, d, sh2_pc(sh2));
a &= 0x1ff;
PREG8(r, a) = d;
old = PREG8(r, a);
// X-men SCI hack
if ((a == 2 && (d & 0x20)) || // transmiter enabled
(a == 4 && !(d & 0x80))) { // valid data in TDR
void *oregs = sh2->other_sh2->peri_regs;
if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
int level = PREG8(oregs, 0x60) >> 4;
int vector = PREG8(oregs, 0x63) & 0x7f;
elprintf(EL_32XP, "%csh2 SCI recv irq (%d, %d)",
(sh2->is_slave ^ 1) ? 's' : 'm', level, vector);
sh2_internal_irq(sh2->other_sh2, level, vector);
return;
switch (a) {
case 0x002: // SCR - serial control
if (!(PREG8(r, a) & 0x20) && (d & 0x20)) { // TE being set
PREG8(r, a) = d;
sci_trigger(sh2, r);
}
break;
case 0x003: // TDR - transmit data
break;
case 0x004: // SSR - serial status
d = (old & (d | 0x06)) | (d & 1);
PREG8(r, a) = d;
sci_trigger(sh2, r);
return;
case 0x005: // RDR - receive data
break;
case 0x010: // TIER
if (d & 0x8e)
elprintf(EL_32XP|EL_ANOMALY, "TIER: %02x", d);
d = (d & 0x8e) | 1;
break;
case 0x017: // TOCR
d |= 0xe0;
break;
}
PREG8(r, a) = d;
}
void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
{
u16 *r = (void *)sh2->peri_regs;
elprintf(EL_32XP, "%csh2 peri w16 [%08x] %04x @%06x",
sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
elprintf_sh2(sh2, EL_32XP, "peri w16 [%08x] %04x @%06x",
a, d, sh2_pc(sh2));
a &= 0x1ff;
@ -297,17 +361,20 @@ void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
{
u32 *r = sh2->peri_regs;
elprintf(EL_32XP, "%csh2 peri w32 [%08x] %08x @%06x",
sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
u32 old;
elprintf_sh2(sh2, EL_32XP, "peri w32 [%08x] %08x @%06x",
a, d, sh2_pc(sh2));
a &= 0x1fc;
old = r[a / 4];
r[a / 4] = d;
switch (a) {
// division unit (TODO: verify):
case 0x104: // DVDNT: divident L, starts divide
elprintf(EL_32XP, "%csh2 divide %08x / %08x",
sh2->is_slave ? 's' : 'm', d, r[0x100 / 4]);
elprintf_sh2(sh2, EL_32XP, "divide %08x / %08x",
d, r[0x100 / 4]);
if (r[0x100 / 4]) {
signed int divisor = r[0x100 / 4];
r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
@ -317,8 +384,8 @@ void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
break;
case 0x114:
elprintf(EL_32XP, "%csh2 divide %08x%08x / %08x @%08x",
sh2->is_slave ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(sh2));
elprintf_sh2(sh2, EL_32XP, "divide %08x%08x / %08x @%08x",
r[0x110 / 4], d, r[0x100 / 4], sh2_pc(sh2));
if (r[0x100 / 4]) {
signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
signed int divisor = r[0x100 / 4];
@ -328,8 +395,7 @@ void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
r[0x11c / 4] = r[0x114 / 4] = divident;
divident >>= 31;
if ((unsigned long long)divident + 1 > 1) {
//elprintf(EL_32XP, "%csh2 divide overflow! @%08x",
// sh2->is_slave ? 's' : 'm', sh2_pc(sh2));
//elprintf_sh2(sh2, EL_32XP, "divide overflow! @%08x", sh2_pc(sh2));
r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
}
}
@ -341,6 +407,8 @@ void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
// perhaps starting a DMA?
if (a == 0x1b0 || a == 0x18c || a == 0x19c) {
struct dmac *dmac = (void *)&sh2->peri_regs[0x180 / 4];
if (a == 0x1b0 && !((old ^ d) & d & DMA_DME))
return;
if (!(dmac->dmaor & DMA_DME))
return;
@ -354,29 +422,28 @@ void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
/* 32X specific */
static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
{
unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
unsigned short dreqlen = Pico32x.regs[0x10 / 2];
int i;
// debug/sanity checks
if (chan->tcr != *dreqlen)
elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0 and len differ: %d != %d",
chan->tcr, *dreqlen);
if (chan->tcr < dreqlen || chan->tcr > dreqlen + 4)
elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0/len inconsistent: %d/%d",
chan->tcr, dreqlen);
// note: DACK is not connected, single addr mode should not be used
if ((chan->chcr & 0x3f08) != 0x0400)
elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr);
if (chan->sar != 0x20004012)
elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad sar?: %08x\n", chan->sar);
if ((chan->sar & ~0x20000000) != 0x00004012)
elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad sar?: %08x", chan->sar);
// HACK: assume bus is busy and SH2 is halted
sh2->state |= SH2_STATE_SLEEP;
for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) {
elprintf(EL_32XP, "dmaw [%08x] %04x, left %d",
chan->dar, Pico32x.dmac_fifo[i], *dreqlen);
elprintf_sh2(sh2, EL_32XP, "dreq0 [%08x] %04x, dreq_len %d",
chan->dar, Pico32x.dmac_fifo[i], dreqlen);
p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2);
chan->dar += 2;
chan->tcr--;
(*dreqlen)--;
}
if (Pico32x.dmac0_fifo_ptr != i)
@ -385,8 +452,6 @@ static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
Pico32x.dmac0_fifo_ptr -= i;
Pico32x.regs[6 / 2] &= ~P32XS_FULL;
if (*dreqlen == 0)
Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
if (chan->tcr == 0)
dmac_transfer_complete(sh2, chan);
else
@ -436,8 +501,19 @@ void p32x_dreq1_trigger(void)
hit = 1;
}
if (!hit)
elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared");
// debug
#if (EL_LOGMASK & (EL_32XP|EL_ANOMALY))
{
static int miss_count;
if (!hit) {
if (++miss_count == 4)
elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared");
}
else
miss_count = 0;
}
#endif
(void)hit;
}
// vim:shiftwidth=2:ts=2:expandtab

5
pico/cart.c
View file

@ -643,6 +643,8 @@ static int rom_strcmp(int rom_offset, const char *s1)
{
int i, len = strlen(s1);
const char *s_rom = (const char *)Pico.rom;
if (rom_offset + len > Pico.romsize)
return 0;
for (i = 0; i < len; i++)
if (s1[i] != s_rom[(i + rom_offset) ^ 1])
return 1;
@ -897,10 +899,13 @@ static void parse_carthw(const char *carthw_cfg, int *fill_sram)
SRam.flags &= ~SRF_EEPROM;
else if (strcmp(p, "filled_sram") == 0)
*fill_sram = 1;
else if (strcmp(p, "force_6btn") == 0)
PicoQuirks |= PQUIRK_FORCE_6BTN;
else {
elprintf(EL_STATUS, "carthw:%d: unsupported prop: %s", line, p);
goto bad_nomsg;
}
elprintf(EL_STATUS, "game prop: %s", p);
continue;
}
else if (is_expr("eeprom_type", &p)) {

15
pico/carthw.cfg
View file

@ -8,6 +8,7 @@
# no_sram - don't emulate sram/EEPROM even if ROM headers tell it's there
# no_eeprom - save storage is not EEPROM, even if ROM headers tell it is
# filled_sram - save storage needs to be initialized with FFh instead of 00h
# force_6btn - game only supports 6 button pad (32X X-men proto)
#
# mappers (hw = ...):
# ssf2_mapper - used in Super Street Fighter2
@ -32,10 +33,12 @@
[Virtua Racing - SVP]
check_str = 0x150, "Virtua Racing"
check_str = 0x810, "OHMP"
hw = svp
[Virtua Racing - SVP]
check_str = 0x150, "VIRTUA RACING"
check_str = 0x810, "OHMP"
hw = svp
[Pico]
@ -60,6 +63,12 @@ prop = filled_sram
check_str = 0x150, "MICRO MACHINES II"
prop = filled_sram
# X-Men proto
[X-Men (prototype)]
check_str = 0x150, "32X SAMPLE PROGRAM"
check_str = 0x32b74c, "Bishop Level"
prop = force_6btn
# The SSF2 mapper
[Super Street Fighter II - The New Challengers (U)]
check_str = 0x150, "SUPER STREET FIGHTER2 The New Challengers"
@ -68,11 +77,9 @@ prop = no_sram
# The Pier Solar mapper, custom eeprom location
[Pier Solar and the Great Architects]
check_str = 0x150, "PIER SOLAR™&THE GREAT ARCHITECTS© WaterMelon™"
check_str = 0x150, "PIER"
check_str = 0x610, "Respect"
hw = piersolar_mapper
sram_range = 0xa13009,0xa1300b
eeprom_type = 3
eeprom_lines = 2,1,0
# detect *_in_1 based on first game and if it's larger than it should be,
# as some dumps look like to be incomplete.

12
pico/carthw_cfg.c
View file

@ -2,9 +2,11 @@
static const char builtin_carthw_cfg[] =
"[]\n"
"check_str=0x150,\"Virtua Racing\"\n"
"check_str=0x810,\"OHMP\"\n"
"hw=svp\n"
"[]\n"
"check_str=0x150,\"VIRTUA RACING\"\n"
"check_str=0x810,\"OHMP\"\n"
"hw=svp\n"
"[]\n"
"check_str=0x100,\"SEGA PICO\"\n"
@ -22,15 +24,17 @@ static const char builtin_carthw_cfg[] =
"check_str=0x150,\"MICRO MACHINES II\"\n"
"prop=filled_sram\n"
"[]\n"
"check_str=0x150,\"32X SAMPLE PROGRAM\"\n"
"check_str=0x32b74c,\"Bishop Level\"\n"
"prop=force_6btn\n"
"[]\n"
"check_str=0x150,\"SUPER STREET FIGHTER2 The New Challengers\"\n"
"hw=ssf2_mapper\n"
"prop=no_sram\n"
"[]\n"
"check_str=0x150,\"PIER SOLAR\x99&THE GREAT ARCHITECTS\xa9 WaterMelon\x99\"\n"
"check_str=0x150,\"PIER\"\n"
"check_str=0x610,\"Respect\"\n"
"hw=piersolar_mapper\n"
"sram_range=0xa13009,0xa1300b\n"
"eeprom_type=3\n"
"eeprom_lines=2,1,0\n"
"[]\n"
"check_str=0x120,\"FLICKY\"\n"
"check_size_gt=0x020000\n"

19
pico/cd/LC89510.c
View file

@ -68,7 +68,7 @@ PICO_INTERNAL void Update_CDC_TRansfer(int which)
unsigned short *dest;
unsigned char *src;
if (Pico_mcd->cdc.DBC.N <= (CDC_DMA_SPEED * 2))
if (1) //Pico_mcd->cdc.DBC.N <= (CDC_DMA_SPEED * 2))
{
length = (Pico_mcd->cdc.DBC.N + 1) >> 1;
Pico_mcd->scd.Status_CDC &= ~0x08; // Last transfer
@ -80,7 +80,7 @@ PICO_INTERNAL void Update_CDC_TRansfer(int which)
{
Pico_mcd->cdc.IFSTAT &= ~0x40;
if (Pico_mcd->s68k_regs[0x33] & (1<<5))
if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN5)
{
elprintf(EL_INTS, "cdc DTE irq 5");
SekInterruptS68k(5);
@ -430,6 +430,19 @@ PICO_INTERNAL void CDC_Write_Reg(unsigned char Data)
cdprintf("************** Starting Data Transfer ***********");
cdprintf("RS0 = %.4X DAC = %.4X DBC = %.4X DMA adr = %.4X\n\n", Pico_mcd->s68k_regs[4]<<8,
Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N, (Pico_mcd->s68k_regs[0xA]<<8) | Pico_mcd->s68k_regs[0xB]);
// tmp
{
int ddx = Pico_mcd->s68k_regs[4] & 7;
if (ddx < 2) break; // invalid
if (ddx < 4) {
Pico_mcd->s68k_regs[4] |= 0x40; // Data set ready in host port
break;
}
if (ddx == 6) break; // invalid
pcd_event_schedule_s68k(PCD_EVENT_DMA, Pico_mcd->cdc.DBC.N / 2);
}
}
break;
@ -504,7 +517,7 @@ PICO_INTERNAL void CDD_Export_Status(void)
Pico_mcd->s68k_regs[0x37] &= 3; // CDD.Control
if (Pico_mcd->s68k_regs[0x33] & (1<<4))
if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN4)
{
elprintf(EL_INTS, "cdd export irq 4");
SekInterruptS68k(4);

4
pico/cd/cd_sys.c
View file

@ -471,6 +471,10 @@ PICO_INTERNAL int Play_CDD_c3(void)
if (delay < 0) delay = -delay;
delay >>= 12;
// based on genplys GX
if (delay < 13)
delay = 13;
Pico_mcd->scd.Cur_LBA = new_lba;
CDC_Update_Header();

172
pico/cd/gfx_cd.c
View file

@ -12,33 +12,21 @@
#define _rot_comp Pico_mcd->rot_comp
static const int Table_Rot_Time[] =
{
0x00054000, 0x00048000, 0x00040000, 0x00036000, //; 008-032 ; briefing - sprite
0x0002E000, 0x00028000, 0x00024000, 0x00022000, //; 036-064 ; arbre souvent
0x00021000, 0x00020000, 0x0001E000, 0x0001B800, //; 068-096 ; map thunderstrike
0x00019800, 0x00017A00, 0x00015C00, 0x00013E00, //; 100-128 ; logo défoncé
0x00012000, 0x00011800, 0x00011000, 0x00010800, //; 132-160 ; briefing - map
0x00010000, 0x0000F800, 0x0000F000, 0x0000E800, //; 164-192
0x0000E000, 0x0000D800, 0x0000D000, 0x0000C800, //; 196-224
0x0000C000, 0x0000B800, 0x0000B000, 0x0000A800, //; 228-256 ; batman visage
0x0000A000, 0x00009F00, 0x00009E00, 0x00009D00, //; 260-288
0x00009C00, 0x00009B00, 0x00009A00, 0x00009900, //; 292-320
0x00009800, 0x00009700, 0x00009600, 0x00009500, //; 324-352
0x00009400, 0x00009300, 0x00009200, 0x00009100, //; 356-384
0x00009000, 0x00008F00, 0x00008E00, 0x00008D00, //; 388-416
0x00008C00, 0x00008B00, 0x00008A00, 0x00008900, //; 420-448
0x00008800, 0x00008700, 0x00008600, 0x00008500, //; 452-476
0x00008400, 0x00008300, 0x00008200, 0x00008100, //; 480-512
};
static void gfx_do_line(unsigned int func, unsigned short *stamp_base,
unsigned int H_Dot);
static void gfx_cd_start(void)
{
int upd_len;
int w, h;
w = _rot_comp.Reg_62;
h = _rot_comp.Reg_64;
if (w == 0 || h == 0) {
elprintf(EL_CD|EL_ANOMALY, "gfx_cd_start with %ux%u", w, h);
_rot_comp.Reg_64 = 0;
// irq?
return;
}
// _rot_comp.XD_Mul = ((_rot_comp.Reg_5C & 0x1f) + 1) * 4; // unused
_rot_comp.Function = (_rot_comp.Reg_58 & 7) | (Pico_mcd->s68k_regs[3] & 0x18); // Jmp_Adr
@ -46,12 +34,10 @@ static void gfx_cd_start(void)
_rot_comp.YD = (_rot_comp.Reg_60 >> 3) & 7;
_rot_comp.Vector_Adr = (_rot_comp.Reg_66 & 0xfffe) << 2;
upd_len = (_rot_comp.Reg_62 >> 3) & 0x3f;
upd_len = Table_Rot_Time[upd_len];
_rot_comp.Draw_Speed = _rot_comp.Float_Part = upd_len;
_rot_comp.Reg_58 |= 0x8000; // Stamp_Size, we start a new GFX operation
pcd_event_schedule_s68k(PCD_EVENT_GFX, 5 * w * h);
switch (_rot_comp.Reg_58 & 6) // Scr_16?
{
case 0: // ?
@ -68,25 +54,46 @@ static void gfx_cd_start(void)
break;
}
dprintf("gfx_cd_start, stamp_map_addr=%06x", _rot_comp.Stamp_Map_Adr);
gfx_cd_update();
}
static void gfx_completed(void)
{
_rot_comp.Reg_58 &= 0x7fff; // Stamp_Size
_rot_comp.Reg_64 = 0;
if (Pico_mcd->s68k_regs[0x33] & (1<<1))
if (PicoOpt & POPT_EN_MCD_GFX)
{
elprintf(EL_INTS, "gfx_cd irq 1");
SekInterruptS68k(1);
unsigned int func = _rot_comp.Function;
unsigned short *stamp_base = (unsigned short *) (Pico_mcd->word_ram2M + _rot_comp.Stamp_Map_Adr);
while (h--)
gfx_do_line(func, stamp_base, w);
}
}
static void gfx_do(unsigned int func, unsigned short *stamp_base, unsigned int H_Dot)
PICO_INTERNAL_ASM unsigned int gfx_cd_read(unsigned int a)
{
unsigned int d = 0;
switch (a) {
case 0x58: d = _rot_comp.Reg_58; break;
case 0x5A: d = _rot_comp.Reg_5A; break;
case 0x5C: d = _rot_comp.Reg_5C; break;
case 0x5E: d = _rot_comp.Reg_5E; break;
case 0x60: d = _rot_comp.Reg_60; break;
case 0x62: d = _rot_comp.Reg_62; break;
case 0x64:
d = _rot_comp.Reg_64;
if (_rot_comp.Reg_64 > 1)
// fudge..
_rot_comp.Reg_64--;
break;
case 0x66: break;
default: dprintf("gfx_cd_read FIXME: unexpected address: %02x", a); break;
}
dprintf("gfx_cd_read(%02x) = %04x", a, d);
return d;
}
static void gfx_do_line(unsigned int func, unsigned short *stamp_base,
unsigned int H_Dot)
{
unsigned int eax, ebx, ecx, edx, esi, edi, pixel;
unsigned int XD, Buffer_Adr;
@ -291,88 +298,13 @@ Next_Pixel:
}
PICO_INTERNAL void gfx_cd_update(void)
{
int V_Dot = _rot_comp.Reg_64 & 0xff;
int jobs;
dprintf("gfx_cd_update, Reg_64 = %04x", _rot_comp.Reg_64);
if (!V_Dot)
{
gfx_completed();
return;
}
jobs = _rot_comp.Float_Part >> 16;
if (!jobs)
{
_rot_comp.Float_Part += _rot_comp.Draw_Speed;
return;
}
_rot_comp.Float_Part &= 0xffff;
_rot_comp.Float_Part += _rot_comp.Draw_Speed;
if (PicoOpt & POPT_EN_MCD_GFX)
{
unsigned int func = _rot_comp.Function;
unsigned int H_Dot = _rot_comp.Reg_62 & 0x1ff;
unsigned short *stamp_base = (unsigned short *) (Pico_mcd->word_ram2M + _rot_comp.Stamp_Map_Adr);
while (jobs--)
{
gfx_do(func, stamp_base, H_Dot); // jmp [Jmp_Adr]:
V_Dot--; // dec byte [V_Dot]
if (V_Dot == 0)
{
// GFX_Completed:
gfx_completed();
return;
}
}
}
else
{
if (jobs >= V_Dot)
{
gfx_completed();
return;
}
V_Dot -= jobs;
}
_rot_comp.Reg_64 = V_Dot;
}
PICO_INTERNAL_ASM unsigned int gfx_cd_read(unsigned int a)
{
unsigned int d = 0;
switch (a) {
case 0x58: d = _rot_comp.Reg_58; break;
case 0x5A: d = _rot_comp.Reg_5A; break;
case 0x5C: d = _rot_comp.Reg_5C; break;
case 0x5E: d = _rot_comp.Reg_5E; break;
case 0x60: d = _rot_comp.Reg_60; break;
case 0x62: d = _rot_comp.Reg_62; break;
case 0x64: d = _rot_comp.Reg_64; break;
case 0x66: break;
default: dprintf("gfx_cd_read FIXME: unexpected address: %02x", a); break;
}
dprintf("gfx_cd_read(%02x) = %04x", a, d);
return d;
}
PICO_INTERNAL_ASM void gfx_cd_write16(unsigned int a, unsigned int d)
{
dprintf("gfx_cd_write16(%x, %04x)", a, d);
if (_rot_comp.Reg_58 & 0x8000)
elprintf(EL_CD|EL_ANOMALY, "cd: busy gfx reg write %02x %04x", a, d);
switch (a) {
case 0x58: // .Reg_Stamp_Size
_rot_comp.Reg_58 = d & 7;

2
pico/cd/gfx_cd.h
View file

@ -24,8 +24,6 @@ typedef struct
} Rot_Comp;
PICO_INTERNAL void gfx_cd_update(void);
PICO_INTERNAL_ASM unsigned int gfx_cd_read(unsigned int a);
PICO_INTERNAL_ASM void gfx_cd_write16(unsigned int a, unsigned int d);

344
pico/cd/mcd.c Normal file
View file

@ -0,0 +1,344 @@
/*
* PicoDrive
* (C) notaz, 2007,2013
*
* This work is licensed under the terms of MAME license.
* See COPYING file in the top-level directory.
*/
#include "../pico_int.h"
#include "../sound/ym2612.h"
extern unsigned char formatted_bram[4*0x10];
static unsigned int m68k_cycle_mult;
void (*PicoMCDopenTray)(void) = NULL;
void (*PicoMCDcloseTray)(void) = NULL;
PICO_INTERNAL void PicoInitMCD(void)
{
SekInitS68k();
Init_CD_Driver();
}
PICO_INTERNAL void PicoExitMCD(void)
{
End_CD_Driver();
}
PICO_INTERNAL void PicoPowerMCD(void)
{
int fmt_size = sizeof(formatted_bram);
memset(Pico_mcd->prg_ram, 0, sizeof(Pico_mcd->prg_ram));
memset(Pico_mcd->word_ram2M, 0, sizeof(Pico_mcd->word_ram2M));
memset(Pico_mcd->pcm_ram, 0, sizeof(Pico_mcd->pcm_ram));
memset(Pico_mcd->bram, 0, sizeof(Pico_mcd->bram));
memcpy(Pico_mcd->bram + sizeof(Pico_mcd->bram) - fmt_size,
formatted_bram, fmt_size);
memset(Pico_mcd->s68k_regs, 0, sizeof(Pico_mcd->s68k_regs));
memset(&Pico_mcd->pcm, 0, sizeof(Pico_mcd->pcm));
memset(&Pico_mcd->m, 0, sizeof(Pico_mcd->m));
// cold reset state (tested)
Pico_mcd->m.state_flags = PCD_ST_S68K_RST;
Pico_mcd->m.busreq = 2; // busreq on, s68k in reset
Pico_mcd->s68k_regs[3] = 1; // 2M word RAM mode, m68k access
Pico_mcd->s68k_regs[6] = 0xff;
Pico_mcd->s68k_regs[7] = 0xff;
memset(Pico_mcd->bios + 0x70, 0xff, 4);
}
PICO_INTERNAL int PicoResetMCD(void)
{
// ??
Reset_CD();
LC89510_Reset();
gfx_cd_reset();
#ifdef _ASM_CD_MEMORY_C
//PicoMemResetCDdecode(1); // don't have to call this in 2M mode
#endif
// use SRam.data for RAM cart
if (PicoOpt & POPT_EN_MCD_RAMCART) {
if (SRam.data == NULL)
SRam.data = calloc(1, 0x12000);
}
else if (SRam.data != NULL) {
free(SRam.data);
SRam.data = NULL;
}
SRam.start = SRam.end = 0; // unused
pcd_event_schedule(0, PCD_EVENT_CDC, 12500000/75);
return 0;
}
static __inline void SekRunS68k(unsigned int to)
{
int cyc_do;
SekCycleAimS68k = to;
if ((cyc_do = SekCycleAimS68k - SekCycleCntS68k) <= 0)
return;
SekCycleCntS68k += cyc_do;
#if defined(EMU_C68K)
PicoCpuCS68k.cycles = cyc_do;
CycloneRun(&PicoCpuCS68k);
SekCycleCntS68k -= PicoCpuCS68k.cycles;
#elif defined(EMU_M68K)
m68k_set_context(&PicoCpuMS68k);
SekCycleCntS68k += m68k_execute(cyc_do) - cyc_do;
m68k_set_context(&PicoCpuMM68k);
#elif defined(EMU_F68K)
g_m68kcontext = &PicoCpuFS68k;
SekCycleCntS68k += fm68k_emulate(cyc_do, 0, 0) - cyc_do;
g_m68kcontext = &PicoCpuFM68k;
#endif
}
unsigned int pcd_cycles_m68k_to_s68k(unsigned int c)
{
return (long long)c * m68k_cycle_mult >> 16;
}
/* events */
static void pcd_cdc_event(unsigned int now)
{
// 75Hz CDC update
Check_CD_Command();
pcd_event_schedule(now, PCD_EVENT_CDC, 12500000/75);
}
static void pcd_int3_timer_event(unsigned int now)
{
if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN3) {
elprintf(EL_INTS|EL_CD, "s68k: timer irq 3");
SekInterruptS68k(3);
}
if (Pico_mcd->s68k_regs[0x31] != 0)
pcd_event_schedule(now, PCD_EVENT_TIMER3,
Pico_mcd->s68k_regs[0x31] * 384);
}
static void pcd_gfx_event(unsigned int now)
{
// update gfx chip
if (Pico_mcd->rot_comp.Reg_58 & 0x8000) {
Pico_mcd->rot_comp.Reg_58 &= 0x7fff;
Pico_mcd->rot_comp.Reg_64 = 0;
if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN1) {
elprintf(EL_INTS |EL_CD, "s68k: gfx_cd irq 1");
SekInterruptS68k(1);
}
}
}
static void pcd_dma_event(unsigned int now)
{
int ddx = Pico_mcd->s68k_regs[4] & 7;
Update_CDC_TRansfer(ddx);
}
typedef void (event_cb)(unsigned int now);
/* times are in s68k (12.5MHz) cycles */
unsigned int pcd_event_times[PCD_EVENT_COUNT];
static unsigned int event_time_next;
static event_cb *pcd_event_cbs[PCD_EVENT_COUNT] = {
[PCD_EVENT_CDC] = pcd_cdc_event,
[PCD_EVENT_TIMER3] = pcd_int3_timer_event,
[PCD_EVENT_GFX] = pcd_gfx_event,
[PCD_EVENT_DMA] = pcd_dma_event,
};
void pcd_event_schedule(unsigned int now, enum pcd_event event, int after)
{
unsigned int when;
when = now + after;
if (when == 0) {
// event cancelled
pcd_event_times[event] = 0;
return;
}
when |= 1;
elprintf(EL_CD, "cd: new event #%u %u->%u", event, now, when);
pcd_event_times[event] = when;
if (event_time_next == 0 || CYCLES_GT(event_time_next, when))
event_time_next = when;
}
void pcd_event_schedule_s68k(enum pcd_event event, int after)
{
if (SekCyclesLeftS68k > after)
SekEndRunS68k(after);
pcd_event_schedule(SekCyclesDoneS68k(), event, after);
}
static void pcd_run_events(unsigned int until)
{
int oldest, oldest_diff, time;
int i, diff;
while (1) {
oldest = -1, oldest_diff = 0x7fffffff;
for (i = 0; i < PCD_EVENT_COUNT; i++) {
if (pcd_event_times[i]) {
diff = pcd_event_times[i] - until;
if (diff < oldest_diff) {
oldest_diff = diff;
oldest = i;
}
}
}
if (oldest_diff <= 0) {
time = pcd_event_times[oldest];
pcd_event_times[oldest] = 0;
elprintf(EL_CD, "cd: run event #%d %u", oldest, time);
pcd_event_cbs[oldest](time);
}
else if (oldest_diff < 0x7fffffff) {
event_time_next = pcd_event_times[oldest];
break;
}
else {
event_time_next = 0;
break;
}
}
if (oldest != -1)
elprintf(EL_CD, "cd: next event #%d at %u",
oldest, event_time_next);
}
int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync)
{
#define now SekCycleCntS68k
unsigned int s68k_target =
(unsigned long long)m68k_target * m68k_cycle_mult >> 16;
unsigned int target;
elprintf(EL_CD, "s68k sync to %u, %u->%u",
m68k_target, now, s68k_target);
if (Pico_mcd->m.busreq != 1) { /* busreq/reset */
SekCycleCntS68k = SekCycleAimS68k = s68k_target;
pcd_run_events(m68k_target);
return 0;
}
while (CYCLES_GT(s68k_target, now)) {
if (event_time_next && CYCLES_GE(now, event_time_next))
pcd_run_events(now);
target = s68k_target;
if (event_time_next && CYCLES_GT(target, event_time_next))
target = event_time_next;
SekRunS68k(target);
if (m68k_poll_sync && Pico_mcd->m.m68k_poll_cnt == 0)
break;
}
return s68k_target - now;
#undef now
}
#define pcd_run_cpus_normal pcd_run_cpus
//#define pcd_run_cpus_lockstep pcd_run_cpus
static void SekSyncM68k(void);
static inline void pcd_run_cpus_normal(int m68k_cycles)
{
SekCycleAim += m68k_cycles;
if (Pico_mcd->m.m68k_poll_cnt >= 16 && !SekShouldInterrupt()) {
int s68k_left = pcd_sync_s68k(SekCycleAim, 1);
if (s68k_left <= 0) {
elprintf(EL_CDPOLL, "m68k poll [%02x] x%d @%06x",
Pico_mcd->m.m68k_poll_a, Pico_mcd->m.m68k_poll_cnt, SekPc);
SekCycleCnt = SekCycleAim;
return;
}
SekCycleCnt = SekCycleAim - (s68k_left * 40220 >> 16);
}
SekSyncM68k();
}
static inline void pcd_run_cpus_lockstep(int m68k_cycles)
{
unsigned int target = SekCycleAim + m68k_cycles;
do {
SekCycleAim += 8;
SekSyncM68k();
pcd_sync_s68k(SekCycleAim, 0);
} while (CYCLES_GT(target, SekCycleAim));
}
#define PICO_CD
#define CPUS_RUN(m68k_cycles) \
pcd_run_cpus(m68k_cycles)
#include "../pico_cmn.c"
PICO_INTERNAL void PicoFrameMCD(void)
{
if (!(PicoOpt&POPT_ALT_RENDERER))
PicoFrameStart();
// ~1.63 for NTSC, ~1.645 for PAL
if (Pico.m.pal)
m68k_cycle_mult = ((12500000ull << 16) / (50*312*488));
else
m68k_cycle_mult = ((12500000ull << 16) / (60*262*488)) + 1;
PicoFrameHints();
}
void pcd_state_loaded(void)
{
unsigned int cycles;
int diff;
pcd_state_loaded_mem();
// old savestates..
cycles = pcd_cycles_m68k_to_s68k(SekCycleAim);
diff = cycles - SekCycleAimS68k;
if (diff < -1000 || diff > 1000) {
SekCycleCntS68k = SekCycleAimS68k = cycles;
}
if (pcd_event_times[PCD_EVENT_CDC] == 0) {
pcd_event_schedule(SekCycleAimS68k, PCD_EVENT_CDC, 12500000/75);
if (Pico_mcd->s68k_regs[0x31])
pcd_event_schedule(SekCycleAimS68k, PCD_EVENT_TIMER3,
Pico_mcd->s68k_regs[0x31] * 384);
if (Pico_mcd->rot_comp.Reg_58 & 0x8000) {
Pico_mcd->rot_comp.Reg_58 &= 0x7fff;
Pico_mcd->rot_comp.Reg_64 = 0;
if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN1)
SekInterruptS68k(1);
}
if (Pico_mcd->scd.Status_CDC & 0x08)
Update_CDC_TRansfer(Pico_mcd->s68k_regs[4] & 7);
}
}
// vim:shiftwidth=2:ts=2:expandtab

0
pico/cd/pico_arm.s → pico/cd/mcd_arm.s
View file

324
pico/cd/memory.c
View file

@ -65,28 +65,41 @@ void PicoWriteS68k16_dec_m1b1(u32 a, u32 d);
void PicoWriteS68k16_dec_m2b1(u32 a, u32 d);
#endif
static void remap_prg_window(void);
static void remap_word_ram(int r3);
static void remap_prg_window(u32 r1, u32 r3);
static void remap_word_ram(u32 r3);
// poller detection
#define POLL_LIMIT 16
#define POLL_CYCLES 124
unsigned int s68k_poll_adclk, s68k_poll_cnt;
u32 m68k_comm_check(u32 a, u32 d)
{
pcd_sync_s68k(SekCyclesDone(), 0);
if (a != Pico_mcd->m.m68k_poll_a) {
Pico_mcd->m.m68k_poll_a = a;
Pico_mcd->m.m68k_poll_cnt = 0;
return d;
}
Pico_mcd->m.m68k_poll_cnt++;
return d;
}
#ifndef _ASM_CD_MEMORY_C
static u32 m68k_reg_read16(u32 a)
{
u32 d=0;
u32 d = 0;
a &= 0x3e;
switch (a) {
case 0:
d = ((Pico_mcd->s68k_regs[0x33]<<13)&0x8000) | Pico_mcd->m.busreq; // here IFL2 is always 0, just like in Gens
// here IFL2 is always 0, just like in Gens
d = ((Pico_mcd->s68k_regs[0x33] << 13) & 0x8000)
| Pico_mcd->m.busreq;
goto end;
case 2:
d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);
elprintf(EL_CDREG3, "m68k_regs r3: %02x @%06x", (u8)d, SekPc);
goto end;
goto end_comm;
case 4:
d = Pico_mcd->s68k_regs[4]<<8;
goto end;
@ -99,8 +112,11 @@ static u32 m68k_reg_read16(u32 a)
case 0xA:
elprintf(EL_UIO, "m68k FIXME: reserved read");
goto end;
case 0xC:
d = Pico_mcd->m.timer_stopwatch >> 16;
case 0xC: // 384 cycle stopwatch timer
// ugh..
d = pcd_cycles_m68k_to_s68k(SekCyclesDone());
d = (d - Pico_mcd->m.stopwatch_base_c) / 384;
d &= 0x0fff;
elprintf(EL_CDREGS, "m68k stopwatch timer read (%04x)", d);
goto end;
}
@ -108,14 +124,16 @@ static u32 m68k_reg_read16(u32 a)
if (a < 0x30) {
// comm flag/cmd/status (0xE-0x2F)
d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];
goto end;
goto end_comm;
}
elprintf(EL_UIO, "m68k_regs FIXME invalid read @ %02x", a);
end:
return d;
end_comm:
return m68k_comm_check(a, d);
}
#endif
@ -127,25 +145,41 @@ void m68k_reg_write8(u32 a, u32 d)
u32 dold;
a &= 0x3f;
Pico_mcd->m.m68k_poll_a =
Pico_mcd->m.m68k_poll_cnt = 0;
switch (a) {
case 0:
d &= 1;
if ((d&1) && (Pico_mcd->s68k_regs[0x33]&(1<<2))) { elprintf(EL_INTS, "m68k: s68k irq 2"); SekInterruptS68k(2); }
if (d && (Pico_mcd->s68k_regs[0x33] & PCDS_IEN2)) {
elprintf(EL_INTS, "m68k: s68k irq 2");
pcd_sync_s68k(SekCyclesDone(), 0);
SekInterruptS68k(2);
}
return;
case 1:
d &= 3;
if (!(d&1)) Pico_mcd->m.state_flags |= 1; // reset pending, needed to be sure we fetch the right vectors on reset
if ( (Pico_mcd->m.busreq&1) != (d&1)) elprintf(EL_INTSW, "m68k: s68k reset %i", !(d&1));
if ( (Pico_mcd->m.busreq&2) != (d&2)) elprintf(EL_INTSW, "m68k: s68k brq %i", (d&2)>>1);
if ((Pico_mcd->m.state_flags&1) && (d&3)==1) {
SekResetS68k(); // S68k comes out of RESET or BRQ state
Pico_mcd->m.state_flags&=~1;
elprintf(EL_CDREGS, "m68k: resetting s68k, cycles=%i", SekCyclesLeft);
}
dold = Pico_mcd->m.busreq;
if (!(d & 1))
d |= 2; // verified: reset also gives bus
if ((d ^ Pico_mcd->m.busreq) & 2)
remap_prg_window();
d |= 2; // verified: can't release bus on reset
if (dold == d)
return;
pcd_sync_s68k(SekCyclesDone(), 0);
if ((dold ^ d) & 1)
elprintf(EL_INTSW, "m68k: s68k reset %i", !(d&1));
if (!(d & 1))
Pico_mcd->m.state_flags |= PCD_ST_S68K_RST;
else if (d == 1 && (Pico_mcd->m.state_flags & PCD_ST_S68K_RST)) {
Pico_mcd->m.state_flags &= ~PCD_ST_S68K_RST;
elprintf(EL_CDREGS, "m68k: resetting s68k");
SekResetS68k();
}
if ((dold ^ d) & 2) {
elprintf(EL_INTSW, "m68k: s68k brq %i", d >> 1);
remap_prg_window(d, Pico_mcd->s68k_regs[3]);
}
Pico_mcd->m.busreq = d;
return;
case 2:
@ -155,30 +189,25 @@ void m68k_reg_write8(u32 a, u32 d)
case 3:
dold = Pico_mcd->s68k_regs[3];
elprintf(EL_CDREG3, "m68k_regs w3: %02x @%06x", (u8)d, SekPc);
//if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);
//if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :
// ((d&2) ? "word ram to s68k" : "word ram to m68k"));
if (dold & 4) { // 1M mode
d ^= 2; // writing 0 to DMNA actually sets it, 1 does nothing
} else {
if ((d ^ dold) & d & 2) { // DMNA is being set
dold &= ~1; // return word RAM to s68k
/* Silpheed hack: bset(w3), r3, btst, bne, r3 */
SekEndRun(20+16+10+12+16);
}
}
Pico_mcd->s68k_regs[3] = (d & 0xc2) | (dold & 0x1f);
if ((d ^ dold) & 0xc0) {
elprintf(EL_CDREGS, "m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));
remap_prg_window();
elprintf(EL_CDREGS, "m68k: prg bank: %i -> %i",
(Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));
remap_prg_window(Pico_mcd->m.busreq, d);
}
#ifdef USE_POLL_DETECT
if ((s68k_poll_adclk&0xfe) == 2 && s68k_poll_cnt > POLL_LIMIT) {
SekSetStopS68k(0); s68k_poll_adclk = 0;
elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);
// 2M mode state is tracked regardless of current mode
if (d & 2) {
Pico_mcd->m.dmna_ret_2m |= 2;
Pico_mcd->m.dmna_ret_2m &= ~1;
}
#endif
return;
if (dold & 4) { // 1M mode
d ^= 2; // 0 sets DMNA, 1 does nothing
d = (d & 0xc2) | (dold & 0x1f);
}
else
d = (d & 0xc0) | (dold & 0x1c) | Pico_mcd->m.dmna_ret_2m;
goto write_comm;
case 6:
Pico_mcd->bios[0x72 + 1] = d; // simple hint vector changer
return;
@ -187,32 +216,29 @@ void m68k_reg_write8(u32 a, u32 d)
elprintf(EL_CDREGS, "hint vector set to %04x%04x",
((u16 *)Pico_mcd->bios)[0x70/2], ((u16 *)Pico_mcd->bios)[0x72/2]);
return;
case 0xf:
d = (d << 1) | ((d >> 7) & 1); // rol8 1 (special case)
case 0xe:
//dprintf("m68k: comm flag: %02x", d);
Pico_mcd->s68k_regs[0xe] = d;
#ifdef USE_POLL_DETECT
if ((s68k_poll_adclk&0xfe) == 0xe && s68k_poll_cnt > POLL_LIMIT) {
SekSetStopS68k(0); s68k_poll_adclk = 0;
elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);
}
#endif
return;
case 0x0f:
a = 0x0e;
case 0x0e:
goto write_comm;
}
if ((a&0xf0) == 0x10) {
Pico_mcd->s68k_regs[a] = d;
#ifdef USE_POLL_DETECT
if ((a&0xfe) == (s68k_poll_adclk&0xfe) && s68k_poll_cnt > POLL_LIMIT) {
SekSetStopS68k(0); s68k_poll_adclk = 0;
elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);
}
#endif
return;
}
if ((a&0xf0) == 0x10)
goto write_comm;
elprintf(EL_UIO, "m68k FIXME: invalid write? [%02x] %02x", a, d);
return;
write_comm:
if (d == Pico_mcd->s68k_regs[a])
return;
Pico_mcd->s68k_regs[a] = d;
pcd_sync_s68k(SekCyclesDone(), 0);
if (Pico_mcd->m.s68k_poll_a == a && Pico_mcd->m.s68k_poll_cnt > POLL_LIMIT) {
SekSetStopS68k(0);
Pico_mcd->m.s68k_poll_a = 0;
elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);
}
}
#ifndef _ASM_CD_MEMORY_C
@ -221,24 +247,26 @@ static
u32 s68k_poll_detect(u32 a, u32 d)
{
#ifdef USE_POLL_DETECT
// needed mostly for Cyclone, which doesn't always check it's cycle counter
if (SekIsStoppedS68k()) return d;
// polling detection
if (a == (s68k_poll_adclk&0xff)) {
unsigned int clkdiff = SekCyclesDoneS68k() - (s68k_poll_adclk>>8);
u32 cycles, cnt = 0;
if (SekIsStoppedS68k())
return d;
cycles = SekCyclesDoneS68k();
if (a == Pico_mcd->m.s68k_poll_a) {
u32 clkdiff = cycles - Pico_mcd->m.s68k_poll_clk;
if (clkdiff <= POLL_CYCLES) {
s68k_poll_cnt++;
//printf("-- diff: %u, cnt = %i\n", clkdiff, s68k_poll_cnt);
if (s68k_poll_cnt > POLL_LIMIT) {
cnt = Pico_mcd->m.s68k_poll_cnt + 1;
//printf("-- diff: %u, cnt = %i\n", clkdiff, cnt);
if (Pico_mcd->m.s68k_poll_cnt > POLL_LIMIT) {
SekSetStopS68k(1);
elprintf(EL_CDPOLL, "s68k poll detected @ %06x, a=%02x", SekPcS68k, a);
elprintf(EL_CDPOLL, "s68k poll detected @ %06x, a=%02x",
SekPcS68k, a);
}
s68k_poll_adclk = (SekCyclesDoneS68k() << 8) | a;
return d;
}
}
s68k_poll_adclk = (SekCyclesDoneS68k() << 8) | a;
s68k_poll_cnt = 0;
Pico_mcd->m.s68k_poll_a = a;
Pico_mcd->m.s68k_poll_clk = cycles;
Pico_mcd->m.s68k_poll_cnt = cnt;
#endif
return d;
}
@ -273,7 +301,9 @@ u32 s68k_reg_read16(u32 a)
case 8:
return Read_CDC_Host(1); // Gens returns 0 here on byte reads
case 0xC:
d = Pico_mcd->m.timer_stopwatch >> 16;
d = SekCyclesDoneS68k() - Pico_mcd->m.stopwatch_base_c;
d /= 384;
d &= 0x0fff;
elprintf(EL_CDREGS, "s68k stopwatch timer read (%04x)", d);
return d;
case 0x30:
@ -317,37 +347,36 @@ void s68k_reg_write8(u32 a, u32 d)
elprintf(EL_CDREG3, "s68k_regs w3: %02x @%06x", (u8)d, SekPcS68k);
d &= 0x1d;
d |= dold & 0xc2;
// 2M mode state
if (d & 1) {
Pico_mcd->m.dmna_ret_2m |= 1;
Pico_mcd->m.dmna_ret_2m &= ~2; // DMNA clears
}
if (d & 4)
{
if ((d ^ dold) & 0x1d) {
d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit
remap_word_ram(d);
}
if (!(dold & 4)) {
elprintf(EL_CDREG3, "wram mode 2M->1M");
wram_2M_to_1M(Pico_mcd->word_ram2M);
}
if ((d ^ dold) & 0x1d)
remap_word_ram(d);
if ((d ^ dold) & 0x05)
d &= ~2; // clear DMNA - swap complete
}
else
{
if (dold & 4) {
elprintf(EL_CDREG3, "wram mode 1M->2M");
if (!(d&1)) { // it didn't set the ret bit, which means it doesn't want to give WRAM to m68k
d &= ~3;
d |= (dold&1) ? 2 : 1; // then give it to the one which had bank0 in 1M mode
}
wram_1M_to_2M(Pico_mcd->word_ram2M);
remap_word_ram(d);
}
// s68k can only set RET, writing 0 has no effect
else if ((dold ^ d) & d & 1) { // RET being set
SekEndRunS68k(20+16+10+12+16); // see DMNA case
} else
d |= dold & 1;
if (d & 1)
d &= ~2; // DMNA clears
d = (d & ~3) | Pico_mcd->m.dmna_ret_2m;
}
break;
goto write_comm;
}
case 4:
elprintf(EL_CDREGS, "s68k CDC dest: %x", d&7);
@ -363,21 +392,30 @@ void s68k_reg_write8(u32 a, u32 d)
elprintf(EL_CDREGS, "s68k set CDC dma addr");
break;
case 0xc:
case 0xd:
elprintf(EL_CDREGS, "s68k set stopwatch timer");
Pico_mcd->m.timer_stopwatch = 0;
case 0xd: // 384 cycle stopwatch timer
elprintf(EL_CDREGS|EL_CD, "s68k clear stopwatch (%x)", d);
// does this also reset internal 384 cycle counter?
Pico_mcd->m.stopwatch_base_c = SekCyclesDoneS68k();
return;
case 0xe:
Pico_mcd->s68k_regs[0xf] = (d>>1) | (d<<7); // ror8 1, Gens note: Dragons lair
return;
case 0x31:
elprintf(EL_CDREGS, "s68k set int3 timer: %02x", d);
Pico_mcd->m.timer_int3 = (d & 0xff) << 16;
case 0x0e:
a = 0x0f;
case 0x0f:
goto write_comm;
case 0x31: // 384 cycle int3 timer
d &= 0xff;
elprintf(EL_CDREGS|EL_CD, "s68k set int3 timer: %02x", d);
Pico_mcd->s68k_regs[a] = (u8) d;
if (d) // d or d+1??
pcd_event_schedule_s68k(PCD_EVENT_TIMER3, d * 384);
else
pcd_event_schedule(0, PCD_EVENT_TIMER3, 0);
break;
case 0x33: // IRQ mask
elprintf(EL_CDREGS, "s68k irq mask: %02x", d);
if ((d&(1<<4)) && (Pico_mcd->s68k_regs[0x37]&4) && !(Pico_mcd->s68k_regs[0x33]&(1<<4))) {
CDD_Export_Status();
elprintf(EL_CDREGS|EL_CD, "s68k irq mask: %02x", d);
d &= 0x7e;
if ((d ^ Pico_mcd->s68k_regs[0x33]) & d & PCDS_IEN4) {
if (Pico_mcd->s68k_regs[0x37] & 4)
CDD_Export_Status();
}
break;
case 0x34: // fader
@ -399,6 +437,9 @@ void s68k_reg_write8(u32 a, u32 d)
return;
}
if ((a&0x1f0) == 0x20)
goto write_comm;
if ((a&0x1f0) == 0x10 || (a >= 0x38 && a < 0x42))
{
elprintf(EL_UIO, "s68k FIXME: invalid write @ %02x?", a);
@ -406,6 +447,13 @@ void s68k_reg_write8(u32 a, u32 d)
}
Pico_mcd->s68k_regs[a] = (u8) d;
return;
write_comm:
Pico_mcd->s68k_regs[a] = (u8) d;
if (Pico_mcd->m.m68k_poll_cnt)
SekEndRunS68k(0);
Pico_mcd->m.m68k_poll_cnt = 0;
}
// -----------------------------------------------------------------
@ -563,20 +611,10 @@ static void PicoWriteM68k16_io(u32 a, u32 d)
{
if ((a & 0xff00) == 0x2000) { // a12000 - a120ff
elprintf(EL_CDREGS, "m68k_regs w16: [%02x] %04x @%06x", a&0x3f, d, SekPc);
/* TODO FIXME?
if (a == 0xe) { // special case, 2 byte writes would be handled differently
Pico_mcd->s68k_regs[0xe] = d >> 8;
#ifdef USE_POLL_DETECT
if ((s68k_poll_adclk&0xfe) == 0xe && s68k_poll_cnt > POLL_LIMIT) {
SekSetStopS68k(0); s68k_poll_adclk = 0;
elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);
}
#endif
return;
}
*/
m68k_reg_write8(a, d >> 8);
m68k_reg_write8(a + 1, d & 0xff);
if ((a & 0x3e) != 0x0e) // special case
m68k_reg_write8(a + 1, d & 0xff);
return;
}
@ -610,17 +648,17 @@ static void s68k_unmapped_write16(u32 a, u32 d)
elprintf(EL_UIO, "s68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
}
// PRG RAM protected range (000000 - 00ff00)?
// PRG RAM protected range (000000 - 01fdff)?
// XXX verify: ff00 or 1fe00 max?
static void PicoWriteS68k8_prgwp(u32 a, u32 d)
{
if (a >= (Pico_mcd->s68k_regs[2] << 8))
if (a >= (Pico_mcd->s68k_regs[2] << 9))
Pico_mcd->prg_ram[a ^ 1] = d;
}
static void PicoWriteS68k16_prgwp(u32 a, u32 d)
{
if (a >= (Pico_mcd->s68k_regs[2] << 8))
if (a >= (Pico_mcd->s68k_regs[2] << 9))
*(u16 *)(Pico_mcd->prg_ram + a) = d;
}
@ -769,20 +807,22 @@ static u32 PicoReadS68k8_pr(u32 a)
// regs
if ((a & 0xfe00) == 0x8000) {
a &= 0x1ff;
elprintf(EL_CDREGS, "s68k_regs r8: [%02x] @ %06x", a, SekPcS68k);
if (a >= 0x0e && a < 0x30) {
d = Pico_mcd->s68k_regs[a];
s68k_poll_detect(a, d);
elprintf(EL_CDREGS, "ret = %02x", (u8)d);
return d;
goto regs_done;
}
else if (a >= 0x58 && a < 0x68)
d = gfx_cd_read(a & ~1);
else d = s68k_reg_read16(a & ~1);
if (!(a & 1))
d >>= 8;
elprintf(EL_CDREGS, "ret = %02x", (u8)d);
return d & 0xff;
regs_done:
d &= 0xff;
elprintf(EL_CDREGS, "s68k_regs r8: [%02x] %02x @ %06x",
a, d, SekPcS68k);
return d;
}
// PCM
@ -810,11 +850,12 @@ static u32 PicoReadS68k16_pr(u32 a)
// regs
if ((a & 0xfe00) == 0x8000) {
a &= 0x1fe;
elprintf(EL_CDREGS, "s68k_regs r16: [%02x] @ %06x", a, SekPcS68k);
if (0x58 <= a && a < 0x68)
d = gfx_cd_read(a);
else d = s68k_reg_read16(a);
elprintf(EL_CDREGS, "ret = %04x", d);
elprintf(EL_CDREGS, "s68k_regs r16: [%02x] %04x @ %06x",
a, d, SekPcS68k);
return d;
}
@ -917,11 +958,11 @@ static const void *s68k_dec_write16[2][4] = {
// -----------------------------------------------------------------
static void remap_prg_window(void)
static void remap_prg_window(u32 r1, u32 r3)
{
// PRG RAM
if (Pico_mcd->m.busreq & 2) {
void *bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3] >> 6];
if (r1 & 2) {
void *bank = Pico_mcd->prg_ram_b[(r3 >> 6) & 3];
cpu68k_map_all_ram(0x020000, 0x03ffff, bank, 0);
}
else {
@ -929,7 +970,7 @@ static void remap_prg_window(void)
}
}
static void remap_word_ram(int r3)
static void remap_word_ram(u32 r3)
{
void *bank;
@ -978,15 +1019,16 @@ static void remap_word_ram(int r3)
#endif
}
void PicoMemStateLoaded(void)
void pcd_state_loaded_mem(void)
{
int r3 = Pico_mcd->s68k_regs[3];
u32 r3 = Pico_mcd->s68k_regs[3];
/* after load events */
if (r3 & 4) // 1M mode?
wram_2M_to_1M(Pico_mcd->word_ram2M);
remap_word_ram(r3);
remap_prg_window();
remap_prg_window(Pico_mcd->m.busreq, r3);
Pico_mcd->m.dmna_ret_2m &= 3;
// restore hint vector
*(unsigned short *)(Pico_mcd->bios + 0x72) = Pico_mcd->m.hint_vector;
@ -1027,8 +1069,8 @@ PICO_INTERNAL void PicoMemSetupCD(void)
cpu68k_map_set(s68k_read16_map, 0x000000, 0x07ffff, Pico_mcd->prg_ram, 0);
cpu68k_map_set(s68k_write8_map, 0x000000, 0x07ffff, Pico_mcd->prg_ram, 0);
cpu68k_map_set(s68k_write16_map, 0x000000, 0x07ffff, Pico_mcd->prg_ram, 0);
cpu68k_map_set(s68k_write8_map, 0x000000, 0x00ffff, PicoWriteS68k8_prgwp, 1);
cpu68k_map_set(s68k_write16_map, 0x000000, 0x00ffff, PicoWriteS68k16_prgwp, 1);
cpu68k_map_set(s68k_write8_map, 0x000000, 0x01ffff, PicoWriteS68k8_prgwp, 1);
cpu68k_map_set(s68k_write16_map, 0x000000, 0x01ffff, PicoWriteS68k16_prgwp, 1);
// BRAM
cpu68k_map_set(s68k_read8_map, 0xfe0000, 0xfeffff, PicoReadS68k8_bram, 1);
@ -1096,9 +1138,6 @@ PICO_INTERNAL void PicoMemSetupCD(void)
#ifdef EMU_M68K
m68k_mem_setup_cd();
#endif
// m68k_poll_addr = m68k_poll_cnt = 0;
s68k_poll_adclk = s68k_poll_cnt = 0;
}
@ -1147,3 +1186,4 @@ static void m68k_mem_setup_cd(void)
}
#endif // EMU_M68K
// vim:shiftwidth=2:ts=2:expandtab

72
pico/cd/memory_arm.s
View file

@ -53,7 +53,6 @@
.extern m68k_reg_write8
.extern s68k_reg_read16
.extern s68k_reg_write8
.extern s68k_poll_adclk
.extern s68k_poll_detect
.extern gfx_cd_read
.extern gfx_cd_write16
@ -62,6 +61,7 @@
.extern PicoRead16_io
.extern PicoWrite8_io
.extern PicoWrite16_io
.extern m68k_comm_check
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@ -174,17 +174,16 @@ m_m68k_read8_r02:
add r1, r1, #0x110000
ldrb r0, [r1, #2]
bx lr
m_m68k_read8_r03:
add r1, r1, #0x110000
ldrb r0, [r1, #3]
add r1, r1, #0x002200
ldr r1, [r1, #4]
and r0, r0, #0xc7
tst r1, #2 @ DMNA pending?
bxeq lr
bic r0, r0, #1
orr r0, r0, #2
bx lr
m_m68k_read8_r03: @ FIXME: sync with C
add r2, r1, #0x110000
ldrb r1, [r2, #3]
add r2, r2, #0x002200
ldr r2, [r2, #4]
and r1, r1, #0xc7
tst r2, #2 @ DMNA pending?
bicne r1, r1, #1
orrne r1, r1, #2
b m68k_comm_check
m_m68k_read8_r04:
add r1, r1, #0x110000
ldrb r0, [r1, #4]
@ -220,8 +219,8 @@ m_m68k_read8_hi:
movge r0, #0
bxeq lr
add r1, r1, #0x110000
ldrb r0, [r1, r0]
bx lr
ldrb r1, [r1, r0]
b m68k_comm_check
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@ -270,19 +269,18 @@ m_m68k_read16_r00:
and r0, r0, #0x04000000 @ we need irq2 mask state
orr r0, r1, r0, lsr #11
bx lr
m_m68k_read16_r02:
add r1, r1, #0x110000
ldrb r0, [r1, #2]
ldrb r2, [r1, #3]
add r1, r1, #0x002200
ldr r1, [r1, #4]
m_m68k_read16_r02: @ FIXME: out of sync from C
add r3, r1, #0x110000
ldrb r1, [r3, #2]
ldrb r2, [r3, #3]
add r3, r3, #0x002200
ldr r3, [r3, #4]
and r2, r2, #0xc7
orr r0, r2, r0, lsl #8
tst r1, #2 @ DMNA pending?
bxeq lr
bic r0, r0, #1
orr r0, r0, #2
bx lr
orr r1, r2, r1, lsl #8
tst r3, #2 @ DMNA pending?
bicne r1, r1, #1
orrne r1, r1, #2
b m68k_comm_check
m_m68k_read16_r04:
add r1, r1, #0x110000
ldrb r0, [r1, #4]
@ -306,10 +304,10 @@ m_m68k_read16_hi:
ldrlth r1, [r1, r0]
movge r0, #0
bxge lr
mov r0, r1, lsr #8
mov r2, r1, lsr #8
and r1, r1, #0xff
orr r0, r0, r1, lsl #8
bx lr
orr r1, r2, r1, lsl #8
b m68k_comm_check
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@ -377,22 +375,8 @@ m_m68k_write16_regs:
b m68k_reg_write8
m_m68k_write16_regs_spec: @ special case
ldr r2, =(Pico+0x22200)
ldr r3, =s68k_poll_adclk
mov r0, #0x110000
ldr r2, [r2]
add r0, r0, #0x00000e
mov r1, r1, lsr #8
strb r1, [r2, r0] @ if (a == 0xe) s68k_regs[0x0e] = d >> 8;
ldr r2, [r3]
mov r1, #0
and r2, r2, #0xfe
cmp r2, #0x0e
bxne lr
ldr r0, =PicoCpuCS68k
str r1, [r0, #0x58] @ push s68k out of stopped state
str r1, [r3]
bx lr
b m68k_reg_write8
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

222
pico/cd/pico.c
View file

@ -1,222 +0,0 @@
/*
* PicoDrive
* (C) notaz, 2007
*
* This work is licensed under the terms of MAME license.
* See COPYING file in the top-level directory.
*/
#include "../pico_int.h"
#include "../sound/ym2612.h"
extern unsigned char formatted_bram[4*0x10];
extern unsigned int s68k_poll_adclk;
void (*PicoMCDopenTray)(void) = NULL;
void (*PicoMCDcloseTray)(void) = NULL;
PICO_INTERNAL void PicoInitMCD(void)
{
SekInitS68k();
Init_CD_Driver();
}
PICO_INTERNAL void PicoExitMCD(void)
{
End_CD_Driver();
}
PICO_INTERNAL void PicoPowerMCD(void)
{
int fmt_size = sizeof(formatted_bram);
memset(Pico_mcd->prg_ram, 0, sizeof(Pico_mcd->prg_ram));
memset(Pico_mcd->word_ram2M, 0, sizeof(Pico_mcd->word_ram2M));
memset(Pico_mcd->pcm_ram, 0, sizeof(Pico_mcd->pcm_ram));
memset(Pico_mcd->bram, 0, sizeof(Pico_mcd->bram));
memcpy(Pico_mcd->bram + sizeof(Pico_mcd->bram) - fmt_size, formatted_bram, fmt_size);
}
PICO_INTERNAL int PicoResetMCD(void)
{
memset(Pico_mcd->s68k_regs, 0, sizeof(Pico_mcd->s68k_regs));
memset(&Pico_mcd->pcm, 0, sizeof(Pico_mcd->pcm));
memset(&Pico_mcd->m, 0, sizeof(Pico_mcd->m));
*(unsigned int *)(Pico_mcd->bios + 0x70) = 0xffffffff; // reset hint vector (simplest way to implement reg6)
Pico_mcd->m.state_flags |= 1; // s68k reset pending
Pico_mcd->s68k_regs[3] = 1; // 2M word RAM mode with m68k access after reset
Reset_CD();
LC89510_Reset();
gfx_cd_reset();
#ifdef _ASM_CD_MEMORY_C
//PicoMemResetCDdecode(1); // don't have to call this in 2M mode
#endif
// use SRam.data for RAM cart
if (PicoOpt & POPT_EN_MCD_RAMCART) {
if (SRam.data == NULL)
SRam.data = calloc(1, 0x12000);
}
else if (SRam.data != NULL) {
free(SRam.data);
SRam.data = NULL;
}
SRam.start = SRam.end = 0; // unused
return 0;
}
static __inline void SekRunS68k(int cyc)
{
int cyc_do;
SekCycleAimS68k+=cyc;
if ((cyc_do=SekCycleAimS68k-SekCycleCntS68k) <= 0) return;
#if defined(EMU_CORE_DEBUG)
SekCycleCntS68k+=CM_compareRun(cyc_do, 1);
#elif defined(EMU_C68K)
PicoCpuCS68k.cycles=cyc_do;
CycloneRun(&PicoCpuCS68k);
SekCycleCntS68k+=cyc_do-PicoCpuCS68k.cycles;
#elif defined(EMU_M68K)
m68k_set_context(&PicoCpuMS68k);
SekCycleCntS68k+=m68k_execute(cyc_do);
m68k_set_context(&PicoCpuMM68k);
#elif defined(EMU_F68K)
g_m68kcontext=&PicoCpuFS68k;
SekCycleCntS68k+=fm68k_emulate(cyc_do, 0, 0);
g_m68kcontext=&PicoCpuFM68k;
#endif
}
#define PS_STEP_M68K ((488<<16)/20) // ~24
//#define PS_STEP_S68K 13
#if defined(_ASM_CD_PICO_C)
extern void SekRunPS(int cyc_m68k, int cyc_s68k);
#elif defined(EMU_F68K)
static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
{
SekCycleAim+=cyc_m68k;
SekCycleAimS68k+=cyc_s68k;
fm68k_emulate(0, 1, 0);
}
#else
static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
{
int cycn, cycn_s68k, cyc_do;
SekCycleAim+=cyc_m68k;
SekCycleAimS68k+=cyc_s68k;
// fprintf(stderr, "=== start %3i/%3i [%3i/%3i] {%05i.%i} ===\n", cyc_m68k, cyc_s68k,
// SekCycleAim-SekCycleCnt, SekCycleAimS68k-SekCycleCntS68k, Pico.m.frame_count, Pico.m.scanline);
/* loop 488 downto 0 in steps of PS_STEP */
for (cycn = (488<<16)-PS_STEP_M68K; cycn >= 0; cycn -= PS_STEP_M68K)
{
cycn_s68k = (cycn + cycn/2 + cycn/8) >> 16;
if ((cyc_do = SekCycleAim-SekCycleCnt-(cycn>>16)) > 0) {
#if defined(EMU_C68K)
PicoCpuCM68k.cycles = cyc_do;
CycloneRun(&PicoCpuCM68k);
SekCycleCnt += cyc_do - PicoCpuCM68k.cycles;
#elif defined(EMU_M68K)
m68k_set_context(&PicoCpuMM68k);
SekCycleCnt += m68k_execute(cyc_do);
#elif defined(EMU_F68K)
g_m68kcontext = &PicoCpuFM68k;
SekCycleCnt += fm68k_emulate(cyc_do, 0, 0);
#endif
}
if ((cyc_do = SekCycleAimS68k-SekCycleCntS68k-cycn_s68k) > 0) {
#if defined(EMU_C68K)
PicoCpuCS68k.cycles = cyc_do;
CycloneRun(&PicoCpuCS68k);
SekCycleCntS68k += cyc_do - PicoCpuCS68k.cycles;
#elif defined(EMU_M68K)
m68k_set_context(&PicoCpuMS68k);
SekCycleCntS68k += m68k_execute(cyc_do);
#elif defined(EMU_F68K)
g_m68kcontext = &PicoCpuFS68k;
SekCycleCntS68k += fm68k_emulate(cyc_do, 0, 0);
#endif
}
}
}
#endif
static __inline void check_cd_dma(void)
{
int ddx;
if (!(Pico_mcd->scd.Status_CDC & 0x08)) return;
ddx = Pico_mcd->s68k_regs[4] & 7;
if (ddx < 2) return; // invalid
if (ddx < 4) {
Pico_mcd->s68k_regs[4] |= 0x40; // Data set ready in host port
return;
}
if (ddx == 6) return; // invalid
Update_CDC_TRansfer(ddx); // now go and do the actual transfer
}
static __inline void update_chips(void)
{
int counter_timer, int3_set;
int counter75hz_lim = Pico.m.pal ? 2080 : 2096;
// 75Hz CDC update
if ((Pico_mcd->m.counter75hz+=10) >= counter75hz_lim) {
Pico_mcd->m.counter75hz -= counter75hz_lim;
Check_CD_Command();
}
// update timers
counter_timer = Pico.m.pal ? 0x21630 : 0x2121c; // 136752 : 135708;
Pico_mcd->m.timer_stopwatch += counter_timer;
if ((int3_set = Pico_mcd->s68k_regs[0x31])) {
Pico_mcd->m.timer_int3 -= counter_timer;
if (Pico_mcd->m.timer_int3 < 0) {
if (Pico_mcd->s68k_regs[0x33] & (1<<3)) {
elprintf(EL_INTS, "s68k: timer irq 3");
SekInterruptS68k(3);
Pico_mcd->m.timer_int3 += int3_set << 16;
}
// is this really what happens if irq3 is masked out?
Pico_mcd->m.timer_int3 &= 0xffffff;
}
}
// update gfx chip
if (Pico_mcd->rot_comp.Reg_58 & 0x8000)
gfx_cd_update();
}
#define PICO_CD
#define CPUS_RUN(m68k_cycles,s68k_cycles) \
{ \
if ((PicoOpt&POPT_EN_MCD_PSYNC) && (Pico_mcd->m.busreq&3) == 1) { \
SekRunPS(m68k_cycles, s68k_cycles); /* "better/perfect sync" */ \
} else { \
SekRunM68k(m68k_cycles); \
if ((Pico_mcd->m.busreq&3) == 1) /* no busreq/no reset */ \
SekRunS68k(s68k_cycles); \
} \
}
#include "../pico_cmn.c"
PICO_INTERNAL void PicoFrameMCD(void)
{
if (!(PicoOpt&POPT_ALT_RENDERER))
PicoFrameStart();
PicoFrameHints();
}

4
pico/cd/sek.c
View file

@ -9,8 +9,8 @@
#include "../pico_int.h"
int SekCycleCntS68k=0; // cycles done in this frame
int SekCycleAimS68k=0; // cycle aim
unsigned int SekCycleCntS68k;
unsigned int SekCycleAimS68k;
/* context */

38
pico/debug.c
View file

@ -40,14 +40,11 @@ char *PDebugMain(void)
sprintf(dstrp, "mode set 4: %02x\n", (r=reg[0xC])); MVP;
sprintf(dstrp, "interlace: %i%i, cells: %i, shadow: %i\n", bit(r,2), bit(r,1), (r&0x80) ? 40 : 32, bit(r,3)); MVP;
sprintf(dstrp, "scroll size: w: %i, h: %i SRAM: %i; eeprom: %i (%i)\n", reg[0x10]&3, (reg[0x10]&0x30)>>4,
!!(SRam.flags & SRF_ENABLED), !!(SRam.flags & SRF_EEPROM), SRam.eeprom_type); MVP;
!!(SRam.flags & SRF_ENABLED), !!(SRam.flags & SRF_EEPROM), SRam.eeprom_type); MVP;
sprintf(dstrp, "sram range: %06x-%06x, reg: %02x\n", SRam.start, SRam.end, Pico.m.sram_reg); MVP;
sprintf(dstrp, "pend int: v:%i, h:%i, vdp status: %04x\n", bit(pv->pending_ints,5), bit(pv->pending_ints,4), pv->status); MVP;
sprintf(dstrp, "pal: %i, hw: %02x, frame#: %i, cycles: %i\n", Pico.m.pal, Pico.m.hardware, Pico.m.frame_count, SekCyclesDoneT()); MVP;
sprintf(dstrp, "pal: %i, hw: %02x, frame#: %i, cycles: %i\n", Pico.m.pal, Pico.m.hardware, Pico.m.frame_count, SekCyclesDone()); MVP;
sprintf(dstrp, "M68k: PC: %06x, SR: %04x, irql: %i\n", SekPc, SekSr, SekIrqLevel); MVP;
#if defined(EMU_C68K)
sprintf(dstrp - 1, ", st_flg: %x\n", PicoCpuCM68k.state_flags); MVP;
#endif
for (r = 0; r < 8; r++) {
sprintf(dstrp, "d%i=%08x, a%i=%08x\n", r, SekDar(r), r, SekDar(r+8)); MVP;
}
@ -535,4 +532,35 @@ void pevt_dump(void)
}
#endif
#if defined(CPU_CMP_R) || defined(CPU_CMP_W) || defined(DRC_CMP)
static FILE *tl_f;
void tl_write(const void *ptr, size_t size)
{
if (tl_f == NULL)
tl_f = fopen("tracelog", "wb");
fwrite(ptr, 1, size, tl_f);
}
void tl_write_uint(unsigned char ctl, unsigned int v)
{
tl_write(&ctl, sizeof(ctl));
tl_write(&v, sizeof(v));
}
int tl_read(void *ptr, size_t size)
{
if (tl_f == NULL)
tl_f = fopen("tracelog", "rb");
return fread(ptr, 1, size, tl_f);
}
int tl_read_uint(void *ptr)
{
return tl_read(ptr, 4);
}
#endif
// vim:shiftwidth=2:ts=2:expandtab

20
pico/debug.h
View file

@ -9,3 +9,23 @@ void PDebugDumpMem(void);
void PDebugZ80Frame(void);
void PDebugCPUStep(void);
#if defined(CPU_CMP_R) || defined(CPU_CMP_W) || defined(DRC_CMP)
enum ctl_byte {
CTL_68K_SLAVE = 0x02,
CTL_68K_PC = 0x04,
CTL_68K_SR = 0x05,
CTL_68K_CYCLES = 0x06,
CTL_68K_R = 0x10, // .. 0x20
CTL_MASTERSLAVE = 0x80,
CTL_EA = 0x82,
CTL_EAVAL = 0x83,
CTL_M68KPC = 0x84,
CTL_CYCLES = 0x85,
CTL_SH2_R = 0x90, // .. 0xa8
};
void tl_write(const void *ptr, size_t size);
void tl_write_uint(unsigned char ctl, unsigned int v);
int tl_read(void *ptr, size_t size);
int tl_read_uint(void *ptr);
#endif

6
pico/draw.c
View file

@ -1505,15 +1505,9 @@ void PicoDrawSync(int to, int blank_last_line)
for (line = DrawScanline; line < to; line++)
{
if (line >= 224) break;
PicoLine(line, offs, sh, bgc);
}
if (line >= 224) {
DrawScanline = 240;
return;
}
// last line
if (line <= to)
{

10
pico/eeprom.c
View file

@ -21,7 +21,7 @@ static void EEPROM_write_do(unsigned int d) // ???? ??la (l=SCL, a=SDA)
unsigned int scyc = Pico.m.eeprom_cycle, ssa = Pico.m.eeprom_slave;
elprintf(EL_EEPROM, "eeprom: scl/sda: %i/%i -> %i/%i, newtime=%i", (sreg&2)>>1, sreg&1,
(d&2)>>1, d&1, SekCyclesDoneT() - last_write);
(d&2)>>1, d&1, SekCyclesDone() - last_write);
saddr &= 0x1fff;
if(sreg & d & 2) {
@ -142,17 +142,17 @@ static void EEPROM_upd_pending(unsigned int d)
void EEPROM_write16(unsigned int d)
{
// this diff must be at most 16 for NBA Jam to work
if (SekCyclesDoneT() - last_write < 16) {
if (SekCyclesDone() - last_write < 16) {
// just update pending state
elprintf(EL_EEPROM, "eeprom: skip because cycles=%i",
SekCyclesDoneT() - last_write);
SekCyclesDone() - last_write);
EEPROM_upd_pending(d);
} else {
int srs = Pico.m.eeprom_status;
EEPROM_write_do(srs >> 6); // execute pending
EEPROM_upd_pending(d);
if ((srs ^ Pico.m.eeprom_status) & 0xc0) // update time only if SDA/SCL changed
last_write = SekCyclesDoneT();
last_write = SekCyclesDone();
}
}
@ -172,7 +172,7 @@ unsigned int EEPROM_read(void)
EEPROM_write_do(Pico.m.eeprom_status>>6);
sreg = Pico.m.eeprom_status; saddr = Pico.m.eeprom_addr&0x1fff; scyc = Pico.m.eeprom_cycle; ssa = Pico.m.eeprom_slave;
interval = SekCyclesDoneT() - last_write;
interval = SekCyclesDone() - last_write;
d = (sreg>>6)&1; // use SDA as "open bus"
// NBA Jam is nasty enough to read <before> raising the SCL and starting the new cycle.

8
pico/m68kif_cyclone.s
View file

@ -24,16 +24,18 @@
cyclone_checkpc:
ldr r1, [r7, #0x60] @ membase
sub r0, r0, r1
bic r0, r0, #0xff000000
bics r0, r0, #1
and r3, r0, #0xff000000
bic r0, r0, #1
bics r2, r0, #0xff000000
beq crashed
ldr r1, [r7, #0x6c] @ read16 map
mov r2, r0, lsr #M68K_MEM_SHIFT
mov r2, r2, lsr #M68K_MEM_SHIFT
ldr r1, [r1, r2, lsl #2]
movs r1, r1, lsl #1
bcs crashed
sub r1, r1, r3
str r1, [r7, #0x60] @ membase
add r0, r0, r1
bx lr

4
pico/media.c
View file

@ -212,6 +212,7 @@ enum media_type_e PicoLoadMedia(const char *filename,
Stop_CD();
PicoCartUnload();
PicoAHW = 0;
PicoQuirks = 0;
if (media_type == PM_CD)
{
@ -296,6 +297,9 @@ enum media_type_e PicoLoadMedia(const char *filename,
}
}
if (PicoQuirks & PQUIRK_FORCE_6BTN)
PicoSetInputDevice(0, PICO_INPUT_PAD_6BTN);
out:
if (rom_data)
free(rom_data);

164
pico/memory.c
View file

@ -49,7 +49,7 @@ static void xmap_set(uptr *map, int shift, int start_addr, int end_addr,
for (i = start_addr >> shift; i <= end_addr >> shift; i++) {
map[i] = addr >> 1;
if (is_func)
map[i] |= (uptr)1 << (sizeof(addr) * 8 - 1);
map[i] |= MAP_FLAG;
}
}
@ -126,19 +126,19 @@ void m68k_map_unmap(int start_addr, int end_addr)
addr = (uptr)m68k_unmapped_read8;
for (i = start_addr >> shift; i <= end_addr >> shift; i++)
m68k_read8_map[i] = (addr >> 1) | (1 << 31);
m68k_read8_map[i] = (addr >> 1) | MAP_FLAG;
addr = (uptr)m68k_unmapped_read16;
for (i = start_addr >> shift; i <= end_addr >> shift; i++)
m68k_read16_map[i] = (addr >> 1) | (1 << 31);
m68k_read16_map[i] = (addr >> 1) | MAP_FLAG;
addr = (uptr)m68k_unmapped_write8;
for (i = start_addr >> shift; i <= end_addr >> shift; i++)
m68k_write8_map[i] = (addr >> 1) | (1 << 31);
m68k_write8_map[i] = (addr >> 1) | MAP_FLAG;
addr = (uptr)m68k_unmapped_write16;
for (i = start_addr >> shift; i <= end_addr >> shift; i++)
m68k_write16_map[i] = (addr >> 1) | (1 << 31);
m68k_write16_map[i] = (addr >> 1) | MAP_FLAG;
}
MAKE_68K_READ8(m68k_read8, m68k_read8_map)
@ -186,62 +186,119 @@ void cyclone_crashed(u32 pc, struct Cyclone *context)
// -----------------------------------------------------------------
// memmap helpers
#ifndef _ASM_MEMORY_C
static
#endif
int PadRead(int i)
static u32 read_pad_3btn(int i, u32 out_bits)
{
int pad,value,data_reg;
pad=~PicoPadInt[i]; // Get inverse of pad MXYZ SACB RLDU
data_reg=Pico.ioports[i+1];
u32 pad = ~PicoPadInt[i]; // Get inverse of pad MXYZ SACB RLDU
u32 value;
// orr the bits, which are set as output
value = data_reg&(Pico.ioports[i+4]|0x80);
if (out_bits & 0x40) // TH
value = pad & 0x3f; // ?1CB RLDU
else
value = ((pad & 0xc0) >> 2) | (pad & 3); // ?0SA 00DU
if (PicoOpt & POPT_6BTN_PAD)
{
int phase = Pico.m.padTHPhase[i];
if(phase == 2 && !(data_reg&0x40)) { // TH
value|=(pad&0xc0)>>2; // ?0SA 0000
return value;
} else if(phase == 3) {
if(data_reg&0x40)
value|=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ
else
value|=((pad&0xc0)>>2)|0x0f; // ?0SA 1111
return value;
}
}
if(data_reg&0x40) // TH
value|=(pad&0x3f); // ?1CB RLDU
else value|=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU
return value; // will mirror later
value |= out_bits & 0x40;
return value;
}
#ifndef _ASM_MEMORY_C
static u32 read_pad_6btn(int i, u32 out_bits)
{
u32 pad = ~PicoPadInt[i]; // Get inverse of pad MXYZ SACB RLDU
int phase = Pico.m.padTHPhase[i];
u32 value;
static u32 io_ports_read(u32 a)
if (phase == 2 && !(out_bits & 0x40)) {
value = (pad & 0xc0) >> 2; // ?0SA 0000
goto out;
}
else if(phase == 3) {
if (out_bits & 0x40)
return (pad & 0x30) | ((pad >> 8) & 0xf); // ?1CB MXYZ
else
return ((pad & 0xc0) >> 2) | 0x0f; // ?0SA 1111
goto out;
}
if (out_bits & 0x40) // TH
value = pad & 0x3f; // ?1CB RLDU
else
value = ((pad & 0xc0) >> 2) | (pad & 3); // ?0SA 00DU
out:
value |= out_bits & 0x40;
return value;
}
static u32 read_nothing(int i, u32 out_bits)
{
return 0xff;
}
typedef u32 (port_read_func)(int index, u32 out_bits);
static port_read_func *port_readers[3] = {
read_pad_3btn,
read_pad_3btn,
read_nothing
};
static NOINLINE u32 port_read(int i)
{
u32 data_reg = Pico.ioports[i + 1];
u32 ctrl_reg = Pico.ioports[i + 4] | 0x80;
u32 in, out;
out = data_reg & ctrl_reg;
out |= 0x7f & ~ctrl_reg; // pull-ups
in = port_readers[i](i, out);
return (in & ~ctrl_reg) | (data_reg & ctrl_reg);
}
void PicoSetInputDevice(int port, enum input_device device)
{
port_read_func *func;
if (port < 0 || port > 2)
return;
switch (device) {
case PICO_INPUT_PAD_3BTN:
func = read_pad_3btn;
break;
case PICO_INPUT_PAD_6BTN:
func = read_pad_6btn;
break;
default:
func = read_nothing;
break;
}
port_readers[port] = func;
}
NOINLINE u32 io_ports_read(u32 a)
{
u32 d;
a = (a>>1) & 0xf;
switch (a) {
case 0: d = Pico.m.hardware; break; // Hardware value (Version register)
case 1: d = PadRead(0); break;
case 2: d = PadRead(1); break;
case 1: d = port_read(0); break;
case 2: d = port_read(1); break;
case 3: d = port_read(2); break;
default: d = Pico.ioports[a]; break; // IO ports can be used as RAM
}
return d;
}
static void NOINLINE io_ports_write(u32 a, u32 d)
NOINLINE void io_ports_write(u32 a, u32 d)
{
a = (a>>1) & 0xf;
// 6 button gamepad: if TH went from 0 to 1, gamepad changes state
if (1 <= a && a <= 2 && (PicoOpt & POPT_6BTN_PAD))
if (1 <= a && a <= 2)
{
Pico.m.padDelay[a - 1] = 0;
if (!(Pico.ioports[a] & 0x40) && (d & 0x40))
@ -252,7 +309,12 @@ static void NOINLINE io_ports_write(u32 a, u32 d)
Pico.ioports[a] = d;
}
#endif // _ASM_MEMORY_C
// lame..
static int z80_cycles_from_68k(void)
{
return z80_cycle_aim
+ cycles_68k_to_z80(SekCyclesDone() - last_z80_sync);
}
void NOINLINE ctl_write_z80busreq(u32 d)
{
@ -262,14 +324,13 @@ void NOINLINE ctl_write_z80busreq(u32 d)
{
if (d)
{
z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());
z80_cycle_cnt = z80_cycles_from_68k();
}
else
{
z80stopCycle = SekCyclesDone();
if ((PicoOpt&POPT_EN_Z80) && !Pico.m.z80_reset) {
pprof_start(m68k);
PicoSyncZ80(z80stopCycle);
PicoSyncZ80(SekCyclesDone());
pprof_end_sub(m68k);
}
}
@ -295,7 +356,7 @@ void NOINLINE ctl_write_z80reset(u32 d)
}
else
{
z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());
z80_cycle_cnt = z80_cycles_from_68k();
z80_reset();
}
Pico.m.z80_reset = d;
@ -431,7 +492,7 @@ static void PicoWrite8_z80(u32 a, u32 d)
}
if ((a & 0x4000) == 0x0000) { // z80 RAM
SekCyclesBurn(2); // hack
SekCyclesBurnRun(2); // FIXME hack
Pico.zram[a & 0x1fff] = (u8)d;
return;
}
@ -885,7 +946,7 @@ static int ym2612_write_local(u32 a, u32 d, int is_from_z80)
timer_a_step = TIMER_A_TICK_ZCYCLES * (1024 - TAnew);
if (ym2612.OPN.ST.mode & 1) {
// this is not right, should really be done on overflow only
int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());
int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
timer_a_next_oflow = (cycles << 8) + timer_a_step;
}
elprintf(EL_YMTIMER, "timer a set to %i, %i", 1024 - TAnew, timer_a_next_oflow>>8);
@ -900,7 +961,7 @@ static int ym2612_write_local(u32 a, u32 d, int is_from_z80)
//ym2612.OPN.ST.TBT = 0;
timer_b_step = TIMER_B_TICK_ZCYCLES * (256 - d); // 262800
if (ym2612.OPN.ST.mode & 2) {
int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());
int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
timer_b_next_oflow = (cycles << 8) + timer_b_step;
}
elprintf(EL_YMTIMER, "timer b set to %i, %i", 256 - d, timer_b_next_oflow>>8);
@ -908,7 +969,7 @@ static int ym2612_write_local(u32 a, u32 d, int is_from_z80)
return 0;
case 0x27: { /* mode, timer control */
int old_mode = ym2612.OPN.ST.mode;
int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());
int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
ym2612.OPN.ST.mode = d;
elprintf(EL_YMTIMER, "st mode %02x", d);
@ -986,7 +1047,7 @@ static u32 ym2612_read_local_z80(void)
static u32 ym2612_read_local_68k(void)
{
int xcycles = cycles_68k_to_z80(SekCyclesDone()) << 8;
int xcycles = z80_cycles_from_68k() << 8;
ym2612_read_local();
@ -1177,3 +1238,4 @@ static void z80_mem_setup(void)
#endif
}
// vim:shiftwidth=2:ts=2:expandtab

8
pico/memory.h
View file

@ -26,6 +26,11 @@ extern uptr s68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];
typedef u32 (cpu68k_read_f)(u32 a);
typedef void (cpu68k_write_f)(u32 a, u32 d);
extern u32 m68k_read8(u32 a);
extern u32 m68k_read16(u32 a);
extern void m68k_write8(u32 a, u8 d);
extern void m68k_write16(u32 a, u16 d);
// z80
#define Z80_MEM_SHIFT 13
extern uptr z80_read_map [0x10000 >> Z80_MEM_SHIFT];
@ -40,7 +45,8 @@ void cpu68k_map_set(uptr *map, int start_addr, int end_addr,
void cpu68k_map_all_ram(int start_addr, int end_addr, void *ptr, int is_sub);
void m68k_map_unmap(int start_addr, int end_addr);
#define map_flag_set(x) ((x) & ((uptr)1 << (sizeof(uptr) * 8 - 1)))
#define MAP_FLAG ((uptr)1 << (sizeof(uptr) * 8 - 1))
#define map_flag_set(x) ((x) & MAP_FLAG)
#define MAKE_68K_READ8(name, map) \
u32 name(u32 a) \

56
pico/memory_arm.s
View file

@ -9,7 +9,6 @@
.equ SRR_MAPPED, (1 << 0)
.equ SRR_READONLY, (1 << 1)
.equ SRF_EEPROM, (1 << 1)
.equ POPT_6BTN_PAD, (1 << 5)
.equ POPT_EN_32X, (1 << 20)
.text
@ -67,24 +66,7 @@ m_read8_eeprom:
PicoRead8_io: @ u32 a, u32 d
bic r2, r0, #0x001f @ most commonly we get i/o port read,
cmp r2, #0xa10000 @ so check for it first
bne m_read8_not_io
m_read8_misc_io:
ands r0, r0, #0x1e
beq m_read8_misc_hwreg
cmp r0, #4
movlt r0, #0
moveq r0, #1
ble PadRead
ldr r3, =(Pico+0x22000)
mov r0, r0, lsr #1 @ other IO ports (Pico.ioports[a])
ldrb r0, [r3, r0]
bx lr
m_read8_misc_hwreg:
ldr r3, =(Pico+0x22200)
ldrb r0, [r3, #0x0f] @ Pico.m.hardware
bx lr
beq io_ports_read
m_read8_not_io:
and r2, r0, #0xfc00
@ -161,7 +143,7 @@ PicoRead16_io: @ u32 a, u32 d
cmp r2, #0xa10000 @ so check for it first
bne m_read16_not_io
stmfd sp!,{lr}
bl m_read8_misc_io @ same as read8
bl io_ports_read @ same as read8
orr r0, r0, r0, lsl #8 @ only has bytes mirrored
ldmfd sp!,{pc}
@ -201,37 +183,7 @@ PicoWrite8_io: @ u32 a, u32 d
bic r2, r0, #0x1e @ most commonly we get i/o port write,
eor r2, r2, #0xa10000 @ so check for it first
eors r2, r2, #1
bne m_write8_not_io
m_write8_io:
ldr r2, =PicoOpt
and r0, r0, #0x1e
ldr r2, [r2]
ldr r3, =(Pico+0x22000) @ Pico.ioports
tst r2, #POPT_6BTN_PAD
beq m_write8_io_done
cmp r0, #2
cmpne r0, #4
bne m_write8_io_done @ not likely to happen
add r2, r3, #0x200 @ Pico+0x22200
mov r12,#0
cmp r0, #2
streqb r12,[r2,#0x18]
strneb r12,[r2,#0x19] @ Pico.m.padDelay[i] = 0
tst r1, #0x40 @ TH
beq m_write8_io_done
ldrb r12,[r3, r0, lsr #1]
tst r12,#0x40
bne m_write8_io_done
cmp r0, #2
ldreqb r12,[r2,#0x0a]
ldrneb r12,[r2,#0x0b] @ Pico.m.padTHPhase
add r12,r12,#1
streqb r12,[r2,#0x0a]
strneb r12,[r2,#0x0b] @ Pico.m.padTHPhase
m_write8_io_done:
strb r1, [r3, r0, lsr #1]
bx lr
beq io_ports_write
m_write8_not_io:
tst r0, #1
@ -270,7 +222,7 @@ m_write8_not_sreg:
PicoWrite16_io: @ u32 a, u32 d
bic r2, r0, #0x1f @ most commonly we get i/o port write,
cmp r2, #0xa10000 @ so check for it first
beq m_write8_io
beq io_ports_write
m_write16_not_io:
and r2, r0, #0xff00

26
pico/pico.c
View file

@ -16,6 +16,7 @@ int PicoSkipFrame; // skip rendering frame?
int PicoPad[2]; // Joypads, format is MXYZ SACB RLDU
int PicoPadInt[2]; // internal copy
int PicoAHW; // active addon hardware: PAHW_*
int PicoQuirks; // game-specific quirks
int PicoRegionOverride; // override the region detection 0: Auto, 1: Japan NTSC, 2: Japan PAL, 4: US, 8: Europe
int PicoAutoRgnOrder;
@ -70,6 +71,9 @@ void PicoPower(void)
Pico.video.pending_ints=0;
z80_reset();
// my MD1 VA6 console has this in IO
Pico.ioports[1] = Pico.ioports[2] = Pico.ioports[3] = 0xff;
// default VDP register values (based on Fusion)
Pico.video.reg[0] = Pico.video.reg[1] = 0x04;
Pico.video.reg[0xc] = 0x81;
@ -146,7 +150,7 @@ int PicoReset(void)
if (Pico.romsize <= 0)
return 1;
#ifdef DRC_CMP
#if defined(CPU_CMP_R) || defined(CPU_CMP_W) || defined(DRC_CMP)
PicoOpt |= POPT_DIS_VDP_FIFO|POPT_DIS_IDLE_DET;
#endif
@ -165,11 +169,7 @@ int PicoReset(void)
SekReset();
// s68k doesn't have the TAS quirk, so we just globally set normal TAS handler in MCD mode (used by Batman games).
SekSetRealTAS(PicoAHW & PAHW_MCD);
SekCycleCntT=0;
if (PicoAHW & PAHW_MCD)
// needed for MCD to reset properly, probably some bug hides behind this..
memset(Pico.ioports,0,sizeof(Pico.ioports));
SekCycleCnt = SekCycleAim = 0;
Pico.m.dirtyPal = 1;
@ -274,23 +274,25 @@ PICO_INTERNAL int CheckDMA(void)
#include "pico_cmn.c"
int z80stopCycle;
int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */
unsigned int last_z80_sync; /* in 68k cycles */
int z80_cycle_cnt;
int z80_cycle_aim;
int z80_scanline;
int z80_scanline_cycles; /* cycles done until z80_scanline */
/* sync z80 to 68k */
PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done)
PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done)
{
int cnt;
z80_cycle_aim = cycles_68k_to_z80(m68k_cycles_done);
z80_cycle_aim += cycles_68k_to_z80(m68k_cycles_done - last_z80_sync);
cnt = z80_cycle_aim - z80_cycle_cnt;
last_z80_sync = m68k_cycles_done;
pprof_start(z80);
elprintf(EL_BUSREQ, "z80 sync %i (%i|%i -> %i|%i)", cnt, z80_cycle_cnt, z80_cycle_cnt / 228,
z80_cycle_aim, z80_cycle_aim / 228);
elprintf(EL_BUSREQ, "z80 sync %i (%u|%u -> %u|%u)", cnt,
z80_cycle_cnt, z80_cycle_cnt / 288,
z80_cycle_aim, z80_cycle_aim / 288);
if (cnt > 0)
z80_cycle_cnt += z80_run(cnt);

16
pico/pico.h
View file

@ -52,7 +52,7 @@ extern void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s;
#define POPT_EN_Z80 (1<< 2)
#define POPT_EN_STEREO (1<< 3)
#define POPT_ALT_RENDERER (1<< 4) // 00 00x0
#define POPT_6BTN_PAD (1<< 5)
// unused (1<< 5)
// unused (1<< 6)
#define POPT_ACC_SPRITES (1<< 7)
#define POPT_DIS_32C_BORDER (1<< 8) // 00 0x00
@ -77,6 +77,10 @@ extern int PicoOpt; // bitfield
#define PAHW_PICO (1<<3)
#define PAHW_SMS (1<<4)
extern int PicoAHW; // Pico active hw
#define PQUIRK_FORCE_6BTN (1<<0)
extern int PicoQuirks;
extern int PicoSkipFrame; // skip rendering frame, but still do sound (if enabled) and emulation stuff
extern int PicoRegionOverride; // override the region detection 0: auto, 1: Japan NTSC, 2: Japan PAL, 4: US, 8: Europe
extern int PicoAutoRgnOrder; // packed priority list of regions, for example 0x148 means this detection order: EUR, USA, JAP
@ -95,7 +99,7 @@ typedef enum { PI_ROM, PI_ISPAL, PI_IS40_CELL, PI_IS240_LINES } pint_t;
typedef union { int vint; void *vptr; } pint_ret_t;
void PicoGetInternal(pint_t which, pint_ret_t *ret);
// cd/Pico.c
// cd/mcd.c
extern void (*PicoMCDopenTray)(void);
extern void (*PicoMCDcloseTray)(void);
extern int PicoCDBuffers;
@ -248,6 +252,14 @@ int PicoCdCheck(const char *fname_in, int *pregion);
extern unsigned char media_id_header[0x100];
// memory.c
enum input_device {
PICO_INPUT_NOTHING,
PICO_INPUT_PAD_3BTN,
PICO_INPUT_PAD_6BTN,
};
void PicoSetInputDevice(int port, enum input_device device);
#ifdef __cplusplus
} // End of extern "C"
#endif

130
pico/pico_cmn.c
View file

@ -1,6 +1,6 @@
/*
* common code for pico.c and cd/pico.c
* (C) notaz, 2007-2009
* common code for base/cd/32x
* (C) notaz, 2007-2009,2013
*
* This work is licensed under the terms of MAME license.
* See COPYING file in the top-level directory.
@ -9,55 +9,58 @@
#define CYCLES_M68K_LINE 488 // suitable for both PAL/NTSC
#define CYCLES_M68K_VINT_LAG 68
#define CYCLES_M68K_ASD 148
#define CYCLES_S68K_LINE 795
#define CYCLES_S68K_VINT_LAG 111
#define CYCLES_S68K_ASD 241
// pad delay (for 6 button pads)
#define PAD_DELAY \
if (PicoOpt&POPT_6BTN_PAD) { \
if(Pico.m.padDelay[0]++ > 25) Pico.m.padTHPhase[0]=0; \
if(Pico.m.padDelay[1]++ > 25) Pico.m.padTHPhase[1]=0; \
}
#define PAD_DELAY() { \
if(Pico.m.padDelay[0]++ > 25) Pico.m.padTHPhase[0]=0; \
if(Pico.m.padDelay[1]++ > 25) Pico.m.padTHPhase[1]=0; \
}
// CPUS_RUN
#ifndef CPUS_RUN
#define CPUS_RUN(m68k_cycles,s68k_cycles) \
#define CPUS_RUN(m68k_cycles) \
SekRunM68k(m68k_cycles)
#endif
static __inline void SekRunM68k(int cyc)
// sync m68k to SekCycleAim
static void SekSyncM68k(void)
{
int cyc_do;
pprof_start(m68k);
pevt_log_m68k_o(EVT_RUN_START);
SekCycleAim+=cyc;
if ((cyc_do=SekCycleAim-SekCycleCnt) <= 0)
goto out;
while ((cyc_do = SekCycleAim - SekCycleCnt) > 0) {
SekCycleCnt += cyc_do;
#if defined(EMU_CORE_DEBUG)
// this means we do run-compare
SekCycleCnt+=CM_compareRun(cyc_do, 0);
#elif defined(EMU_C68K)
PicoCpuCM68k.cycles=cyc_do;
CycloneRun(&PicoCpuCM68k);
SekCycleCnt+=cyc_do-PicoCpuCM68k.cycles;
#if defined(EMU_C68K)
PicoCpuCM68k.cycles = cyc_do;
CycloneRun(&PicoCpuCM68k);
SekCycleCnt -= PicoCpuCM68k.cycles;
#elif defined(EMU_M68K)
SekCycleCnt+=m68k_execute(cyc_do);
SekCycleCnt += m68k_execute(cyc_do) - cyc_do;
#elif defined(EMU_F68K)
SekCycleCnt+=fm68k_emulate(cyc_do+1, 0, 0);
SekCycleCnt += fm68k_emulate(cyc_do, 0, 0) - cyc_do;
#endif
}
out:
SekCyclesLeft = 0;
SekTrace(0);
pevt_log_m68k_o(EVT_RUN_END);
pprof_end(m68k);
}
static inline void SekRunM68k(int cyc)
{
SekCycleAim += cyc;
SekSyncM68k();
}
static int PicoFrameHints(void)
{
struct PicoVideo *pv=&Pico.video;
int lines, y, lines_vis = 224, line_sample, skip, vcnt_wrap;
unsigned int cycles;
int hint; // Hint counter
pevt_log_m68k_o(EVT_FRAME_START);
@ -81,11 +84,7 @@ static int PicoFrameHints(void)
line_sample = 93;
}
SekCyclesReset();
z80_resetCycles();
#ifdef PICO_CD
SekCyclesResetS68k();
#endif
PsndDacLine = 0;
emustatus &= ~1;
@ -95,7 +94,7 @@ static int PicoFrameHints(void)
//dprintf("-hint: %i", hint);
// This is to make active scan longer (needed for Double Dragon 2, mainly)
CPUS_RUN(CYCLES_M68K_ASD, CYCLES_S68K_ASD);
CPUS_RUN(CYCLES_M68K_ASD);
for (y = 0; y < lines_vis; y++)
{
@ -113,10 +112,7 @@ static int PicoFrameHints(void)
Pico.video.status|=0x200;
}
PAD_DELAY
#ifdef PICO_CD
check_cd_dma();
#endif
PAD_DELAY();
// H-Interrupts:
if (--hint < 0) // y <= lines_vis: Comix Zone, Golden Axe
@ -124,7 +120,7 @@ static int PicoFrameHints(void)
hint=pv->reg[10]; // Reload H-Int counter
pv->pending_ints|=0x10;
if (pv->reg[0]&0x10) {
elprintf(EL_INTS, "hint: @ %06x [%i]", SekPc, SekCycleCnt);
elprintf(EL_INTS, "hint: @ %06x [%i]", SekPc, SekCyclesDone());
SekInterrupt(4);
}
}
@ -145,25 +141,26 @@ static int PicoFrameHints(void)
// get samples from sound chips
if ((y == 224 || y == line_sample) && PsndOut)
{
cycles = SekCyclesDone();
if (Pico.m.z80Run && !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80))
PicoSyncZ80(SekCycleCnt);
PicoSyncZ80(cycles);
if (ym2612.dacen && PsndDacLine <= y)
PsndDoDAC(y);
#ifdef PICO_CD
pcd_sync_s68k(cycles, 0);
#endif
#ifdef PICO_32X
p32x_sync_sh2s(SekCyclesDoneT2());
p32x_sync_sh2s(cycles);
#endif
PsndGetSamples(y);
}
// Run scanline:
if (Pico.m.dma_xfers) SekCyclesBurn(CheckDMA());
CPUS_RUN(CYCLES_M68K_LINE, CYCLES_S68K_LINE);
CPUS_RUN(CYCLES_M68K_LINE);
#ifdef PICO_CD
update_chips();
#else
if (PicoLineHook) PicoLineHook();
#endif
pevt_log_m68k_o(EVT_NEXT_LINE);
}
@ -186,17 +183,14 @@ static int PicoFrameHints(void)
Pico.video.status|=0x200;
memcpy(PicoPadInt, PicoPad, sizeof(PicoPadInt));
PAD_DELAY
#ifdef PICO_CD
check_cd_dma();
#endif
PAD_DELAY();
// Last H-Int:
if (--hint < 0)
{
hint=pv->reg[10]; // Reload H-Int counter
pv->pending_ints|=0x10;
//printf("rhint: %i @ %06x [%i|%i]\n", hint, SekPc, y, SekCycleCnt);
//printf("rhint: %i @ %06x [%i|%i]\n", hint, SekPc, y, SekCyclesDone());
if (pv->reg[0]&0x10) SekInterrupt(4);
}
@ -207,20 +201,25 @@ static int PicoFrameHints(void)
// there must be a delay after vblank bit is set and irq is asserted (Mazin Saga)
// also delay between F bit (bit 7) is set in SR and IRQ happens (Ex-Mutants)
// also delay between last H-int and V-int (Golden Axe 3)
CPUS_RUN(CYCLES_M68K_VINT_LAG, CYCLES_S68K_VINT_LAG);
CPUS_RUN(CYCLES_M68K_VINT_LAG);
if (pv->reg[1]&0x20) {
elprintf(EL_INTS, "vint: @ %06x [%i]", SekPc, SekCycleCnt);
elprintf(EL_INTS, "vint: @ %06x [%i]", SekPc, SekCyclesDone());
SekInterrupt(6);
}
cycles = SekCyclesDone();
if (Pico.m.z80Run && !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80)) {
PicoSyncZ80(SekCycleCnt);
PicoSyncZ80(cycles);
elprintf(EL_INTS, "zint");
z80_int();
}
#ifdef PICO_CD
pcd_sync_s68k(cycles, 0);
#endif
#ifdef PICO_32X
p32x_sync_sh2s(SekCyclesDoneT2());
p32x_sync_sh2s(cycles);
p32x_start_blank();
#endif
@ -234,14 +233,9 @@ static int PicoFrameHints(void)
// Run scanline:
if (Pico.m.dma_xfers) SekCyclesBurn(CheckDMA());
CPUS_RUN(CYCLES_M68K_LINE - CYCLES_M68K_VINT_LAG - CYCLES_M68K_ASD,
CYCLES_S68K_LINE - CYCLES_S68K_VINT_LAG - CYCLES_S68K_ASD);
CPUS_RUN(CYCLES_M68K_LINE - CYCLES_M68K_VINT_LAG - CYCLES_M68K_ASD);
#ifdef PICO_CD
update_chips();
#else
if (PicoLineHook) PicoLineHook();
#endif
pevt_log_m68k_o(EVT_NEXT_LINE);
lines = scanlines_total;
@ -256,31 +250,28 @@ static int PicoFrameHints(void)
pv->v_counter = (pv->v_counter << 1) | 1;
pv->v_counter &= 0xff;
PAD_DELAY
#ifdef PICO_CD
check_cd_dma();
#endif
PAD_DELAY();
// Run scanline:
if (Pico.m.dma_xfers) SekCyclesBurn(CheckDMA());
CPUS_RUN(CYCLES_M68K_LINE, CYCLES_S68K_LINE);
CPUS_RUN(CYCLES_M68K_LINE);
#ifdef PICO_CD
update_chips();
#else
if (PicoLineHook) PicoLineHook();
#endif
pevt_log_m68k_o(EVT_NEXT_LINE);
}
// sync z80
// sync cpus
cycles = SekCyclesDone();
if (Pico.m.z80Run && !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80))
PicoSyncZ80(Pico.m.pal ? 151809 : 127671); // cycles adjusted for converter
PicoSyncZ80(cycles);
if (PsndOut && ym2612.dacen && PsndDacLine <= lines-1)
PsndDoDAC(lines-1);
#ifdef PICO_CD
pcd_sync_s68k(cycles, 0);
#endif
#ifdef PICO_32X
p32x_sync_sh2s(SekCyclesDoneT2());
p32x_sync_sh2s(cycles);
#endif
timers_cycle();
@ -290,3 +281,4 @@ static int PicoFrameHints(void)
#undef PAD_DELAY
#undef CPUS_RUN
// vim:shiftwidth=2:ts=2:expandtab

232
pico/pico_int.h
View file

@ -37,45 +37,36 @@ extern "C" {
#ifdef EMU_C68K
#include "../cpu/cyclone/Cyclone.h"
extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;
#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run
#define SekCyclesLeft \
(((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)
#define SekCyclesLeftS68k \
((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)
#define SekEndTimeslice(after) PicoCpuCM68k.cycles=after
#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after
#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run
#define SekCyclesLeftS68k PicoCpuCS68k.cycles
#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)
#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)
#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])
#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])
#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])
#define SekSr CycloneGetSr(&PicoCpuCM68k)
#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)
#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }
#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }
#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)
#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)
#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))
#define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))
#define SekInterrupt(i) PicoCpuCM68k.irq=i
#define SekIrqLevel PicoCpuCM68k.irq
#ifdef EMU_M68K
#define EMU_CORE_DEBUG
#endif
#endif
#ifdef EMU_F68K
#include "../cpu/fame/fame.h"
extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;
#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter
#define SekCyclesLeft \
(((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)
#define SekCyclesLeftS68k \
((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)
#define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after
#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after
#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter
#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter
#define SekPc fm68k_get_pc(&PicoCpuFM68k)
#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)
#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)
#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)
#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)
#define SekSr PicoCpuFM68k.sr
#define SekSrS68k PicoCpuFS68k.sr
#define SekSetStop(x) { \
PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \
if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \
@ -86,31 +77,25 @@ extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;
}
#define SekIsStoppedM68k() (PicoCpuFM68k.execinfo&FM68K_HALTED)
#define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)
#define SekShouldInterrupt fm68k_would_interrupt()
#define SekShouldInterrupt() fm68k_would_interrupt()
#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq
#define SekIrqLevel PicoCpuFM68k.interrupts[0]
#ifdef EMU_M68K
#define EMU_CORE_DEBUG
#endif
#endif
#ifdef EMU_M68K
#include "../cpu/musashi/m68kcpu.h"
extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;
#ifndef SekCyclesLeft
#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles
#define SekCyclesLeft \
(((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)
#define SekCyclesLeftS68k \
((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)
#define SekEndTimeslice(after) SET_CYCLES(after)
#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after
#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles
#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles
#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)
#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)
#define SekDar(x) PicoCpuMM68k.dar[x]
#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)
#define SekDar(x) PicoCpuMM68k.dar[x]
#define SekDarS68k(x) PicoCpuMS68k.dar[x]
#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)
#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)
#define SekSetStop(x) { \
if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \
else PicoCpuMM68k.stopped=0; \
@ -121,7 +106,7 @@ extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;
}
#define SekIsStoppedM68k() (PicoCpuMM68k.stopped==STOP_LEVEL_STOP)
#define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)
#define SekShouldInterrupt (CPU_INT_LEVEL > FLAG_INT_MASK)
#define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)
#define SekInterrupt(irq) { \
void *oldcontext = m68ki_cpu_p; \
@ -134,52 +119,50 @@ extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;
#endif
#endif // EMU_M68K
extern int SekCycleCnt; // cycles done in this frame
extern int SekCycleAim; // cycle aim
extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame
// while running, cnt represents target of current timeslice
// while not in SekRun(), it's actual cycles done
// (but always use SekCyclesDone() if you need current position)
// cnt may change if timeslice is ended prematurely or extended,
// so we use SekCycleAim for the actual target
extern unsigned int SekCycleCnt;
extern unsigned int SekCycleAim;
#define SekCyclesReset() { \
SekCycleCntT+=SekCycleAim; \
SekCycleCnt-=SekCycleAim; \
SekCycleAim=0; \
// number of cycles done (can be checked anywhere)
#define SekCyclesDone() (SekCycleCnt - SekCyclesLeft)
// burn cycles while not in SekRun() and while in
#define SekCyclesBurn(c) SekCycleCnt += c
#define SekCyclesBurnRun(c) { \
SekCyclesLeft -= c; \
if (SekCyclesLeft < 0) \
SekCyclesLeft = 0; \
}
#define SekCyclesBurn(c) SekCycleCnt+=c
#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)
#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom
#define SekCyclesDoneT2() (SekCycleCntT + SekCycleCnt) // same as above but not from memhandlers
// note: sometimes may extend timeslice to delay an irq
#define SekEndRun(after) { \
SekCycleCnt -= SekCyclesLeft - (after); \
if (SekCycleCnt < 0) SekCycleCnt = 0; \
SekEndTimeslice(after); \
SekCycleCnt -= SekCyclesLeft - (after); \
SekCyclesLeft = after; \
}
extern unsigned int SekCycleCntS68k;
extern unsigned int SekCycleAimS68k;
#define SekEndRunS68k(after) { \
SekCycleCntS68k -= SekCyclesLeftS68k - (after); \
if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \
SekEndTimesliceS68k(after); \
if (SekCyclesLeftS68k > (after)) { \
SekCycleCntS68k -= SekCyclesLeftS68k - (after); \
SekCyclesLeftS68k = after; \
} \
}
extern int SekCycleCntS68k;
extern int SekCycleAimS68k;
#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)
#define SekCyclesResetS68k() { \
SekCycleCntS68k-=SekCycleAimS68k; \
SekCycleAimS68k=0; \
}
#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)
#ifdef EMU_CORE_DEBUG
extern int dbg_irq_level;
#undef SekEndTimeslice
#undef SekCyclesBurn
#undef SekEndRun
#undef SekInterrupt
#define SekEndTimeslice(c)
#define SekCyclesBurn(c) c
#define SekEndRun(c)
#define SekInterrupt(irq) dbg_irq_level=irq
#endif
// compare cycles, handling overflows
// check if a > b
#define CYCLES_GT(a, b) \
((int)((a) - (b)) > 0)
// check if a >= b
#define CYCLES_GE(a, b) \
((int)((a) - (b)) >= 0)
// ----------------------- Z80 CPU -----------------------
@ -191,6 +174,8 @@ extern struct DrZ80 drZ80;
#define z80_run(cycles) ((cycles) - DrZ80Run(&drZ80, cycles))
#define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)
#define z80_int() drZ80.Z80_IRQ = 1
#define z80_int() drZ80.Z80_IRQ = 1
#define z80_nmi() drZ80.Z80IF |= 8
#define z80_cyclesLeft drZ80.cycles
#define z80_pc() (drZ80.Z80PC - drZ80.Z80PC_BASE)
@ -201,6 +186,7 @@ extern struct DrZ80 drZ80;
#define z80_run(cycles) Cz80_Exec(&CZ80, cycles)
#define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)
#define z80_int() Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)
#define z80_nmi() Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)
#define z80_cyclesLeft (CZ80.ICount - CZ80.ExtraCycles)
#define z80_pc() Cz80_Get_Reg(&CZ80, CZ80_PC)
@ -210,18 +196,20 @@ extern struct DrZ80 drZ80;
#define z80_run(cycles) (cycles)
#define z80_run_nr(cycles)
#define z80_int()
#define z80_nmi()
#endif
#define Z80_STATE_SIZE 0x60
extern int z80stopCycle; /* in 68k cycles */
extern unsigned int last_z80_sync;
extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */
extern int z80_cycle_aim;
extern int z80_scanline;
extern int z80_scanline_cycles; /* cycles done until z80_scanline */
#define z80_resetCycles() \
last_z80_sync = SekCyclesDone(); \
z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;
#define z80_cyclesDone() \
@ -245,6 +233,7 @@ extern SH2 sh2s[2];
} \
} while (0)
# define sh2_cycles_left(sh2) (sh2)->icount
# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n
# define sh2_pc(sh2) (sh2)->ppc
#else
# define sh2_end_run(sh2, after_) do { \
@ -256,6 +245,7 @@ extern SH2 sh2s[2];
} \
} while (0)
# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)
# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)
# define sh2_pc(sh2) (sh2)->pc
#endif
@ -275,6 +265,9 @@ extern SH2 sh2s[2];
#define sh2_set_vbr(c, v) \
{ if (c) ssh2.vbr = v; else msh2.vbr = v; }
#define elprintf_sh2(sh2, w, f, ...) \
elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)
// ---------------------------------------------------------
// main oscillator clock which controls timing
@ -324,7 +317,8 @@ struct PicoMS
{
unsigned char carthw[0x10];
unsigned char io_ctl;
unsigned char pad[0x4f];
unsigned char nmi_state;
unsigned char pad[0x4e];
};
// some assembly stuff depend on these, do not touch!
@ -342,7 +336,7 @@ struct Pico
unsigned short vsram[0x40]; // 0x22180
unsigned char *rom; // 0x22200
unsigned int romsize; // 0x22204
unsigned int romsize; // 0x22204 (on 32bits)
struct PicoMisc m;
struct PicoVideo video;
@ -393,20 +387,24 @@ struct mcd_pcm
} ch[8];
};
#define PCD_ST_S68K_RST 1
struct mcd_misc
{
unsigned short hint_vector;
unsigned char busreq;
unsigned char busreq; // not s68k_regs[1]
unsigned char s68k_pend_ints;
unsigned int state_flags; // 04: emu state: reset_pending
unsigned int counter75hz;
unsigned int pad0;
int timer_int3; // 10
unsigned int timer_stopwatch;
unsigned int state_flags; // 04
unsigned int stopwatch_base_c;
unsigned short m68k_poll_a;
unsigned short m68k_poll_cnt;
unsigned short s68k_poll_a;
unsigned short s68k_poll_cnt;
unsigned int s68k_poll_clk;
unsigned char bcram_reg; // 18: battery-backed RAM cart register
unsigned char pad2;
unsigned char dmna_ret_2m;
unsigned short pad3;
int pad[9];
int pad4[9];
};
typedef struct
@ -430,6 +428,7 @@ typedef struct
unsigned char pcm_ram[0x10000];
unsigned char pcm_ram_b[0x10][0x1000];
};
// FIXME: should be short
unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs
unsigned char bram[0x2000]; // 110200: 8K
struct mcd_misc m; // 112200: misc
@ -471,8 +470,9 @@ typedef struct
#define P32XP_FULL (1<<15) // PWM pulse
#define P32XP_EMPTY (1<<14)
#define P32XF_68KCPOLL (1 << 0)
#define P32XF_68KVPOLL (1 << 1)
#define P32XF_68KCPOLL (1 << 0)
#define P32XF_68KVPOLL (1 << 1)
#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io
#define P32XI_VRES (1 << 14/2) // IRL/2
#define P32XI_VINT (1 << 12/2)
@ -483,8 +483,7 @@ typedef struct
// peripheral reg access
#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]
// real one is 4*2, but we use more because we don't lockstep
#define DMAC_FIFO_LEN (4*4)
#define DMAC_FIFO_LEN (4*2)
#define PWM_BUFF_LEN 1024 // in one channel samples
#define SH2_DRCBLK_RAM_SHIFT 1
@ -505,8 +504,10 @@ struct Pico32x
unsigned char sh2irqi[2]; // individual
unsigned int sh2irqs; // common irqs
unsigned short dmac_fifo[DMAC_FIFO_LEN];
unsigned int pad[4];
unsigned int dmac0_fifo_ptr;
unsigned int pad;
unsigned short vdp_fbcr_fake;
unsigned short pad2;
unsigned char comm_dirty_68k;
unsigned char comm_dirty_sh2;
unsigned char pwm_irq_cnt;
@ -530,12 +531,19 @@ struct Pico32xMem
#ifdef DRC_SH2
unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];
#endif
unsigned char sh2_rom_m[0x800];
unsigned char sh2_rom_s[0x400];
union {
unsigned char b[0x800];
unsigned short w[0x800/2];
} sh2_rom_m;
union {
unsigned char b[0x400];
unsigned short w[0x400/2];
} sh2_rom_s;
unsigned short pal[0x100];
unsigned short pal_native[0x100]; // converted to native (for renderer)
signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame
signed short pwm_fifo[2][4]; // [0] - current, others - fifo entries
signed short pwm_current[2]; // current converted samples
unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries
};
// area.c
@ -586,14 +594,13 @@ unsigned int PicoRead8_io(unsigned int a);
unsigned int PicoRead16_io(unsigned int a);
void PicoWrite8_io(unsigned int a, unsigned int d);
void PicoWrite16_io(unsigned int a, unsigned int d);
void p32x_dreq1_trigger(void);
// pico/memory.c
PICO_INTERNAL void PicoMemSetupPico(void);
// cd/memory.c
PICO_INTERNAL void PicoMemSetupCD(void);
void PicoMemStateLoaded(void);
void pcd_state_loaded_mem(void);
// pico.c
extern struct Pico Pico;
@ -605,15 +612,36 @@ extern void (*PicoResetHook)(void);
extern void (*PicoLineHook)(void);
PICO_INTERNAL int CheckDMA(void);
PICO_INTERNAL void PicoDetectRegion(void);
PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);
PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);
// cd/mcd.c
#define PCDS_IEN1 (1<<1)
#define PCDS_IEN2 (1<<2)
#define PCDS_IEN3 (1<<3)
#define PCDS_IEN4 (1<<4)
#define PCDS_IEN5 (1<<5)
#define PCDS_IEN6 (1<<6)
// cd/pico.c
PICO_INTERNAL void PicoInitMCD(void);
PICO_INTERNAL void PicoExitMCD(void);
PICO_INTERNAL void PicoPowerMCD(void);
PICO_INTERNAL int PicoResetMCD(void);
PICO_INTERNAL void PicoFrameMCD(void);
enum pcd_event {
PCD_EVENT_CDC,
PCD_EVENT_TIMER3,
PCD_EVENT_GFX,
PCD_EVENT_DMA,
PCD_EVENT_COUNT,
};
extern unsigned int pcd_event_times[PCD_EVENT_COUNT];
void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);
void pcd_event_schedule_s68k(enum pcd_event event, int after);
unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);
int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);
void pcd_state_loaded(void);
// pico/pico.c
PICO_INTERNAL void PicoInitPico(void);
PICO_INTERNAL void PicoReratePico(void);
@ -633,6 +661,11 @@ PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub);
void SekStepM68k(void);
void SekInitIdleDet(void);
void SekFinishIdleDet(void);
#if defined(CPU_CMP_R) || defined(CPU_CMP_W)
void SekTrace(int is_s68k);
#else
#define SekTrace(x)
#endif
// cd/sek.c
PICO_INTERNAL void SekInitS68k(void);
@ -732,9 +765,10 @@ extern struct Pico32x Pico32x;
enum p32x_event {
P32X_EVENT_PWM,
P32X_EVENT_FILLEND,
P32X_EVENT_HINT,
P32X_EVENT_COUNT,
};
extern unsigned int event_times[P32X_EVENT_COUNT];
extern unsigned int p32x_event_times[P32X_EVENT_COUNT];
void Pico32xInit(void);
void PicoPower32x(void);
@ -746,9 +780,12 @@ void Pico32xStateLoaded(int is_early);
void p32x_sync_sh2s(unsigned int m68k_target);
void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);
void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);
void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);
void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);
void p32x_reset_sh2s(void);
void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);
void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);
void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);
// 32x/memory.c
struct Pico32xMem *Pico32xMem;
@ -785,6 +822,7 @@ void p32x_pwm_update(int *buf32, int length, int stereo);
void p32x_pwm_ctl_changed(void);
void p32x_pwm_schedule(unsigned int m68k_now);
void p32x_pwm_schedule_sh2(SH2 *sh2);
void p32x_pwm_sync_to_sh2(SH2 *sh2);
void p32x_pwm_irq_event(unsigned int m68k_now);
void p32x_pwm_state_loaded(void);
@ -793,6 +831,7 @@ void p32x_dreq0_trigger(void);
void p32x_dreq1_trigger(void);
void p32x_timers_recalc(void);
void p32x_timers_do(unsigned int m68k_slice);
void sh2_peripheral_reset(SH2 *sh2);
unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);
unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);
unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);
@ -853,6 +892,7 @@ static __inline int isspace_(int c)
#define EL_32X 0x00080000
#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */
#define EL_32XP 0x00200000 /* 32X peripherals */
#define EL_CD 0x00400000 /* MCD */
#define EL_STATUS 0x40000000 /* status messages */
#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */
@ -903,9 +943,9 @@ void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);
void pevt_dump(void);
#define pevt_log_m68k(e) \
pevt_log(SekCyclesDoneT(), EVT_M68K, e)
pevt_log(SekCyclesDone(), EVT_M68K, e)
#define pevt_log_m68k_o(e) \
pevt_log(SekCyclesDoneT2(), EVT_M68K, e)
pevt_log(SekCyclesDone(), EVT_M68K, e)
#define pevt_log_sh2(sh2, e) \
pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)
#define pevt_log_sh2_o(sh2, e) \

158
pico/sek.c
View file

@ -11,9 +11,8 @@
#include "memory.h"
int SekCycleCnt=0; // cycles done in this frame
int SekCycleAim=0; // cycle aim
unsigned int SekCycleCntT=0;
unsigned int SekCycleCnt;
unsigned int SekCycleAim;
/* context */
@ -220,7 +219,8 @@ PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub)
#endif
*(unsigned int *)(cpu+0x40) = pc;
*(unsigned int *)(cpu+0x50) = SekCycleCntT;
*(unsigned int *)(cpu+0x50) =
is_sub ? SekCycleCntS68k : SekCycleCnt;
}
PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub)
@ -257,7 +257,10 @@ PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub)
context->execinfo &= ~FM68K_HALTED;
if (cpu[0x4d]&1) context->execinfo |= FM68K_HALTED;
#endif
SekCycleCntT = *(unsigned int *)(cpu+0x50);
if (is_sub)
SekCycleCntS68k = *(unsigned int *)(cpu+0x50);
else
SekCycleCnt = *(unsigned int *)(cpu+0x50);
}
@ -268,7 +271,7 @@ PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub)
static unsigned short **idledet_ptrs = NULL;
static int idledet_count = 0, idledet_bads = 0;
int idledet_start_frame = 0;
static int idledet_start_frame = 0;
#if 0
#define IDLE_STATS 1
@ -312,6 +315,11 @@ void SekInitIdleDet(void)
#endif
}
int SekIsIdleReady(void)
{
return (Pico.m.frame_count >= idledet_start_frame);
}
int SekIsIdleCode(unsigned short *dst, int bytes)
{
// printf("SekIsIdleCode %04x %i\n", *dst, bytes);
@ -322,11 +330,16 @@ int SekIsIdleCode(unsigned short *dst, int bytes)
return 1;
break;
case 4:
if ( (*dst & 0xfff8) == 0x4a10 || // tst.b ($aX) // there should be no need to wait
(*dst & 0xfff8) == 0x4a28 || // tst.b ($xxxx,a0) // for byte change anywhere
(*dst & 0xff3f) == 0x4a38 || // tst.x ($xxxx.w); tas ($xxxx.w)
(*dst & 0xc1ff) == 0x0038 || // move.x ($xxxx.w), dX
(*dst & 0xf13f) == 0xb038) // cmp.x ($xxxx.w), dX
if ( (*dst & 0xff3f) == 0x4a38 || // tst.x ($xxxx.w); tas ($xxxx.w)
(*dst & 0xc1ff) == 0x0038 || // move.x ($xxxx.w), dX
(*dst & 0xf13f) == 0xb038) // cmp.x ($xxxx.w), dX
return 1;
if (PicoAHW & (PAHW_MCD|PAHW_32X))
break;
// with no addons, there should be no need to wait
// for byte change anywhere
if ( (*dst & 0xfff8) == 0x4a10 || // tst.b ($aX)
(*dst & 0xfff8) == 0x4a28) // tst.b ($xxxx,a0)
return 1;
break;
case 6:
@ -348,7 +361,9 @@ int SekIsIdleCode(unsigned short *dst, int bytes)
return 1;
break;
case 12:
if ((*dst & 0xf1f8) == 0x3010 && // move.w (aX), dX
if (PicoAHW & (PAHW_MCD|PAHW_32X))
break;
if ( (*dst & 0xf1f8) == 0x3010 && // move.w (aX), dX
(dst[1]&0xf100) == 0x0000 && // arithmetic
(dst[3]&0xf100) == 0x0000) // arithmetic
return 1;
@ -372,6 +387,7 @@ int SekRegisterIdlePatch(unsigned int pc, int oldop, int newop, void *ctx)
is_main68k = ctx == &PicoCpuFM68k;
#endif
pc &= ~0xff000000;
if (!(newop&0x200))
elprintf(EL_IDLE, "idle: patch %06x %04x %04x %c %c #%i", pc, oldop, newop,
(newop&0x200)?'n':'y', is_main68k?'m':'s', idledet_count);
@ -420,6 +436,122 @@ void SekFinishIdleDet(void)
}
#if defined(CPU_CMP_R) || defined(CPU_CMP_W)
#include "debug.h"
struct ref_68k {
u32 dar[16];
u32 pc;
u32 sr;
u32 cycles;
u32 pc_prev;
};
struct ref_68k ref_68ks[2];
static int current_68k;
void SekTrace(int is_s68k)
{
struct ref_68k *x68k = &ref_68ks[is_s68k];
u32 pc = is_s68k ? SekPcS68k : SekPc;
u32 sr = is_s68k ? SekSrS68k : SekSr;
u32 cycles = is_s68k ? SekCycleCntS68k : SekCycleCnt;
u32 r;
u8 cmd;
#ifdef CPU_CMP_W
int i;
if (is_s68k != current_68k) {
current_68k = is_s68k;
cmd = CTL_68K_SLAVE | current_68k;
tl_write(&cmd, sizeof(cmd));
}
if (pc != x68k->pc) {
x68k->pc = pc;
tl_write_uint(CTL_68K_PC, x68k->pc);
}
if (sr != x68k->sr) {
x68k->sr = sr;
tl_write_uint(CTL_68K_SR, x68k->sr);
}
for (i = 0; i < 16; i++) {
r = is_s68k ? SekDarS68k(i) : SekDar(i);
if (r != x68k->dar[i]) {
x68k->dar[i] = r;
tl_write_uint(CTL_68K_R + i, r);
}
}
tl_write_uint(CTL_68K_CYCLES, cycles);
#else
int i, bad = 0;
while (1)
{
int ret = tl_read(&cmd, sizeof(cmd));
if (ret == 0) {
elprintf(EL_STATUS, "EOF");
exit(1);
}
switch (cmd) {
case CTL_68K_SLAVE:
case CTL_68K_SLAVE + 1:
current_68k = cmd & 1;
break;
case CTL_68K_PC:
tl_read_uint(&x68k->pc);
break;
case CTL_68K_SR:
tl_read_uint(&x68k->sr);
break;
case CTL_68K_CYCLES:
tl_read_uint(&x68k->cycles);
goto breakloop;
default:
if (CTL_68K_R <= cmd && cmd < CTL_68K_R + 0x10)
tl_read_uint(&x68k->dar[cmd - CTL_68K_R]);
else
elprintf(EL_STATUS, "invalid cmd: %02x", cmd);
}
}
breakloop:
if (is_s68k != current_68k) {
printf("bad 68k: %d %d\n", is_s68k, current_68k);
bad = 1;
}
if (cycles != x68k->cycles) {
printf("bad cycles: %u %u\n", cycles, x68k->cycles);
bad = 1;
}
if ((pc ^ x68k->pc) & 0xffffff) {
printf("bad PC: %08x %08x\n", pc, x68k->pc);
bad = 1;
}
if (sr != x68k->sr) {
printf("bad SR: %03x %03x\n", sr, x68k->sr);
bad = 1;
}
for (i = 0; i < 16; i++) {
r = is_s68k ? SekDarS68k(i) : SekDar(i);
if (r != x68k->dar[i]) {
printf("bad %c%d: %08x %08x\n", i < 8 ? 'D' : 'A', i & 7,
r, x68k->dar[i]);
bad = 1;
}
}
if (bad) {
for (i = 0; i < 8; i++)
printf("D%d: %08x A%d: %08x\n", i, x68k->dar[i],
i, x68k->dar[i + 8]);
printf("PC: %08x, %08x\n", x68k->pc, x68k->pc_prev);
PDebugDumpMem();
exit(1);
}
x68k->pc_prev = x68k->pc;
#endif
}
#endif // CPU_CMP_*
#if defined(EMU_M68K) && M68K_INSTRUCTION_HOOK == OPT_SPECIFY_HANDLER
static unsigned char op_flags[0x400000/2] = { 0, };
static int atexit_set = 0;
@ -447,3 +579,5 @@ void instruction_hook(void)
op_flags[REG_PC/2] = 1;
}
#endif
// vim:shiftwidth=2:ts=2:expandtab

7
pico/sms.c
View file

@ -11,7 +11,6 @@
* - remaining status flags (OVR/COL)
* - RAM support in mapper
* - region support
* - Pause button (NMI)
* - SN76496 DAC-like usage
* - H counter
*/
@ -256,8 +255,14 @@ void PicoFrameMS(void)
int skip = PicoSkipFrame;
int lines_vis = 192;
int hint; // Hint counter
int nmi;
int y;
nmi = (PicoPad[0] >> 7) & 1;
if (!Pico.ms.nmi_state && nmi)
z80_nmi();
Pico.ms.nmi_state = nmi;
PicoFrameStartMode4();
hint = pv->reg[0x0a];

45
pico/state.c
View file

@ -173,12 +173,14 @@ typedef enum {
CHUNK_32X_EVT,
CHUNK_32X_FIRST = CHUNK_MSH2,
CHUNK_32X_LAST = CHUNK_32X_EVT,
// add new stuff here
CHUNK_CD_EVT = 50,
//
CHUNK_DEFAULT_COUNT,
CHUNK_CARTHW_ = CHUNK_CARTHW, // defined in PicoInt
CHUNK_CARTHW_ = CHUNK_CARTHW, // 64 (defined in PicoInt)
} chunk_name_e;
static const char * const chunk_names[] = {
static const char * const chunk_names[CHUNK_DEFAULT_COUNT] = {
"INVALID!",
"M68K state",
"RAM",
@ -235,7 +237,7 @@ static int write_chunk(chunk_name_e name, int len, void *data, void *file)
}
#define CHECKED_WRITE(name,len,data) { \
if (PicoStateProgressCB && name < CHUNK_DEFAULT_COUNT) { \
if (PicoStateProgressCB && name < CHUNK_DEFAULT_COUNT && chunk_names[name]) { \
strncpy(sbuff + 9, chunk_names[name], sizeof(sbuff) - 9); \
PicoStateProgressCB(sbuff); \
} \
@ -243,7 +245,7 @@ static int write_chunk(chunk_name_e name, int len, void *data, void *file)
}
#define CHECKED_WRITE_BUFF(name,buff) { \
if (PicoStateProgressCB && name < CHUNK_DEFAULT_COUNT) { \
if (PicoStateProgressCB && name < CHUNK_DEFAULT_COUNT && chunk_names[name]) { \
strncpy(sbuff + 9, chunk_names[name], sizeof(sbuff) - 9); \
PicoStateProgressCB(sbuff); \
} \
@ -290,7 +292,8 @@ static int state_save(void *file)
SekPackCpu(buff, 1);
if (Pico_mcd->s68k_regs[3] & 4) // 1M mode?
wram_1M_to_2M(Pico_mcd->word_ram2M);
Pico_mcd->m.hint_vector = *(unsigned short *)(Pico_mcd->bios + 0x72);
memcpy(&Pico_mcd->m.hint_vector, Pico_mcd->bios + 0x72,
sizeof(Pico_mcd->m.hint_vector));
CHECKED_WRITE_BUFF(CHUNK_S68K, buff);
CHECKED_WRITE_BUFF(CHUNK_PRG_RAM, Pico_mcd->prg_ram);
@ -304,6 +307,9 @@ static int state_save(void *file)
CHECKED_WRITE_BUFF(CHUNK_SCD, Pico_mcd->scd);
CHECKED_WRITE_BUFF(CHUNK_RC, Pico_mcd->rot_comp);
CHECKED_WRITE_BUFF(CHUNK_MISC_CD, Pico_mcd->m);
memset(buff, 0, 0x40);
memcpy(buff, pcd_event_times, sizeof(pcd_event_times));
CHECKED_WRITE(CHUNK_CD_EVT, 0x40, buff);
if (Pico_mcd->s68k_regs[3] & 4) // convert back
wram_2M_to_1M(Pico_mcd->word_ram2M);
@ -335,7 +341,7 @@ static int state_save(void *file)
CHECKED_WRITE_BUFF(CHUNK_32XPAL, Pico32xMem->pal);
memset(buff, 0, 0x40);
memcpy(buff, event_times, sizeof(event_times));
memcpy(buff, p32x_event_times, sizeof(p32x_event_times));
CHECKED_WRITE(CHUNK_32X_EVT, 0x40, buff);
}
#endif
@ -402,6 +408,9 @@ static int state_load(void *file)
R_ERROR_RETURN("bad header");
CHECKED_READ(4, &ver);
memset(pcd_event_times, 0, sizeof(pcd_event_times));
memset(p32x_event_times, 0, sizeof(p32x_event_times));
while (!areaEof(file))
{
CHECKED_READ(1, &chunk);
@ -458,6 +467,11 @@ static int state_load(void *file)
case CHUNK_RC: CHECKED_READ_BUFF(Pico_mcd->rot_comp); break;
case CHUNK_MISC_CD: CHECKED_READ_BUFF(Pico_mcd->m); break;
case CHUNK_CD_EVT:
CHECKED_READ_BUFF(buff);
memcpy(pcd_event_times, buff, sizeof(pcd_event_times));
break;
// 32x stuff
#ifndef NO_32X
case CHUNK_MSH2:
@ -484,7 +498,7 @@ static int state_load(void *file)
case CHUNK_32X_EVT:
CHECKED_READ_BUFF(buff);
memcpy(event_times, buff, sizeof(event_times));
memcpy(p32x_event_times, buff, sizeof(p32x_event_times));
break;
#endif
default:
@ -509,14 +523,6 @@ readend:
if (PicoAHW & PAHW_SMS)
PicoStateLoadedMS();
if (PicoAHW & PAHW_MCD)
{
PicoMemStateLoaded();
if (!(Pico_mcd->s68k_regs[0x36] & 1) && (Pico_mcd->scd.Status_CDC & 1))
cdda_start_play();
}
if (PicoAHW & PAHW_32X)
Pico32xStateLoaded(1);
@ -529,8 +535,17 @@ readend:
z80_unpack(buff_z80);
// due to dep from 68k cycles..
SekCycleAim = SekCycleCnt;
if (PicoAHW & PAHW_32X)
Pico32xStateLoaded(0);
if (PicoAHW & PAHW_MCD)
{
SekCycleAimS68k = SekCycleCntS68k;
pcd_state_loaded();
if (!(Pico_mcd->s68k_regs[0x36] & 1) && (Pico_mcd->scd.Status_CDC & 1))
cdda_start_play();
}
return 0;
}

8
pico/videoport.c
View file

@ -93,8 +93,7 @@ static void DmaSlow(int len)
SekCyclesDone(), SekPc);
Pico.m.dma_xfers += len;
if ((PicoAHW & PAHW_MCD) && (PicoOpt & POPT_EN_MCD_PSYNC)) SekCyclesBurn(CheckDMA());
else SekEndTimeslice(SekCyclesLeftNoMCD - CheckDMA());
SekCyclesBurnRun(CheckDMA());
if ((source&0xe00000)==0xe00000) { // Ram
pd=(u16 *)(Pico.ram+(source&0xfffe));
@ -362,8 +361,7 @@ PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d)
pvid->lwrite_cnt++;
if (pvid->lwrite_cnt >= 4) pvid->status|=0x100; // FIFO full
if (pvid->lwrite_cnt > 4) {
SekCyclesBurn(32); // penalty // 488/12-8
if (SekCycleCnt>=SekCycleAim) SekEndRun(0);
SekCyclesBurnRun(32); // penalty // 488/12-8
}
elprintf(EL_ASVDP, "VDP data write: %04x [%06x] {%i} #%i @ %06x", d, Pico.video.addr,
Pico.video.type, pvid->lwrite_cnt, SekPc);
@ -425,7 +423,7 @@ PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d)
update_irq:
#ifndef EMU_CORE_DEBUG
// update IRQ level
if (!SekShouldInterrupt) // hack
if (!SekShouldInterrupt()) // hack
{
int lines, pints, irq=0;
lines = (pvid->reg[1] & 0x20) | (pvid->reg[0] & 0x10);