mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
Merge branch 'dev'
This commit is contained in:
notaz
commit
9a1f192a14
89 changed files with 3226 additions and 4002 deletions
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@ -73,7 +73,7 @@ static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan)
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{
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chan->chcr |= DMA_TE; // DMA has ended normally
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p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDoneT());
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p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDone());
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if (chan->chcr & DMA_IE)
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dmac_te_irq(sh2, chan);
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}
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@ -128,7 +128,7 @@ static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan)
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// DMA trigger by SH2 register write
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static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
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{
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elprintf(EL_32XP, "sh2 DMA %08x->%08x, cnt %d, chcr %04x @%06x",
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elprintf_sh2(sh2, EL_32XP, "DMA %08x->%08x, cnt %d, chcr %04x @%06x",
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chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
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chan->tcr &= 0xffffff;
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@ -142,7 +142,7 @@ static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
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// DREQ0 is only sent after first 4 words are written.
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// we do multiple of 4 words to avoid messing up alignment
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if (chan->sar == 0x20004012) {
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if ((chan->sar & ~0x20000000) == 0x00004012) {
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if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) {
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elprintf(EL_32XP, "68k -> sh2 DMA");
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p32x_dreq0_trigger();
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@ -150,6 +150,10 @@ static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
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return;
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}
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// DREQ1
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if ((chan->dar & 0xc7fffff0) == 0x00004030)
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return;
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elprintf(EL_32XP|EL_ANOMALY, "unhandled DMA: "
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"%08x->%08x, cnt %d, chcr %04x @%06x",
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chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
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@ -207,6 +211,16 @@ void p32x_timers_do(unsigned int m68k_slice)
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}
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}
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void sh2_peripheral_reset(SH2 *sh2)
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{
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memset(sh2->peri_regs, 0, sizeof(sh2->peri_regs)); // ?
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PREG8(sh2->peri_regs, 0x001) = 0xff; // SCI BRR
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PREG8(sh2->peri_regs, 0x003) = 0xff; // SCI TDR
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PREG8(sh2->peri_regs, 0x004) = 0x84; // SCI SSR
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PREG8(sh2->peri_regs, 0x011) = 0x01; // TIER
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PREG8(sh2->peri_regs, 0x017) = 0xe0; // TOCR
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}
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// ------------------------------------------------------------------
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// SH2 internal peripheral memhandlers
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// we keep them in little endian format
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@ -219,8 +233,8 @@ u32 sh2_peripheral_read8(u32 a, SH2 *sh2)
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a &= 0x1ff;
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d = PREG8(r, a);
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elprintf(EL_32XP, "%csh2 peri r8 [%08x] %02x @%06x",
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sh2->is_slave ? 's' : 'm', a | ~0x1ff, d, sh2_pc(sh2));
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elprintf_sh2(sh2, EL_32XP, "peri r8 [%08x] %02x @%06x",
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a | ~0x1ff, d, sh2_pc(sh2));
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return d;
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}
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@ -232,8 +246,8 @@ u32 sh2_peripheral_read16(u32 a, SH2 *sh2)
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a &= 0x1ff;
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d = r[(a / 2) ^ 1];
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elprintf(EL_32XP, "%csh2 peri r16 [%08x] %04x @%06x",
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sh2->is_slave ? 's' : 'm', a | ~0x1ff, d, sh2_pc(sh2));
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elprintf_sh2(sh2, EL_32XP, "peri r16 [%08x] %04x @%06x",
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a | ~0x1ff, d, sh2_pc(sh2));
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return d;
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}
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@ -243,40 +257,90 @@ u32 sh2_peripheral_read32(u32 a, SH2 *sh2)
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a &= 0x1fc;
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d = sh2->peri_regs[a / 4];
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elprintf(EL_32XP, "%csh2 peri r32 [%08x] %08x @%06x",
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sh2->is_slave ? 's' : 'm', a | ~0x1ff, d, sh2_pc(sh2));
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elprintf_sh2(sh2, EL_32XP, "peri r32 [%08x] %08x @%06x",
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a | ~0x1ff, d, sh2_pc(sh2));
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return d;
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}
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static void sci_trigger(SH2 *sh2, u8 *r)
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{
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u8 *oregs;
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if (!(PREG8(r, 2) & 0x20))
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return; // transmitter not enabled
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if ((PREG8(r, 4) & 0x80)) // TDRE - TransmitDataR Empty
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return;
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oregs = (u8 *)sh2->other_sh2->peri_regs;
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if (!(PREG8(oregs, 2) & 0x10))
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return; // receiver not enabled
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PREG8(oregs, 5) = PREG8(r, 3); // other.RDR = this.TDR
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PREG8(r, 4) |= 0x80; // TDRE - TDR empty
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PREG8(oregs, 4) |= 0x40; // RDRF - RDR Full
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// might need to delay these a bit..
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if (PREG8(r, 2) & 0x80) { // TIE - tx irq enabled
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int level = PREG8(oregs, 0x60) >> 4;
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int vector = PREG8(oregs, 0x64) & 0x7f;
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elprintf_sh2(sh2, EL_32XP, "SCI tx irq (%d, %d)",
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level, vector);
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sh2_internal_irq(sh2, level, vector);
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}
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// TODO: TEIE
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if (PREG8(oregs, 2) & 0x40) { // RIE - rx irq enabled
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int level = PREG8(oregs, 0x60) >> 4;
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int vector = PREG8(oregs, 0x63) & 0x7f;
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elprintf_sh2(sh2->other_sh2, EL_32XP, "SCI rx irq (%d, %d)",
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level, vector);
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sh2_internal_irq(sh2->other_sh2, level, vector);
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}
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}
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void REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, SH2 *sh2)
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{
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u8 *r = (void *)sh2->peri_regs;
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elprintf(EL_32XP, "%csh2 peri w8 [%08x] %02x @%06x",
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sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
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u8 old;
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elprintf_sh2(sh2, EL_32XP, "peri w8 [%08x] %02x @%06x",
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a, d, sh2_pc(sh2));
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a &= 0x1ff;
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PREG8(r, a) = d;
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old = PREG8(r, a);
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// X-men SCI hack
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if ((a == 2 && (d & 0x20)) || // transmiter enabled
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(a == 4 && !(d & 0x80))) { // valid data in TDR
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void *oregs = sh2->other_sh2->peri_regs;
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if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
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int level = PREG8(oregs, 0x60) >> 4;
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int vector = PREG8(oregs, 0x63) & 0x7f;
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elprintf(EL_32XP, "%csh2 SCI recv irq (%d, %d)",
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(sh2->is_slave ^ 1) ? 's' : 'm', level, vector);
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sh2_internal_irq(sh2->other_sh2, level, vector);
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return;
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switch (a) {
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case 0x002: // SCR - serial control
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if (!(PREG8(r, a) & 0x20) && (d & 0x20)) { // TE being set
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PREG8(r, a) = d;
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sci_trigger(sh2, r);
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}
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break;
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case 0x003: // TDR - transmit data
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break;
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case 0x004: // SSR - serial status
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d = (old & (d | 0x06)) | (d & 1);
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PREG8(r, a) = d;
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sci_trigger(sh2, r);
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return;
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case 0x005: // RDR - receive data
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break;
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case 0x010: // TIER
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if (d & 0x8e)
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elprintf(EL_32XP|EL_ANOMALY, "TIER: %02x", d);
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d = (d & 0x8e) | 1;
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break;
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case 0x017: // TOCR
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d |= 0xe0;
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break;
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}
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PREG8(r, a) = d;
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}
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void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
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{
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u16 *r = (void *)sh2->peri_regs;
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elprintf(EL_32XP, "%csh2 peri w16 [%08x] %04x @%06x",
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sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
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elprintf_sh2(sh2, EL_32XP, "peri w16 [%08x] %04x @%06x",
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a, d, sh2_pc(sh2));
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a &= 0x1ff;
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@ -297,17 +361,20 @@ void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
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void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
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{
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u32 *r = sh2->peri_regs;
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elprintf(EL_32XP, "%csh2 peri w32 [%08x] %08x @%06x",
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sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
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u32 old;
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elprintf_sh2(sh2, EL_32XP, "peri w32 [%08x] %08x @%06x",
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a, d, sh2_pc(sh2));
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a &= 0x1fc;
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old = r[a / 4];
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r[a / 4] = d;
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switch (a) {
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// division unit (TODO: verify):
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case 0x104: // DVDNT: divident L, starts divide
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elprintf(EL_32XP, "%csh2 divide %08x / %08x",
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sh2->is_slave ? 's' : 'm', d, r[0x100 / 4]);
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elprintf_sh2(sh2, EL_32XP, "divide %08x / %08x",
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d, r[0x100 / 4]);
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if (r[0x100 / 4]) {
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signed int divisor = r[0x100 / 4];
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r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
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@ -317,8 +384,8 @@ void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
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r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
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break;
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case 0x114:
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elprintf(EL_32XP, "%csh2 divide %08x%08x / %08x @%08x",
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sh2->is_slave ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(sh2));
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elprintf_sh2(sh2, EL_32XP, "divide %08x%08x / %08x @%08x",
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r[0x110 / 4], d, r[0x100 / 4], sh2_pc(sh2));
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if (r[0x100 / 4]) {
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signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
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signed int divisor = r[0x100 / 4];
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@ -328,8 +395,7 @@ void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
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r[0x11c / 4] = r[0x114 / 4] = divident;
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divident >>= 31;
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if ((unsigned long long)divident + 1 > 1) {
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//elprintf(EL_32XP, "%csh2 divide overflow! @%08x",
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// sh2->is_slave ? 's' : 'm', sh2_pc(sh2));
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//elprintf_sh2(sh2, EL_32XP, "divide overflow! @%08x", sh2_pc(sh2));
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r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
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}
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}
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@ -341,6 +407,8 @@ void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
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// perhaps starting a DMA?
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if (a == 0x1b0 || a == 0x18c || a == 0x19c) {
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struct dmac *dmac = (void *)&sh2->peri_regs[0x180 / 4];
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if (a == 0x1b0 && !((old ^ d) & d & DMA_DME))
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return;
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if (!(dmac->dmaor & DMA_DME))
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return;
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@ -354,29 +422,28 @@ void REGPARM(3) sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
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/* 32X specific */
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static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
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{
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unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
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unsigned short dreqlen = Pico32x.regs[0x10 / 2];
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int i;
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// debug/sanity checks
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if (chan->tcr != *dreqlen)
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elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0 and len differ: %d != %d",
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chan->tcr, *dreqlen);
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if (chan->tcr < dreqlen || chan->tcr > dreqlen + 4)
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elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0/len inconsistent: %d/%d",
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chan->tcr, dreqlen);
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// note: DACK is not connected, single addr mode should not be used
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if ((chan->chcr & 0x3f08) != 0x0400)
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elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr);
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if (chan->sar != 0x20004012)
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elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad sar?: %08x\n", chan->sar);
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if ((chan->sar & ~0x20000000) != 0x00004012)
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elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad sar?: %08x", chan->sar);
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// HACK: assume bus is busy and SH2 is halted
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sh2->state |= SH2_STATE_SLEEP;
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for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) {
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elprintf(EL_32XP, "dmaw [%08x] %04x, left %d",
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chan->dar, Pico32x.dmac_fifo[i], *dreqlen);
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elprintf_sh2(sh2, EL_32XP, "dreq0 [%08x] %04x, dreq_len %d",
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chan->dar, Pico32x.dmac_fifo[i], dreqlen);
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p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2);
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chan->dar += 2;
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chan->tcr--;
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(*dreqlen)--;
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}
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if (Pico32x.dmac0_fifo_ptr != i)
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@ -385,8 +452,6 @@ static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
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Pico32x.dmac0_fifo_ptr -= i;
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Pico32x.regs[6 / 2] &= ~P32XS_FULL;
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if (*dreqlen == 0)
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Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
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if (chan->tcr == 0)
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dmac_transfer_complete(sh2, chan);
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else
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@ -436,8 +501,19 @@ void p32x_dreq1_trigger(void)
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hit = 1;
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}
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if (!hit)
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elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared");
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// debug
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#if (EL_LOGMASK & (EL_32XP|EL_ANOMALY))
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{
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static int miss_count;
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if (!hit) {
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if (++miss_count == 4)
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elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared");
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}
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else
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miss_count = 0;
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}
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#endif
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(void)hit;
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}
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// vim:shiftwidth=2:ts=2:expandtab
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