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psp bugfixes, refactoring, stuff

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git-svn-id: file:///home/notaz/opt/svn/PicoDrive@284 be3aeb3a-fb24-0410-a615-afba39da0efa
This commit is contained in:
notaz 2007-10-29 18:16:46 +00:00
parent 03e4f2a349
commit 9d917eea21
14 changed files with 109 additions and 48 deletions
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21
cpu/fame/famec.c
View file

@ -26,6 +26,7 @@
#define FAMEC_ADR_BITS 24
// #define FAMEC_FETCHBITS 8
#define FAMEC_DATABITS 8
#define FAMEC_32BIT_PC
#define USE_CYCLONE_TIMING
#define USE_CYCLONE_TIMING_DIV
@ -289,15 +290,22 @@ static u32 flag_I;
#define GET_PC \
(u32)PC - BasePC;
#ifndef FAMEC_32BIT_PC
#define SET_PC(A) \
BasePC = g_m68kcontext->Fetch[((A) >> M68K_FETCHSFT) & M68K_FETCHMASK]; \
/* BasePC -= (A) & 0xFF000000; */ \
PC = (u16*)(((A) & M68K_ADR_MASK) + BasePC);
#define SET_PC_BASE(P,B,A) \
(B) = g_m68kcontext->Fetch[((A) >> M68K_FETCHSFT) & M68K_FETCHMASK]; \
/* (B) -= (A) & 0xFF000000; */ \
(P) = (u16*)(((A) & M68K_ADR_MASK) + (B));
#else
#define SET_PC(A) \
BasePC = g_m68kcontext->Fetch[((A) >> M68K_FETCHSFT) & M68K_FETCHMASK]; \
BasePC -= (A) & 0xFF000000; \
PC = (u16*)((A) + BasePC);
#endif
#define PRE_IO \
@ -717,7 +725,10 @@ static FAMEC_EXTRA_INLINE void execute_exception(s32 vect)
/* adjust SR */
flag_S = M68K_SR_S;
newPC&=M68K_ADR_MASK&~1; // don't crash on games with bad vector tables
#ifndef FAMEC_32BIT_PC
newPC&=M68K_ADR_MASK
#endif
newPC&=~1; // don't crash on games with bad vector tables
SET_PC(newPC)

44
cpu/fame/famec_opcodes.h
View file

@ -30046,7 +30046,11 @@ OPCODE(0x90D0)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
#ifdef USE_CYCLONE_TIMING
RET(12)
#else
RET(10)
#endif
}
// SUBA
@ -30063,7 +30067,11 @@ OPCODE(0x90D8)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
#ifdef USE_CYCLONE_TIMING
RET(12)
#else
RET(10)
#endif
}
// SUBA
@ -30080,7 +30088,11 @@ OPCODE(0x90E0)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
#ifdef USE_CYCLONE_TIMING
RET(14)
#else
RET(12)
#endif
}
// SUBA
@ -30097,7 +30109,11 @@ OPCODE(0x90E8)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
#ifdef USE_CYCLONE_TIMING
RET(16)
#else
RET(14)
#endif
}
// SUBA
@ -30114,7 +30130,11 @@ OPCODE(0x90F0)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
#ifdef USE_CYCLONE_TIMING
RET(18)
#else
RET(16)
#endif
}
// SUBA
@ -30130,7 +30150,11 @@ OPCODE(0x90F8)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
#ifdef USE_CYCLONE_TIMING
RET(16)
#else
RET(14)
#endif
}
// SUBA
@ -30146,7 +30170,11 @@ OPCODE(0x90F9)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
#ifdef USE_CYCLONE_TIMING
RET(20)
#else
RET(18)
#endif
}
// SUBA
@ -30163,7 +30191,11 @@ OPCODE(0x90FA)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
#ifdef USE_CYCLONE_TIMING
RET(16)
#else
RET(14)
#endif
}
// SUBA
@ -30180,7 +30212,11 @@ OPCODE(0x90FB)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
#ifdef USE_CYCLONE_TIMING
RET(18)
#else
RET(16)
#endif
}
// SUBA
@ -30210,7 +30246,11 @@ OPCODE(0x90DF)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
#ifdef USE_CYCLONE_TIMING
RET(12)
#else
RET(10)
#endif
}
// SUBA
@ -30227,7 +30267,11 @@ OPCODE(0x90E7)
res = dst - src;
AREG((Opcode >> 9) & 7) = res;
POST_IO
#ifdef USE_CYCLONE_TIMING
RET(14)
#else
RET(12)
#endif
}
// SUBA