mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
32x: improve interrupt handling
..hopefully..
This commit is contained in:
notaz
parent
531a8f3883
commit
9e1fa0a6cf
4 changed files with 74 additions and 37 deletions
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@ -39,13 +39,13 @@ void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
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m68k_cycles = sh2_cycles_done_m68k(active_sh2);
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// msh2
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irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES);
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irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[0];
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while ((irqs >>= 1))
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mlvl++;
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mlvl *= 2;
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// ssh2
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irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES);
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irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[1];
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while ((irqs >>= 1))
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slvl++;
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slvl *= 2;
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@ -67,6 +67,33 @@ void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
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elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
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}
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// the mask register is inconsistent, CMD is supposed to be a mask,
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// while others are actually irq trigger enables?
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// TODO: test on hw..
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void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask)
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{
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Pico32x.sh2irqs |= mask & P32XI_VRES;
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Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3);
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Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3);
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p32x_update_irls(sh2, m68k_cycles);
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}
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void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles)
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{
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if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1))
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Pico32x.sh2irqi[0] |= P32XI_CMD;
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else
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Pico32x.sh2irqi[0] &= ~P32XI_CMD;
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if ((Pico32x.sh2irq_mask[1] & 2) && (Pico32x.regs[2 / 2] & 2))
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Pico32x.sh2irqi[1] |= P32XI_CMD;
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else
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Pico32x.sh2irqi[1] &= ~P32XI_CMD;
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p32x_update_irls(sh2, m68k_cycles);
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}
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void Pico32xStartup(void)
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{
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elprintf(EL_STATUS|EL_32X, "32X startup");
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@ -174,8 +201,7 @@ void PicoReset32x(void)
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{
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if (PicoAHW & PAHW_32X) {
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msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT();
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Pico32x.sh2irqs |= P32XI_VRES;
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p32x_update_irls(NULL, SekCyclesDoneT2());
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p32x_trigger_irq(NULL, SekCyclesDoneT2(), P32XI_VRES);
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p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
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p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
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p32x_pwm_ctl_changed();
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@ -222,8 +248,7 @@ static void p32x_start_blank(void)
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Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
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}
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Pico32x.sh2irqs |= P32XI_VINT;
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p32x_update_irls(NULL, SekCyclesDoneT2());
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p32x_trigger_irq(NULL, SekCyclesDoneT2(), P32XI_VINT);
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p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
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p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
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}
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@ -265,8 +290,7 @@ static void fillend_event(unsigned int now)
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static void hint_event(unsigned int now)
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{
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Pico32x.sh2irqs |= P32XI_HINT;
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p32x_update_irls(NULL, now);
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p32x_trigger_irq(NULL, now, P32XI_HINT);
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p32x_schedule_hint(NULL, now);
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}
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@ -212,7 +212,7 @@ static u32 p32x_reg_read16(u32 a)
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unsigned int cycles = SekCyclesDoneT();
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if (cycles - msh2.m68krcycles_done > 64)
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p32x_sync_sh2s(cycles);
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return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
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goto out;
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}
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if ((a & 0x30) == 0x30)
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@ -269,21 +269,11 @@ static void p32x_reg_write8(u32 a, u32 d)
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case 0x02: // ignored, always 0
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return;
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case 0x03: // irq ctl
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if ((d & 1) != !!(Pico32x.sh2irqi[0] & P32XI_CMD)) {
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p32x_sync_sh2s(SekCyclesDoneT());
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if (d & 1)
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Pico32x.sh2irqi[0] |= P32XI_CMD;
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else
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Pico32x.sh2irqi[0] &= ~P32XI_CMD;
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p32x_update_irls(NULL, SekCyclesDoneT2());
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}
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if (!!(d & 2) != !!(Pico32x.sh2irqi[1] & P32XI_CMD)) {
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p32x_sync_sh2s(SekCyclesDoneT());
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if (d & 2)
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Pico32x.sh2irqi[1] |= P32XI_CMD;
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else
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Pico32x.sh2irqi[1] &= ~P32XI_CMD;
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p32x_update_irls(NULL, SekCyclesDoneT2());
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if ((d ^ r[0x02 / 2]) & 3) {
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int cycles = SekCyclesDoneT();
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p32x_sync_sh2s(cycles);
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r[0x02 / 2] = d & 3;
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p32x_update_cmd_irq(NULL, cycles);
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}
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return;
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case 0x04: // ignored, always 0
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@ -625,8 +615,9 @@ static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
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static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
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{
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a &= 0xff;
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u32 old;
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a &= 0xff;
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sh2->poll_addr = 0;
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switch (a) {
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@ -635,14 +626,20 @@ static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
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Pico32x.regs[0] |= (d << 8) & P32XS_FM;
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return;
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case 1: // HEN/irq masks
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old = Pico32x.sh2irq_mask[sh2->is_slave];
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if ((d ^ old) & 1)
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p32x_pwm_sync_to_sh2(sh2);
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Pico32x.sh2irq_mask[sh2->is_slave] = d & 0x0f;
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Pico32x.sh2_regs[0] &= ~0x80;
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Pico32x.sh2_regs[0] |= d & 0x80;
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if (d & 1)
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if ((d ^ old) & 1)
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p32x_pwm_schedule_sh2(sh2);
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if (d & 4)
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if ((old ^ d) & 2)
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p32x_update_cmd_irq(sh2, 0);
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if ((old ^ d) & 4)
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p32x_schedule_hint(sh2, 0);
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p32x_update_irls(sh2, 0);
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return;
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case 5: // H count
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d &= 0xff;
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@ -702,12 +699,22 @@ static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
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Pico32x.regs[0] &= ~P32XS_FM;
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Pico32x.regs[0] |= d & P32XS_FM;
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break;
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case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
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case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
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case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
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case 0x1a: Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_CMD; goto irls;
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case 0x14:
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Pico32x.sh2irqs &= ~P32XI_VRES;
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goto irls;
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case 0x16:
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Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_VINT;
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goto irls;
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case 0x18:
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Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_HINT;
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goto irls;
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case 0x1a:
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Pico32x.regs[2 / 2] &= ~(1 << sh2->is_slave);
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p32x_update_cmd_irq(sh2, 0);
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return;
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case 0x1c:
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Pico32x.sh2irqs &= ~P32XI_PWM;
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p32x_pwm_sync_to_sh2(sh2);
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Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_PWM;
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p32x_pwm_schedule_sh2(sh2);
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goto irls;
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}
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@ -31,8 +31,7 @@ void p32x_pwm_ctl_changed(void)
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static void do_pwm_irq(SH2 *sh2, unsigned int m68k_cycles)
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{
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Pico32x.sh2irqs |= P32XI_PWM;
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p32x_update_irls(sh2, m68k_cycles);
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p32x_trigger_irq(sh2, m68k_cycles, P32XI_PWM);
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if (Pico32x.regs[0x30 / 2] & P32XP_RTP) {
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p32x_event_schedule(m68k_cycles, P32X_EVENT_PWM, pwm_cycles / 3 + 1);
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@ -105,8 +104,6 @@ static int p32x_pwm_schedule_(SH2 *sh2, unsigned int m68k_now)
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if (cycles_diff_sh2 >= pwm_cycles)
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consume_fifo_do(sh2, m68k_now, cycles_diff_sh2);
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if (Pico32x.sh2irqs & P32XI_PWM)
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return 0; // previous not acked
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if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 1))
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return 0; // masked by everyone
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@ -129,6 +126,12 @@ void p32x_pwm_schedule_sh2(SH2 *sh2)
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p32x_event_schedule_sh2(sh2, P32X_EVENT_PWM, after);
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}
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void p32x_pwm_sync_to_sh2(SH2 *sh2)
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{
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int m68k_cycles = sh2_cycles_done_m68k(sh2);
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consume_fifo(sh2, m68k_cycles);
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}
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void p32x_pwm_irq_event(unsigned int m68k_now)
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{
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p32x_pwm_schedule(m68k_now);
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