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sh2 drc: bug fixing and optimization in register cache and branch handling

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This commit is contained in:
kub 2019-10-04 17:11:18 +02:00
parent 32818177bd
commit a0f5ba4067
3 changed files with 104 additions and 129 deletions
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15
cpu/drc/emit_arm.c
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@ -160,7 +160,12 @@ static NOINLINE void EMIT(u32 op, u32 dst, u32 src)
}
}
}
if (emit_index <= EMIT_CACHE_SIZE) {
if (dst & M1(PC)) {
// commit everything if a branch insn is emitted
for (i = 1; i <= emit_index+1; i++)
EMIT_PTR(emit_ptr, emit_cache[i].op);
emit_index = 0;
} else if (emit_index <= EMIT_CACHE_SIZE) {
// queue not yet full
emit_index++;
} else {
@ -654,13 +659,14 @@ static inline void emith_pool_adjust(int pool_index, int move_offs)
literal_insn[pool_index] += move_offs;
}
#define JMP_POS(ptr) \
#define JMP_POS(ptr) { \
ptr = tcache_ptr; \
EMIT(0,M1(PC),0);
EMIT(0,M1(PC),0); \
}
#define JMP_EMIT(cond, ptr) { \
u32 val_ = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \
emith_flush(); \
emith_flush(); /* NO insn swapping across jump targets */ \
EOP_C_B_PTR(ptr, cond, 0, val_ & 0xffffff); \
}
@ -890,7 +896,6 @@ static inline void emith_pool_adjust(int pool_index, int move_offs)
emith_top_imm(cond, A_OP_TST, r, imm)
#define emith_move_r_imm_s8_patchable(r, imm) do { \
emith_flush(); \
if ((s8)(imm) < 0) \
EOP_MVN_IMM(r, 0, (u8)~(imm)); \
else \

4
cpu/drc/emit_mips.c
View file

@ -1249,11 +1249,11 @@ static int emith_cond_check(int cond, int *r)
#define emith_push_ret(r) do { \
emith_sub_r_imm(SP, 8+16); /* reserve new arg save area (16) */ \
emith_write_r_r_offs(LR, SP, 4+16); \
if ((r) >= 0) emith_write_r_r_offs(r, SP, 0+16); \
if ((r) > 0) emith_write_r_r_offs(r, SP, 0+16); \
} while (0)
#define emith_pop_and_ret(r) do { \
if ((r) >= 0) emith_read_r_r_offs(r, SP, 0+16); \
if ((r) > 0) emith_read_r_r_offs(r, SP, 0+16); \
emith_read_r_r_offs(LR, SP, 4+16); \
emith_add_r_imm(SP, 8+16); \
emith_ret(); \