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sh2 drc: bug fixing and optimization in register cache and branch handling

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This commit is contained in:
kub 2019-10-04 17:11:18 +02:00
parent 32818177bd
commit a0f5ba4067
3 changed files with 104 additions and 129 deletions
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4
cpu/drc/emit_mips.c
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@ -1249,11 +1249,11 @@ static int emith_cond_check(int cond, int *r)
#define emith_push_ret(r) do { \
emith_sub_r_imm(SP, 8+16); /* reserve new arg save area (16) */ \
emith_write_r_r_offs(LR, SP, 4+16); \
if ((r) >= 0) emith_write_r_r_offs(r, SP, 0+16); \
if ((r) > 0) emith_write_r_r_offs(r, SP, 0+16); \
} while (0)
#define emith_pop_and_ret(r) do { \
if ((r) >= 0) emith_read_r_r_offs(r, SP, 0+16); \
if ((r) > 0) emith_read_r_r_offs(r, SP, 0+16); \
emith_read_r_r_offs(LR, SP, 4+16); \
emith_add_r_imm(SP, 8+16); \
emith_ret(); \