32x: drc: new smc handling, some bugfixes + refactoring

git-svn-id: file:///home/notaz/opt/svn/PicoDrive@864 be3aeb3a-fb24-0410-a615-afba39da0efa

cpu/drc/cmn.h

@@ -2,7 +2,7 @@ typedef unsigned char  u8;
 typedef unsigned short u16;
 typedef unsigned int   u32;
 
-#define DRC_TCACHE_SIZE         (512*1024)
+#define DRC_TCACHE_SIZE         (2*1024*1024)
 
 extern u8 tcache[DRC_TCACHE_SIZE];
 

cpu/drc/emit_arm.c

@@ -332,8 +332,8 @@ static int emith_xbranch(int cond, void *target, int is_call)
 	tcache_ptr += sizeof(u32)
 
 #define JMP_EMIT(cond, ptr) { \
-	int val = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \
-	EOP_C_B_PTR(ptr, cond, 0, val & 0xffffff); \
+	u32 val_ = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \
+	EOP_C_B_PTR(ptr, cond, 0, val_ & 0xffffff); \
 }
 
 #define EMITH_JMP_START(cond) { \
@@ -630,9 +630,6 @@ static int emith_xbranch(int cond, void *target, int is_call)
 	EOP_MOV_REG_ASR(d,d,32 - (bits)); \
 }
 
-#define host_arg2reg(rd, arg) \
-	rd = arg
-
 // upto 4 args
 #define emith_pass_arg_r(arg, reg) \
 	EOP_MOV_REG_SIMPLE(arg, reg)
@@ -658,6 +655,11 @@ static int emith_xbranch(int cond, void *target, int is_call)
 	*ptr_ = (*ptr_ & 0xff000000) | (val_ & 0x00ffffff); \
 } while (0)
 
+#define emith_jump_at(ptr, target) { \
+	u32 val_ = (u32 *)(target) - (u32 *)(ptr) - 2; \
+	EOP_C_B_PTR(ptr, A_COND_AL, 0, val_ & 0xffffff); \
+}
+
 #define emith_jump_reg_c(cond, r) \
 	EOP_C_BX(cond, r)
 
@@ -690,6 +692,18 @@ static int emith_xbranch(int cond, void *target, int is_call)
 #define emith_ret_to_ctx(offs) \
 	emith_ctx_write(14, offs)
 
+#define emith_push_ret() \
+	EOP_STMFD_SP(A_R14M)
+
+#define emith_pop_and_ret() \
+	EOP_LDMFD_SP(A_R15M)
+
+#define host_instructions_updated(base, end) \
+	cache_flush_d_inval_i(base, end)
+
+#define host_arg2reg(rd, arg) \
+	rd = arg
+
 /* SH2 drc specific */
 #define emith_sh2_drc_entry() \
 	EOP_STMFD_SP(A_R4M|A_R5M|A_R6M|A_R7M|A_R8M|A_R9M|A_R10M|A_R11M|A_R14M)

cpu/drc/emit_x86.c

@@ -1,6 +1,6 @@
 /*
  * note:
- *  temp registers must be eax-edx due to use of SETcc.
+ *  temp registers must be eax-edx due to use of SETcc and r/w 8/16.
  * note about silly things like emith_eor_r_r_r:
  *  these are here because the compiler was designed
  *  for ARM as it's primary target.
@@ -416,6 +416,30 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	} \
 } while (0)
 
+#define is_abcdx(r) (xAX <= (r) && (r) <= xDX)
+
+#define emith_read_op_8_16(op, r, rs, offs) do { \
+	int r_ = r; \
+	if (!is_abcdx(r)) \
+		r_ = rcache_get_tmp(); \
+	emith_deref_op(op, r_, rs, offs); \
+	if ((r) != r_) { \
+		emith_move_r_r(r, r_); \
+		rcache_free_tmp(r_); \
+	} \
+} while (0)
+
+#define emith_write_op_8_16(op, r, rs, offs) do { \
+	int r_ = r; \
+	if (!is_abcdx(r)) { \
+		r_ = rcache_get_tmp(); \
+		emith_move_r_r(r_, r); \
+	} \
+	emith_deref_op(op, r_, rs, offs); \
+	if ((r) != r_) \
+		rcache_free_tmp(r_); \
+} while (0)
+
 #define emith_read_r_r_offs(r, rs, offs) \
 	emith_deref_op(0x8b, r, rs, offs)
 
@@ -423,19 +447,19 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	emith_deref_op(0x89, r, rs, offs)
 
 #define emith_read8_r_r_offs(r, rs, offs) \
-	emith_deref_op(0x8a, r, rs, offs)
+	emith_read_op_8_16(0x8a, r, rs, offs)
 
 #define emith_write8_r_r_offs(r, rs, offs) \
-	emith_deref_op(0x88, r, rs, offs)
+	emith_write_op_8_16(0x88, r, rs, offs)
 
 #define emith_read16_r_r_offs(r, rs, offs) { \
 	EMIT(0x66, u8); /* operand override */ \
-	emith_read_r_r_offs(r, rs, offs); \
+	emith_read_op_8_16(0x8b, r, rs, offs); \
 }
 
 #define emith_write16_r_r_offs(r, rs, offs) { \
 	EMIT(0x66, u8); \
-	emith_write16_r_r_offs(r, rs, offs) \
+	emith_read_op_8_16(0x89, r, rs, offs); \
 }
 
 #define emith_ctx_read(r, offs) \
@@ -487,6 +511,12 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \
 } while (0)
 
+#define emith_jump_at(ptr, target) { \
+	u32 disp_ = (u32)(target) - ((u32)(ptr) + 5); \
+	EMIT_PTR(ptr, 0xe9, u8); \
+	EMIT_PTR((u8 *)(ptr) + 1, disp_, u32); \
+}
+
 #define emith_call(ptr) { \
 	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
 	EMIT_OP(0xe8); \
@@ -515,6 +545,11 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	EMIT(offs, u32); \
 }
 
+#define emith_push_ret()
+
+#define emith_pop_and_ret() \
+	emith_ret()
+
 #define EMITH_JMP_START(cond) { \
 	u8 *cond_ptr; \
 	JMP8_POS(cond_ptr)
@@ -544,13 +579,6 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 #define EMITH_SJMP3_MID EMITH_JMP3_MID
 #define EMITH_SJMP3_END EMITH_JMP3_END
 
-#define host_arg2reg(rd, arg) \
-	switch (arg) { \
-	case 0: rd = xAX; break; \
-	case 1: rd = xDX; break; \
-	case 2: rd = xCX; break; \
-	}
-
 #define emith_pass_arg_r(arg, reg) { \
 	int rd = 7; \
 	host_arg2reg(rd, arg); \
@@ -563,6 +591,15 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	emith_move_r_imm(rd, imm); \
 }
 
+#define host_instructions_updated(base, end)
+
+#define host_arg2reg(rd, arg) \
+	switch (arg) { \
+	case 0: rd = xAX; break; \
+	case 1: rd = xDX; break; \
+	case 2: rd = xCX; break; \
+	}
+
 /* SH2 drc specific */
 #define emith_sh2_drc_entry() { \
 	emith_push(xBX);        \