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sh2 drc: fix speed regression

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This commit is contained in:
kub 2019-12-13 18:23:03 +01:00
parent 90b1c9db91
commit a5e51c16e6
8 changed files with 35 additions and 18 deletions
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2
cpu/drc/emit_arm.c
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@ -20,7 +20,7 @@
#define TEMPORARY_REGS { 12, 14 }
#define CONTEXT_REG 11
#define STATIC_SH2_REGS { SHR_SR,10 , SHR_R0,8 , SHR_R0+1,9 }
#define STATIC_SH2_REGS { SHR_SR,10 , SHR_R(0),8 , SHR_R(1),9 }
// XXX: tcache_ptr type for SVP and SH2 compilers differs..
#define EMIT_PTR(ptr, x) \

2
cpu/drc/emit_arm64.c
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@ -15,7 +15,7 @@
#define TEMPORARY_REGS { 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 }
#define CONTEXT_REG 29
#define STATIC_SH2_REGS { SHR_SR,28 , SHR_R0,27 , SHR_R0+1,26 }
#define STATIC_SH2_REGS { SHR_SR,28 , SHR_R(0),27 , SHR_R(1),26 }
// R31 doesn't exist, it aliases either with zero or SP
#define SP 31 // stack pointer

2
cpu/drc/emit_mips.c
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@ -17,7 +17,7 @@
#define TEMPORARY_REGS { 2, 3, 8, 9, 10, 11, 12, 13, 14 } // v0-v1,t0-t6
#define CONTEXT_REG 23 // s7
#define STATIC_SH2_REGS { SHR_SR,22 , SHR_R0,21 , SHR_R0+1,20 }
#define STATIC_SH2_REGS { SHR_SR,22 , SHR_R(0),21 , SHR_R(1),20 }
// NB: the ubiquitous JZ74[46]0 uses MIPS32 Release 1, a slight MIPS II superset
#ifndef __mips_isa_rev

2
cpu/drc/emit_riscv.c
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@ -16,7 +16,7 @@
#define TEMPORARY_REGS { 5, 6, 7 } // t0-t2
#define CONTEXT_REG 9 // s1
#define STATIC_SH2_REGS { SHR_SR,27 , SHR_R0,26 , SHR_R0+1,25 }
#define STATIC_SH2_REGS { SHR_SR,27 , SHR_R(0),26 , SHR_R(1),25 }
// registers usable for user code: r1-r25, others reserved or special
#define Z0 0 // zero register

2
cpu/drc/emit_x86.c
View file

@ -1072,7 +1072,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI, // x86-64,i386 common
#define PARAM_REGS { xCX, xDX, xR8, xR9 }
#define PRESERVED_REGS { xSI, xDI, xR12, xR13, xR14, xR15, xBX, xBP }
#define TEMPORARY_REGS { xAX, xR10, xR11 }
#define STATIC_SH2_REGS { SHR_SR,xBX , SHR_R0,xR15 , SH2_R0+1,xR14 }
#define STATIC_SH2_REGS { SHR_SR,xBX , SHR_R(0),xR15 , SH2_R(1),xR14 }
#define host_arg2reg(rd, arg) \
switch (arg) { \