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sh2 drc: fix speed regression

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kub 2019-12-13 18:23:03 +01:00
parent 90b1c9db91
commit a5e51c16e6
8 changed files with 35 additions and 18 deletions
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2
cpu/drc/emit_mips.c
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@ -17,7 +17,7 @@
#define TEMPORARY_REGS { 2, 3, 8, 9, 10, 11, 12, 13, 14 } // v0-v1,t0-t6
#define CONTEXT_REG 23 // s7
#define STATIC_SH2_REGS { SHR_SR,22 , SHR_R0,21 , SHR_R0+1,20 }
#define STATIC_SH2_REGS { SHR_SR,22 , SHR_R(0),21 , SHR_R(1),20 }
// NB: the ubiquitous JZ74[46]0 uses MIPS32 Release 1, a slight MIPS II superset
#ifndef __mips_isa_rev