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sh2 drc: fix speed regression

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This commit is contained in:
kub 2019-12-13 18:23:03 +01:00
parent 90b1c9db91
commit a5e51c16e6
8 changed files with 35 additions and 18 deletions
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2
cpu/drc/emit_riscv.c
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@ -16,7 +16,7 @@
#define TEMPORARY_REGS { 5, 6, 7 } // t0-t2
#define CONTEXT_REG 9 // s1
#define STATIC_SH2_REGS { SHR_SR,27 , SHR_R0,26 , SHR_R0+1,25 }
#define STATIC_SH2_REGS { SHR_SR,27 , SHR_R(0),26 , SHR_R(1),25 }
// registers usable for user code: r1-r25, others reserved or special
#define Z0 0 // zero register