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sh2 drc, make B/W read functions signed (reduces generated code size)

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This commit is contained in:
kub 2019-04-26 18:53:21 +02:00
parent ed7e915078
commit aa4c4cb951
7 changed files with 85 additions and 60 deletions
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48
cpu/drc/emit_arm.c
View file

@ -795,6 +795,8 @@ static inline void emith_pool_check(void)
emith_read_r_r_offs_c(cond, r, rs, offs)
#define emith_read_r_r_r_c(cond, r, rs, rm) \
EOP_LDR_REG_LSL(cond, r, rs, rm, 0)
#define emith_read_r_r_offs(r, rs, offs) \
emith_read_r_r_offs_c(A_COND_AL, r, rs, offs)
#define emith_read_r_r_r(r, rs, rm) \
EOP_LDR_REG_LSL(A_COND_AL, r, rs, rm, 0)
@ -802,28 +804,37 @@ static inline void emith_pool_check(void)
EOP_LDRB_IMM2(cond, r, rs, offs)
#define emith_read8_r_r_r_c(cond, r, rs, rm) \
EOP_LDRB_REG_LSL(cond, r, rs, rm, 0)
#define emith_read8_r_r_offs(r, rs, offs) \
emith_read8_r_r_offs_c(A_COND_AL, r, rs, offs)
#define emith_read8_r_r_r(r, rs, rm) \
EOP_LDRB_REG_LSL(A_COND_AL, r, rs, rm, 0)
emith_read8_r_r_r_c(A_COND_AL, r, rs, rm)
#define emith_read16_r_r_offs_c(cond, r, rs, offs) \
EOP_LDRH_IMM2(cond, r, rs, offs)
#define emith_read16_r_r_r_c(cond, r, rs, rm) \
EOP_LDRH_REG2(cond, r, rs, rm)
#define emith_read16_r_r_r(r, rs, rm) \
EOP_LDRH_REG2(A_COND_AL, r, rs, rm)
#define emith_read_r_r_offs(r, rs, offs) \
emith_read_r_r_offs_c(A_COND_AL, r, rs, offs)
#define emith_read8s_r_r_offs(r, rs, offs) \
EOP_LDRSB_IMM2(A_COND_AL, r, rs, offs)
#define emith_read8_r_r_offs(r, rs, offs) \
emith_read8_r_r_offs_c(A_COND_AL, r, rs, offs)
#define emith_read16s_r_r_offs(r, rs, offs) \
EOP_LDRSH_IMM2(A_COND_AL, r, rs, offs)
#define emith_read16_r_r_offs(r, rs, offs) \
emith_read16_r_r_offs_c(A_COND_AL, r, rs, offs)
#define emith_read16_r_r_r(r, rs, rm) \
emith_read16_r_r_r_c(A_COND_AL, r, rs, rm)
#define emith_read8s_r_r_offs_c(cond, r, rs, offs) \
EOP_LDRSB_IMM2(cond, r, rs, offs)
#define emith_read8s_r_r_r_c(cond, r, rs, rm) \
EOP_LDRSB_REG2(cond, r, rs, rm)
#define emith_read8s_r_r_offs(r, rs, offs) \
emith_read8s_r_r_offs_c(A_COND_AL, r, rs, offs)
#define emith_read8s_r_r_r(r, rs, rm) \
emith_read8s_r_r_r_c(A_COND_AL, r, rs, rm)
#define emith_read16s_r_r_offs_c(cond, r, rs, offs) \
EOP_LDRSH_IMM2(cond, r, rs, offs)
#define emith_read16s_r_r_r_c(cond, r, rs, rm) \
EOP_LDRSH_REG2(cond, r, rs, rm)
#define emith_read16s_r_r_offs(r, rs, offs) \
emith_read16s_r_r_offs_c(A_COND_AL, r, rs, offs)
#define emith_read16s_r_r_r(r, rs, rm) \
emith_read16s_r_r_r_c(A_COND_AL, r, rs, rm)
#define emith_write_r_r_offs_c(cond, r, rs, offs) \
EOP_STR_IMM2(cond, r, rs, offs)
@ -945,6 +956,11 @@ static inline void emith_pool_check(void)
#define emith_call(target) \
emith_call_cond(A_COND_AL, target)
#define emith_call_reg(r) { \
emith_move_r_r(14, 15); \
EOP_C_BX(A_COND_AL, r); \
}
#define emith_call_ctx(offs) { \
emith_move_r_r(14, 15); \
emith_jump_ctx(offs); \
@ -1091,9 +1107,7 @@ static inline void emith_pool_check(void)
} while (0)
/* mh:ml += rn*rm, does saturation if required by S bit. rn, rm must be TEMP */
#define emith_sh2_macw(ml, mh, rn, rm, sr) do { \
emith_sext(rn, rn, 16); \
emith_sext(rm, rm, 16); \
#define emith_sh2_macw(ml, mh, rn, rm, sr) do { \
emith_tst_r_imm(sr, S); \
EMITH_SJMP2_START(DCOND_NE); \
emith_mula_s64_c(DCOND_EQ, ml, mh, rn, rm); \

22
cpu/drc/emit_x86.c
View file

@ -397,8 +397,12 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
#define emith_read8_r_r_r_c(cond, r, rs, rm) \
emith_read8_r_r_r(r, rs, rm)
#define emith_read8s_r_r_r_c(cond, r, rs, rm) \
emith_read8s_r_r_r(r, rs, rm)
#define emith_read16_r_r_r_c(cond, r, rs, rm) \
emith_read16_r_r_r(r, rs, rm)
#define emith_read16s_r_r_r_c(cond, r, rs, rm) \
emith_read16s_r_r_r(r, rs, rm)
#define emith_read_r_r_r_c(cond, r, rs, rm) \
emith_read_r_r_r(r, rs, rm)
@ -684,12 +688,24 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
EMIT_SIB(0, rs, rm); /* mov r, [rm + rs * 1] */ \
} while (0)
#define emith_read8s_r_r_r(r, rs, rm) do { \
EMIT(0x0f, u8); \
EMIT_OP_MODRM(0xbe, 0, r, 4); \
EMIT_SIB(0, rs, rm); /* mov r, [rm + rs * 1] */ \
} while (0)
#define emith_read16_r_r_r(r, rs, rm) do { \
EMIT(0x0f, u8); \
EMIT_OP_MODRM(0xb7, 0, r, 4); \
EMIT_SIB(0, rs, rm); /* mov r, [rm + rs * 1] */ \
} while (0)
#define emith_read16s_r_r_r(r, rs, rm) do { \
EMIT(0x0f, u8); \
EMIT_OP_MODRM(0xbf, 0, r, 4); \
EMIT_SIB(0, rs, rm); /* mov r, [rm + rs * 1] */ \
} while (0)
#define emith_read_r_r_r(r, rs, rm) do { \
EMIT_OP_MODRM(0x8b, 0, r, 4); \
EMIT_SIB(0, rs, rm); /* mov r, [rm + rs * 1] */ \
@ -785,9 +801,11 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
EMIT(offs, u32); \
} while (0)
#define emith_push_ret()
#define emith_push_ret() \
emith_push(xSI); /* to align */
#define emith_pop_and_ret() \
emith_pop(xSI); \
emith_ret()
#define EMITH_JMP_START(cond) { \
@ -1080,8 +1098,6 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
/* mh:ml += rn*rm, does saturation if required by S bit. rn, rm must be TEMP */
#define emith_sh2_macw(ml, mh, rn, rm, sr) do { \
emith_sext(rn, rn, 16); \
emith_sext(rm, rm, 16); \
emith_tst_r_imm(sr, S); \
EMITH_SJMP_START(DCOND_EQ); \
/* XXX: MACH should be untouched when S is set? */ \

34
cpu/sh2/compiler.c
View file

@ -2354,17 +2354,15 @@ static int emit_memhandler_read_rr(SH2 *sh2, sh2_reg_e rd, sh2_reg_e rs, u32 off
hr2 = hr;
else
#if REMAP_REGISTER
hr2 = rcache_map_reg(rd, hr, size != 2 ? RC_GR_RMW : RC_GR_WRITE);
hr2 = rcache_map_reg(rd, hr, RC_GR_WRITE);
#else
hr2 = rcache_get_reg(rd, RC_GR_WRITE, NULL);
#endif
if (rd != SHR_TMP && size != 2) { // 16, 8
emith_sext(hr2, hr, size ? 16 : 8);
} else if (hr != hr2) // 32
if (hr != hr2) {
emith_move_r_r(hr2, hr);
if (hr != hr2)
rcache_free_tmp(hr);
}
return hr2;
}
@ -2422,21 +2420,19 @@ static int emit_indirect_indexed_read(SH2 *sh2, sh2_reg_e rd, sh2_reg_e rx, sh2_
hr = emit_memhandler_read(size);
size &= MF_SIZEMASK;
if (rd != SHR_TMP)
if (rd == SHR_TMP)
hr2 = hr;
else
#if REMAP_REGISTER
hr2 = rcache_map_reg(rd, hr, size != 2 ? RC_GR_RMW : RC_GR_WRITE);
hr2 = rcache_map_reg(rd, hr, RC_GR_WRITE);
#else
hr2 = rcache_get_reg(rd, RC_GR_WRITE, NULL);
#endif
else
hr2 = hr;
if (rd != SHR_TMP && size != 2) { // 16, 8
emith_sext(hr2, hr, size ? 16 : 8);
} else if (hr != hr2) // 32
if (hr != hr2) {
emith_move_r_r(hr2, hr);
if (hr != hr2)
rcache_free_tmp(hr);
}
return hr2;
}
@ -2991,16 +2987,14 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
}
tmp2 = emit_memhandler_read(opd->size);
#if REMAP_REGISTER
tmp3 = rcache_map_reg(GET_Rn(), tmp2, opd->size != 2 ? RC_GR_RMW : RC_GR_WRITE);
tmp3 = rcache_map_reg(GET_Rn(), tmp2, RC_GR_WRITE);
#else
tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE, NULL);
#endif
if (opd->size != 2) {
emith_sext(tmp3, tmp2, 16);
} else if (tmp3 != tmp2)
if (tmp3 != tmp2) {
emith_move_r_r(tmp3, tmp2);
if (tmp3 != tmp2)
rcache_free_tmp(tmp2);
}
}
goto end_op;
@ -4025,7 +4019,7 @@ static void sh2_generate_utils(void)
EMITH_SJMP_START(DCOND_CS);
emith_and_r_r_c(DCOND_CC, arg0, arg3);
emith_eor_r_imm_c(DCOND_CC, arg0, 1);
emith_read8_r_r_r_c(DCOND_CC, RET_REG, arg0, arg2);
emith_read8s_r_r_r_c(DCOND_CC, RET_REG, arg0, arg2);
emith_ret_c(DCOND_CC);
EMITH_SJMP_END(DCOND_CS);
emith_move_r_r_ptr(arg1, CONTEXT_REG);
@ -4037,7 +4031,7 @@ static void sh2_generate_utils(void)
emith_sh2_rcall(arg0, arg1, arg2, arg3);
EMITH_SJMP_START(DCOND_CS);
emith_and_r_r_c(DCOND_CC, arg0, arg3);
emith_read16_r_r_r_c(DCOND_CC, RET_REG, arg0, arg2);
emith_read16s_r_r_r_c(DCOND_CC, RET_REG, arg0, arg2);
emith_ret_c(DCOND_CC);
EMITH_SJMP_END(DCOND_CS);
emith_move_r_r_ptr(arg1, CONTEXT_REG);

4
cpu/sh2/compiler.h
View file

@ -44,10 +44,10 @@ unsigned short scan_block(unsigned int base_pc, int is_slave,
#define _DRC_DECLARE_SR(SR) __DRC_DECLARE_SR(SR)
#define DRC_DECLARE_SR _DRC_DECLARE_SR(DRC_SR_REG)
#define DRC_SAVE_SR(sh2) \
if ((sh2->state & (SH2_STATE_RUN)) == SH2_STATE_RUN) \
if ((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN) \
sh2->sr = sh2_sr;
#define DRC_RESTORE_SR(sh2) \
if ((sh2->state & (SH2_STATE_RUN)) == SH2_STATE_RUN) \
if ((sh2->state & (SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN) \
sh2_sr = sh2->sr;
#else
#define DRC_DECLARE_SR

10
cpu/sh2/mame/sh2.c
View file

@ -372,7 +372,7 @@ INLINE void BRA(sh2_state *sh2, UINT32 d)
#if BUSY_LOOP_HACKS
if (disp == -2)
{
UINT32 next_opcode = RW( sh2, sh2->ppc & AM );
UINT32 next_opcode = (UINT32)(UINT16)RW( sh2, sh2->ppc & AM );
/* BRA $
* NOP
*/
@ -802,7 +802,7 @@ INLINE void DT(sh2_state *sh2, UINT32 n)
sh2->sr &= ~T;
#if BUSY_LOOP_HACKS
{
UINT32 next_opcode = RW( sh2, sh2->ppc & AM );
UINT32 next_opcode = (UINT32)(UINT16)RW( sh2, sh2->ppc & AM );
/* DT Rn
* BF $-2
*/
@ -1049,12 +1049,12 @@ INLINE void MAC_W(sh2_state *sh2, UINT32 m, UINT32 n)
INT32 tempm, tempn, dest, src, ans;
UINT32 templ;
tempn = (INT32) RW( sh2, sh2->r[n] );
tempn = (INT32)(INT16) RW( sh2, sh2->r[n] );
sh2->r[n] += 2;
tempm = (INT32) RW( sh2, sh2->r[m] );
tempm = (INT32)(INT16) RW( sh2, sh2->r[m] );
sh2->r[m] += 2;
templ = sh2->macl;
tempm = ((INT32) (short) tempn * (INT32) (short) tempm);
tempm = (tempn * tempm);
if ((INT32) sh2->macl >= 0)
dest = 0;
else

8
cpu/sh2/mame/sh2pico.c
View file

@ -121,7 +121,7 @@ int sh2_execute_interpreter(SH2 *sh2, int cycles)
if (sh2->delay)
{
sh2->ppc = sh2->delay;
opcode = RW(sh2, sh2->delay);
opcode = (UINT32)(UINT16)RW(sh2, sh2->delay);
// TODO: more branch types
if ((opcode >> 13) == 5) { // BRA/BSR
@ -139,7 +139,7 @@ int sh2_execute_interpreter(SH2 *sh2, int cycles)
else
{
sh2->ppc = sh2->pc;
opcode = RW(sh2, sh2->pc);
opcode = (UINT32)(UINT16)RW(sh2, sh2->pc);
}
sh2->delay = 0;
@ -232,13 +232,13 @@ int sh2_execute_interpreter(SH2 *sh2, int cycles)
if (sh2->delay)
{
sh2->ppc = sh2->delay;
opcode = RW(sh2, sh2->delay);
opcode = (UINT32)(UINT16)RW(sh2, sh2->delay);
sh2->pc -= 2;
}
else
{
sh2->ppc = sh2->pc;
opcode = RW(sh2, sh2->pc);
opcode = (UINT32)(UINT16)RW(sh2, sh2->pc);
}
sh2->delay = 0;