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core, fix z80 irq handling, reset defaults (cz80, drz80)

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This commit is contained in:
kub 2024-02-22 21:01:37 +01:00
parent bfe516c3a9
commit ad43165afc
6 changed files with 35 additions and 40 deletions
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2
cpu/cz80/cz80.c
View file

@ -212,6 +212,8 @@ void Cz80_Reset(cz80_struc *CPU)
{
// I, R, CPU and interrupts logic is reset, registers are untouched
memset(&CPU->R, 0, (FPTR)&CPU->BasePC - (FPTR)&CPU->R);
Cz80_Set_Reg(CPU, CZ80_FA, 0xffff);
Cz80_Set_Reg(CPU, CZ80_SP, 0xffff);
Cz80_Set_Reg(CPU, CZ80_PC, 0);
}

11
cpu/cz80/cz80_op.c
View file

@ -711,15 +711,6 @@ OP_EI:
USE_CYCLES(4)
if (!zIFF1)
{
zIFF1 = zIFF2 = (1 << 2);
while (GET_OP() == 0xfb)
{
USE_CYCLES(4)
PC++;
#if CZ80_EMULATE_R_EXACTLY
zR++;
#endif
}
if (CPU->IRQState)
{
CPU->Status |= CZ80_HAS_INT;
@ -727,7 +718,7 @@ OP_EI:
CPU->ICount = 0;
}
}
else zIFF2 = (1 << 2);
zIFF1 = zIFF2 = (1 << 2);
goto Cz80_Exec_nocheck;
/*-----------------------------------------

35
cpu/cz80/cz80_opED.c
View file

@ -407,29 +407,14 @@ OP_SBC16:
RET(8)
/*-----------------------------------------
RETN
RETI/RETN
-----------------------------------------*/
OPED(0x45): // RETN;
OPED(0x55): // RETN;
OPED(0x65): // RETN;
OPED(0x75): // RETN;
POP_16(res);
SET_PC(res);
if (!zIFF1 && zIFF2)
{
zIFF1 = (1 << 2);
if (CPU->IRQState)
{
CPU->Status |= CZ80_HAS_INT;
}
}
else zIFF1 = zIFF2;
RET(10)
/*-----------------------------------------
RETI
-----------------------------------------*/
// works the same, but Z80 PIO can detect the opcode
OPED(0x45): // RETN
OPED(0x55): // RETN
OPED(0x65): // RETN
OPED(0x75): // RETN
OPED(0x4d): // RETI
OPED(0x5d): // RETI
@ -437,6 +422,14 @@ OP_SBC16:
OPED(0x7d): // RETI
POP_16(res);
SET_PC(res);
if (!zIFF1 && zIFF2)
{
if (CPU->IRQState)
{
CPU->Status |= CZ80_HAS_INT;
}
}
zIFF1 = zIFF2;
RET(10)
/*-----------------------------------------