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sh2 drc, register cache optimisations

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This commit is contained in:
kub 2019-05-22 21:04:59 +02:00
parent 49daa9e093
commit adf39a13f9
3 changed files with 197 additions and 151 deletions
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26
pico/32x/memory.c
View file

@ -1730,6 +1730,32 @@ void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
wh(a, d, sh2);
}
void *p32x_sh2_get_mem_ptr(u32 a, u32 *mask, SH2 *sh2)
{
const sh2_memmap *mm = sh2->read8_map;
void *ret = (void *)-1;
u32 am;
mm += a >> SH2_READ_SHIFT;
am = a & ((1 << SH2_READ_SHIFT)-1);
if (!map_flag_set(mm->addr) && !(am & ~mm->mask)) {
// directly mapped memory (SDRAM, ROM, data array)
ret = (void *)(mm->addr << 1);
*mask = mm->mask;
} else if ((a & ~0x7ff) == 0) {
// BIOS, has handler function since it shares its segment with I/O
ret = sh2->is_slave ? Pico32xMem->sh2_rom_s.w : Pico32xMem->sh2_rom_m.w;
*mask = 0x7ff;
} else if ((a & 0xc6000000) == 0x02000000) {
// banked ROM. Return bank address
u32 bank = carthw_ssf2_banks[(a >> 19) & 7] << 19;
ret = sh2->p_rom + bank;
*mask = 0x07ffff;
}
return ret;
}
// -----------------------------------------------------------------
static void z80_md_bank_write_32x(unsigned int a, unsigned char d)

1
pico/pico_int.h
View file

@ -933,6 +933,7 @@ void Pico32xMemStateLoaded(void);
void p32x_update_banks(void);
void p32x_m68k_poll_event(unsigned int flags);
void p32x_sh2_poll_memory(unsigned int a, SH2 *sh2);
void *p32x_sh2_get_mem_ptr(unsigned int a, unsigned int *mask, SH2 *sh2);
void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);
// 32x/draw.c