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https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 15:27:46 -04:00
32x: drc: mmap dram+rom for direct dereference
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@851 be3aeb3a-fb24-0410-a615-afba39da0efa
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notaz
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f6c49d38cb
commit
b081408f66
8 changed files with 200 additions and 71 deletions
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@ -169,7 +169,8 @@
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#define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm) EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
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/* ldr and str */
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#define EOP_LDR_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,0,1,rn,rd,offset_12)
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#define EOP_LDR_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,0,1,rn,rd,offset_12)
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#define EOP_LDRB_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,1,1,rn,rd,offset_12)
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#define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
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#define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
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@ -179,6 +180,8 @@
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#define EOP_LDR_REG_LSL(cond,rd,rn,rm,shift_imm) EOP_C_AM2_REG(cond,1,0,1,rn,rd,shift_imm,A_AM1_LSL,rm)
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#define EOP_LDRH_IMM2(cond,rd,rn,offset_8) EOP_C_AM3_IMM(cond,1,1,rn,rd,0,1,offset_8)
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#define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
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#define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
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#define EOP_LDRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
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@ -327,11 +330,14 @@ static int emith_xbranch(int cond, void *target, int is_call)
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}
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// fake "simple" or "short" jump - using cond insns instead
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#define EMITH_SJMP_START(cond) \
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#define EMITH_NOTHING1(cond) \
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(void)(cond)
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#define EMITH_SJMP_END(cond) \
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(void)(cond)
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#define EMITH_SJMP_START(cond) EMITH_NOTHING1(cond)
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#define EMITH_SJMP_END(cond) EMITH_NOTHING1(cond)
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#define EMITH_SJMP3_START(cond) EMITH_NOTHING1(cond)
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#define EMITH_SJMP3_MID(cond) EMITH_NOTHING1(cond)
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#define EMITH_SJMP3_END()
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#define emith_move_r_r(d, s) \
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EOP_MOV_REG_SIMPLE(d, s)
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@ -485,8 +491,11 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_asr(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ASR,cnt)
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#define emith_ror_c(cond, d, s, cnt) \
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EOP_MOV_REG(cond,0,d,s,A_AM1_ROR,cnt)
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#define emith_ror(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,cnt)
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emith_ror_c(A_COND_AL, d, s, cnt)
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#define emith_rol(d, s, cnt) \
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EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,32-(cnt)); \
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@ -536,8 +545,26 @@ static int emith_xbranch(int cond, void *target, int is_call)
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EOP_C_SMLAL(A_COND_AL,0,dhi,dlo,s1,s2)
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// misc
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#define emith_read_r_r_offs_c(cond, r, rs, offs) \
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EOP_LDR_IMM2(cond, r, rs, offs)
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#define emith_read8_r_r_offs_c(cond, r, rs, offs) \
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EOP_LDRB_IMM2(cond, r, rs, offs)
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#define emith_read16_r_r_offs_c(cond, r, rs, offs) \
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EOP_LDRH_IMM2(cond, r, rs, offs)
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#define emith_read_r_r_offs(r, rs, offs) \
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emith_read_r_r_offs_c(A_COND_AL, r, rs, offs)
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#define emith_read8_r_r_offs(r, rs, offs) \
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emith_read8_r_r_offs_c(A_COND_AL, r, rs, offs)
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#define emith_read16_r_r_offs(r, rs, offs) \
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emith_read16_r_r_offs_c(A_COND_AL, r, rs, offs)
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#define emith_ctx_read(r, offs) \
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EOP_LDR_IMM(r, CONTEXT_REG, offs)
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emith_read_r_r_offs(r, CONTEXT_REG, offs)
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#define emith_ctx_write(r, offs) \
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EOP_STR_IMM(r, CONTEXT_REG, offs)
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@ -219,29 +219,38 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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emith_add_r_imm(r, imm); \
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}
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#define emith_or_r_imm_c(cond, r, imm) { \
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(void)(cond); \
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emith_or_r_imm(r, imm); \
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}
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#define emith_eor_r_imm_c(cond, r, imm) { \
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(void)(cond); \
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emith_eor_r_imm(r, imm); \
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}
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#define emith_sub_r_imm_c(cond, r, imm) { \
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(void)(cond); \
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emith_sub_r_imm(r, imm); \
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}
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#define emith_bic_r_imm_c(cond, r, imm) { \
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(void)(cond); \
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emith_bic_r_imm(r, imm); \
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}
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#define emith_or_r_imm_c(cond, r, imm) \
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emith_or_r_imm(r, imm)
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#define emith_eor_r_imm_c(cond, r, imm) \
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emith_eor_r_imm(r, imm)
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#define emith_bic_r_imm_c(cond, r, imm) \
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emith_bic_r_imm(r, imm)
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#define emith_ror_c(cond, d, s, cnt) \
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emith_ror(d, s, cnt)
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#define emith_jump_reg_c(cond, r) emith_jump_reg(r)
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#define emith_jump_ctx_c(cond, offs) emith_jump_ctx(offs)
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#define emith_ret_c(cond) emith_ret()
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#define emith_read_r_r_offs_c(cond, r, rs, offs) \
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emith_read_r_r_offs(r, rs, offs)
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#define emith_write_r_r_offs_c(cond, r, rs, offs) \
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emith_write_r_r_offs(r, rs, offs)
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#define emith_read8_r_r_offs_c(cond, r, rs, offs) \
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emith_read8_r_r_offs(r, rs, offs)
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#define emith_write8_r_r_offs_c(cond, r, rs, offs) \
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emith_write8_r_r_offs(r, rs, offs)
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#define emith_read16_r_r_offs_c(cond, r, rs, offs) \
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emith_read16_r_r_offs(r, rs, offs)
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#define emith_write16_r_r_offs_c(cond, r, rs, offs) \
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emith_write16_r_r_offs(r, rs, offs)
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#define emith_jump_reg_c(cond, r) \
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emith_jump_reg(r)
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#define emith_jump_ctx_c(cond, offs) \
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emith_jump_ctx(offs)
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#define emith_ret_c(cond) \
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emith_ret()
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// _r_r_imm
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#define emith_add_r_r_imm(d, s, imm) { \
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@ -391,22 +400,44 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_rolcf emith_rolc
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#define emith_rorcf emith_rorc
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#define emith_ctx_op(op, r, offs) do { \
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#define emith_deref_op(op, r, rs, offs) do { \
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/* mov r <-> [ebp+#offs] */ \
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if ((offs) >= 0x80) { \
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EMIT_OP_MODRM(op, 2, r, xBP); \
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EMIT_OP_MODRM(op, 2, r, rs); \
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EMIT(offs, u32); \
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} else { \
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EMIT_OP_MODRM(op, 1, r, xBP); \
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EMIT_OP_MODRM(op, 1, r, rs); \
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EMIT(offs, u8); \
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} \
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} while (0)
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#define emith_read_r_r_offs(r, rs, offs) \
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emith_deref_op(0x8b, r, rs, offs)
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#define emith_write_r_r_offs(r, rs, offs) \
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emith_deref_op(0x89, r, rs, offs)
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#define emith_read8_r_r_offs(r, rs, offs) \
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emith_deref_op(0x8a, r, rs, offs)
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#define emith_write8_r_r_offs(r, rs, offs) \
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emith_deref_op(0x88, r, rs, offs)
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#define emith_read16_r_r_offs(r, rs, offs) { \
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EMIT(0x66, u8); /* operand override */ \
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emith_read_r_r_offs(r, rs, offs); \
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}
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#define emith_write16_r_r_offs(r, rs, offs) { \
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EMIT(0x66, u8); \
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emith_write16_r_r_offs(r, rs, offs) \
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}
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#define emith_ctx_read(r, offs) \
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emith_ctx_op(0x8b, r, offs)
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emith_read_r_r_offs(r, CONTEXT_REG, offs)
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#define emith_ctx_write(r, offs) \
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emith_ctx_op(0x89, r, offs)
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emith_write_r_r_offs(r, CONTEXT_REG, offs)
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#define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
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int r_ = r, offs_ = offs, cnt_ = cnt; \
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@ -460,7 +491,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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EMIT_OP_MODRM(0xff, 3, 2, r)
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#define emith_call_ctx(offs) { \
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EMIT_OP_MODRM(0xff, 2, 2, xBP); \
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EMIT_OP_MODRM(0xff, 2, 2, CONTEXT_REG); \
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EMIT(offs, u32); \
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}
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@ -471,7 +502,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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EMIT_OP_MODRM(0xff, 3, 4, r)
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#define emith_jump_ctx(offs) { \
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EMIT_OP_MODRM(0xff, 2, 4, xBP); \
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EMIT_OP_MODRM(0xff, 2, 4, CONTEXT_REG); \
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EMIT(offs, u32); \
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}
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@ -483,10 +514,27 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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JMP8_EMIT(cond, cond_ptr); \
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}
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#define EMITH_JMP3_START(cond) { \
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u8 *cond_ptr, *else_ptr; \
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JMP8_POS(cond_ptr)
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#define EMITH_JMP3_MID(cond) \
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JMP8_POS(else_ptr); \
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JMP8_EMIT(cond, cond_ptr);
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#define EMITH_JMP3_END() \
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JMP8_EMIT_NC(else_ptr); \
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}
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// "simple" jump (no more then a few insns)
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// ARM will use conditional instructions here
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#define EMITH_SJMP_START EMITH_JMP_START
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#define EMITH_SJMP_END EMITH_JMP_END
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#define EMITH_SJMP3_START EMITH_JMP3_START
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#define EMITH_SJMP3_MID EMITH_JMP3_MID
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#define EMITH_SJMP3_END EMITH_JMP3_END
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#define host_arg2reg(rd, arg) \
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switch (arg) { \
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case 0: rd = xAX; break; \
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@ -496,24 +496,60 @@ static void emit_or_t_if_eq(int srr)
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// reg cache must be clean before call
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static int emit_memhandler_read(int size)
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{
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int ctxr;
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host_arg2reg(ctxr, 1);
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emith_move_r_r(ctxr, CONTEXT_REG);
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switch (size) {
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case 0: // 8
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// must writeback cycles for poll detection stuff
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if (reg_map_g2h[SHR_SR] != -1)
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emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
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emith_call(p32x_sh2_read8);
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break;
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case 1: // 16
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if (reg_map_g2h[SHR_SR] != -1)
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emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
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emith_call(p32x_sh2_read16);
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break;
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case 2: // 32
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emith_call(p32x_sh2_read32);
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break;
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int arg0, arg1;
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host_arg2reg(arg0, 0);
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// must writeback cycles for poll detection stuff
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if (reg_map_g2h[SHR_SR] != -1)
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emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
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arg1 = rcache_get_tmp_arg(1);
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emith_move_r_r(arg1, CONTEXT_REG);
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#if 1
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if (Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
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int tmp = rcache_get_tmp();
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emith_and_r_r_imm(tmp, arg0, 0xfb000000);
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emith_cmp_r_imm(tmp, 0x02000000);
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switch (size) {
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case 0: // 8
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EMITH_SJMP3_START(DCOND_NE);
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emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
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emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
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EMITH_SJMP3_MID(DCOND_NE);
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emith_call_cond(DCOND_NE, p32x_sh2_read8);
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EMITH_SJMP3_END();
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break;
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case 1: // 16
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EMITH_SJMP3_START(DCOND_NE);
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emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
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EMITH_SJMP3_MID(DCOND_NE);
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emith_call_cond(DCOND_NE, p32x_sh2_read16);
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EMITH_SJMP3_END();
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break;
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case 2: // 32
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EMITH_SJMP3_START(DCOND_NE);
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emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
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emith_ror_c(DCOND_EQ, arg0, arg0, 16);
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EMITH_SJMP3_MID(DCOND_NE);
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emith_call_cond(DCOND_NE, p32x_sh2_read32);
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EMITH_SJMP3_END();
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break;
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}
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}
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else
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#endif
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{
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switch (size) {
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case 0: // 8
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emith_call(p32x_sh2_read8);
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break;
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case 1: // 16
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emith_call(p32x_sh2_read16);
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break;
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case 2: // 32
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emith_call(p32x_sh2_read32);
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break;
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}
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}
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rcache_invalidate();
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// assuming arg0 and retval reg matches
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