sms, improve ROM bank mapping, add some SRAM support

cpu/cz80/cz80.h

@@ -59,7 +59,8 @@ extern "C" {
 /* Z80 core Structures & definitions */
 /*************************************/
 
-#define CZ80_FETCH_BITS			4   // [4-12]   default = 8
+// NB this must have at least the value of (16-Z80_MEM_SHIFT)
+#define CZ80_FETCH_BITS			6   // [4-12]   default = 8
 
 #define CZ80_FETCH_SFT			(16 - CZ80_FETCH_BITS)
 #define CZ80_FETCH_BANK			(1 << CZ80_FETCH_BITS)

pico/cart.c

@@ -34,6 +34,7 @@ void (*PicoCDLoadProgressCB)(const char *fname, int percent) = NULL; // handled
 int PicoGameLoaded;
 
 static void PicoCartDetect(const char *carthw_cfg);
+static void PicoCartDetectMS(void);
 
 /* cso struct */
 typedef struct _cso_struct
@@ -850,6 +851,8 @@ int PicoCartInsert(unsigned char *rom, unsigned int romsize, const char *carthw_
 
   if (!(PicoIn.AHW & (PAHW_MCD|PAHW_SMS)))
     PicoCartDetect(carthw_cfg);
+  else if (PicoIn.AHW & PAHW_SMS)
+    PicoCartDetectMS();
 
   // setup correct memory map for loaded ROM
   switch (PicoIn.AHW) {
@@ -1320,4 +1323,17 @@ static void PicoCartDetect(const char *carthw_cfg)
     *(u32 *) (Pico.rom + 0x1f0) = CPU_LE4(0x20204520);
 }
 
+static void PicoCartDetectMS(void)
+{
+  memset(&Pico.sv, 0, sizeof(Pico.sv));
+
+  // Always map SRAM, since there's no indicator in ROM if it's needed or not
+  // TODO: this should somehow be coming from a cart database!
+
+  Pico.sv.size  = 0x8000; // Sega mapper, 2 banks of 16 KB each
+  Pico.sv.flags |= SRF_ENABLED;
+  Pico.sv.data = calloc(Pico.sv.size, 1);
+  if (Pico.sv.data == NULL)
+    Pico.sv.flags &= ~SRF_ENABLED;
+}
 // vim:shiftwidth=2:expandtab

pico/memory.h

@@ -38,7 +38,7 @@ extern void s68k_write16(u32 a, u16 d);
 extern void s68k_write32(u32 a, u32 d);
 
 // z80
-#define Z80_MEM_SHIFT 13
+#define Z80_MEM_SHIFT 10 // must be <=10 to allow 1KB pages for SMS Sega mapper
 extern uptr z80_read_map [0x10000 >> Z80_MEM_SHIFT];
 extern uptr z80_write_map[0x10000 >> Z80_MEM_SHIFT];
 typedef unsigned char (z80_read_f)(unsigned short a);

pico/sms.c

@@ -219,17 +219,30 @@ static void z80_sms_out(unsigned short a, unsigned char d)
 
 static int bank_mask;
 
+static void xwrite(unsigned int a, unsigned char d);
+
+static void write_sram(unsigned short a, unsigned char d)
+{
+  // SRAM is mapped in 2 16KB banks, selected by bit 2 in control reg
+  a &= 0x3fff;
+  a += ((Pico.ms.carthw[0x0c] & 0x04) >> 2) * 0x4000;
+
+  Pico.sv.changed |= (Pico.sv.data[a] != d);
+  Pico.sv.data[a] = d;
+}
+
 static void write_bank(unsigned short a, unsigned char d)
 {
   elprintf(EL_Z80BNK, "bank %04x %02x @ %04x", a, d, z80_pc());
+  Pico.ms.carthw[a & 0x0f] = d;
   switch (a & 0x0f)
   {
-    case 0x0c:
-      elprintf(EL_STATUS|EL_ANOMALY, "%02x written to control reg!", d);
-      break;
     case 0x0d:
-      if (d != 0)
+      d &= bank_mask;
-        elprintf(EL_STATUS|EL_ANOMALY, "bank0 changed to %d!", d);
+      z80_map_set(z80_read_map, 0x0400, 0x3fff, Pico.rom+0x400 + (d << 14), 0);
+#ifdef _USE_CZ80
+      Cz80_Set_Fetch(&CZ80, 0x0400, 0x3fff, (FPTR)Pico.rom+0x400 + (d << 14));
+#endif
       break;
     case 0x0e:
       d &= bank_mask;
@@ -238,15 +251,29 @@ static void write_bank(unsigned short a, unsigned char d)
       Cz80_Set_Fetch(&CZ80, 0x4000, 0x7fff, (FPTR)Pico.rom + (d << 14));
 #endif
       break;
+
+    case 0x0c:
+      if (d & ~0x8c)
+        elprintf(EL_STATUS|EL_ANOMALY, "%02x written to control reg!", d);
+      /*FALLTHROUGH*/
     case 0x0f:
-      d &= bank_mask;
+      if (Pico.ms.carthw[0xc] & 0x08) {
-      z80_map_set(z80_read_map, 0x8000, 0xbfff, Pico.rom + (d << 14), 0);
+        d = (Pico.ms.carthw[0xc] & 0x04) >> 2;
+        z80_map_set(z80_read_map, 0x8000, 0xbfff, Pico.sv.data + d*0x4000, 0);
 #ifdef _USE_CZ80
-      Cz80_Set_Fetch(&CZ80, 0x8000, 0xbfff, (FPTR)Pico.rom + (d << 14));
+        Cz80_Set_Fetch(&CZ80, 0x8000, 0xbfff, (FPTR)Pico.sv.data + d*0x4000);
 #endif
+        z80_map_set(z80_write_map, 0x8000, 0xbfff, write_sram, 1);
+      } else {
+        d = Pico.ms.carthw[0xf] & bank_mask;
+        z80_map_set(z80_read_map, 0x8000, 0xbfff, Pico.rom + (d << 14), 0);
+#ifdef _USE_CZ80
+        Cz80_Set_Fetch(&CZ80, 0x8000, 0xbfff, (FPTR)Pico.rom + (d << 14));
+#endif
+        z80_map_set(z80_write_map, 0x8000, 0xbfff, xwrite, 1);
+      }
       break;
   }
-  Pico.ms.carthw[a & 0x0f] = d;
 }
 
 static void xwrite(unsigned int a, unsigned char d)
@@ -256,6 +283,16 @@ static void xwrite(unsigned int a, unsigned char d)
     PicoMem.zram[a & 0x1fff] = d;
   if (a >= 0xfff8)
     write_bank(a, d);
+  // codemasters
+  if (a == 0x0000)
+    write_bank(0xfffd, d);
+  if (a == 0x4000)
+    write_bank(0xfffe, d);
+  if (a == 0x8000)
+    write_bank(0xffff, d);
+  // korean
+  if (a == 0xa000)
+    write_bank(0xffff, d);
 }
 
 void PicoResetMS(void)
@@ -284,6 +321,8 @@ void PicoPowerMS(void)
   tmp = 1 << s;
   bank_mask = (tmp - 1) >> 14;
 
+  Pico.ms.carthw[0x0c] = 0;
+  Pico.ms.carthw[0x0d] = 0;
   Pico.ms.carthw[0x0e] = 1;
   Pico.ms.carthw[0x0f] = 2;
 
@@ -315,6 +354,8 @@ void PicoMemSetupMS(void)
 
 void PicoStateLoadedMS(void)
 {
+  write_bank(0xfffc, Pico.ms.carthw[0x0c]);
+  write_bank(0xfffd, Pico.ms.carthw[0x0d]);
   write_bank(0xfffe, Pico.ms.carthw[0x0e]);
   write_bank(0xffff, Pico.ms.carthw[0x0f]);
 }