mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
DRC: reworked scan_block (fix register usage masks, better block and literals detection)
This commit is contained in:
kub
parent
32feba7458
commit
b804d9543b
3 changed files with 162 additions and 85 deletions
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@ -5,7 +5,7 @@ typedef signed short s16;
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typedef unsigned int u32;
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typedef signed int s32;
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#define DRC_TCACHE_SIZE (2*1024*1024)
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#define DRC_TCACHE_SIZE (4*1024*1024)
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extern u8 *tcache;
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@ -686,7 +686,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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case 0: rd = xDI; break; \
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case 1: rd = xSI; break; \
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case 2: rd = xDX; break; \
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case 2: rd = xBX; break; \
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case 3: rd = xBX; break; \
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}
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#define emith_sh2_drc_entry() { \
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@ -43,9 +43,9 @@
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#define MAX_BLOCK_SIZE (BLOCK_INSN_LIMIT * 6 * 6)
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// max literal offset from the block end
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#define MAX_LITERAL_OFFSET 32*2
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#define MAX_LITERAL_OFFSET 0x200 // max. MOVA, MOV @(PC) offset
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#define MAX_LITERALS (BLOCK_INSN_LIMIT / 4)
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#define MAX_LOCAL_BRANCHES 32
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#define MAX_LOCAL_BRANCHES (BLOCK_INSN_LIMIT / 4)
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// debug stuff
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// 01 - warnings/errors
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@ -98,8 +98,10 @@ static int insns_compiled, hash_collisions, host_insn_count;
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#define BITMASK3(v0,v1,v2) (BITMASK2(v0,v1) | (1 << (v2)))
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#define BITMASK4(v0,v1,v2,v3) (BITMASK3(v0,v1,v2) | (1 << (v3)))
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#define BITMASK5(v0,v1,v2,v3,v4) (BITMASK4(v0,v1,v2,v3) | (1 << (v4)))
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#define BITMASK6(v0,v1,v2,v3,v4,v5) (BITMASK5(v0,v1,v2,v3,v4) | (1 << (v5)))
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#define SHR_T SHR_SR // might make them separate someday
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#define SHR_T SHR_SR // might make them separate someday
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#define SHR_MEM 31
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static struct op_data {
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u8 op;
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@ -115,6 +117,7 @@ static struct op_data {
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enum op_types {
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OP_UNHANDLED = 0,
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OP_BRANCH,
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OP_BRANCH_N, // conditional known not to be taken
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OP_BRANCH_CT, // conditional, branch if T set
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OP_BRANCH_CF, // conditional, branch if T clear
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OP_BRANCH_R, // indirect
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@ -125,6 +128,8 @@ enum op_types {
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OP_MOVA,
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OP_SLEEP,
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OP_RTE,
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OP_TRAPA,
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OP_UNDEFINED,
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};
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#ifdef DRC_SH2
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@ -1672,6 +1677,9 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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tmp2 = ops[i-1].op == OP_BRANCH_CT ? DCOND_NE : DCOND_EQ;
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emith_move_r_imm_c(tmp2, tmp, ops[i-1].imm);
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break;
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case OP_BRANCH_N:
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emit_move_r_imm32(SHR_PC, pc);
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break;
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// case OP_BRANCH_R OP_BRANCH_RF - PC already loaded
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}
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}
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@ -1684,6 +1692,9 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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switch (opd->op)
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{
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case OP_BRANCH_N:
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goto end_op;
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case OP_BRANCH:
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case OP_BRANCH_CT:
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case OP_BRANCH_CF:
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@ -1734,6 +1745,32 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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drcf.pending_branch_indirect = 1;
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goto end_op;
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case OP_UNDEFINED:
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elprintf_sh2(sh2, EL_ANOMALY,
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"drc: illegal op %04x @ %08x", op, pc - 2);
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opd->imm = 4;
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// fallthrough
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case OP_TRAPA:
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tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
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emith_sub_r_imm(tmp, 4*2);
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// push SR
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tmp = rcache_get_reg_arg(0, SHR_SP);
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emith_add_r_imm(tmp, 4);
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tmp = rcache_get_reg_arg(1, SHR_SR);
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emith_clear_msb(tmp, tmp, 22);
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emit_memhandler_write(2);
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// push PC
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rcache_get_reg_arg(0, SHR_SP);
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tmp = rcache_get_tmp_arg(1);
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emith_move_r_imm(tmp, pc);
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emit_memhandler_write(2);
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// obtain new PC
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emit_memhandler_read_rr(SHR_PC, SHR_VBR, opd->imm * 4, 2);
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// indirect jump -> back to dispatcher
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rcache_flush();
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emith_jump(sh2_drc_dispatcher);
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goto end_op;
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case OP_LOAD_POOL:
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#if PROPAGATE_CONSTANTS
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if (opd->imm != 0 && opd->imm < end_literals
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@ -2610,26 +2647,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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tmp = (op & 0x300) >> 8;
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emit_memhandler_read_rr(SHR_R0, SHR_GBR, (op & 0xff) << tmp, tmp);
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goto end_op;
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case 0x0300: // TRAPA #imm 11000011iiiiiiii
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tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
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emith_sub_r_imm(tmp, 4*2);
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// push SR
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tmp = rcache_get_reg_arg(0, SHR_SP);
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emith_add_r_imm(tmp, 4);
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tmp = rcache_get_reg_arg(1, SHR_SR);
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emith_clear_msb(tmp, tmp, 22);
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emit_memhandler_write(2);
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// push PC
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rcache_get_reg_arg(0, SHR_SP);
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tmp = rcache_get_tmp_arg(1);
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emith_move_r_imm(tmp, pc);
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emit_memhandler_write(2);
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// obtain new PC
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emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2);
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// indirect jump -> back to dispatcher
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rcache_flush();
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emith_jump(sh2_drc_dispatcher);
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goto end_op;
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case 0x0800: // TST #imm,R0 11001000iiiiiiii
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tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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@ -3446,13 +3463,15 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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u16 *dr_pc_base;
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u32 pc, op, tmp;
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u32 end_pc, end_literals = 0;
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u32 lowest_literal = 0;
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u32 lowest_mova = 0;
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struct op_data *opd;
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int next_is_delay = 0;
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int end_block = 0;
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int i, i_end;
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memset(op_flags, 0, BLOCK_INSN_LIMIT);
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memset(op_flags, 0, sizeof(*op_flags) * BLOCK_INSN_LIMIT);
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op_flags[0] |= OF_BTARGET; // block start is always a target
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dr_pc_base = dr_get_pc_base(base_pc, is_slave);
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@ -3473,6 +3492,9 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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}
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else if (end_block || i >= BLOCK_INSN_LIMIT - 2)
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break;
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else if ((lowest_mova && lowest_mova <= pc) ||
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(lowest_literal && lowest_literal <= pc))
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break; // text area collides with data area
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op = FETCH_OP(pc);
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switch ((op & 0xf000) >> 12)
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@ -3506,18 +3528,22 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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// BSRF Rm 0000mmmm00000011
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opd->op = OP_BRANCH_RF;
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opd->rm = GET_Rn();
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opd->source = BITMASK1(opd->rm);
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opd->source = BITMASK2(SHR_PC, opd->rm);
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opd->dest = BITMASK1(SHR_PC);
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if (!(op & 0x20))
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opd->dest |= BITMASK1(SHR_PR);
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opd->cycles = 2;
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next_is_delay = 1;
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end_block = 1;
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if (!(opd->dest & BITMASK1(SHR_PR)))
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end_block = !(op_flags[i+1+next_is_delay] & OF_BTARGET);
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else
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op_flags[i+1+next_is_delay] |= OF_BTARGET;
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break;
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case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
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case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
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case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
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opd->source = BITMASK3(GET_Rm(), SHR_R0, GET_Rn());
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opd->dest = BITMASK1(SHR_MEM);
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break;
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case 0x07:
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// MUL.L Rm,Rn 0000nnnnmmmm0111
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@ -3594,7 +3620,7 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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opd->dest = BITMASK1(SHR_PC);
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opd->cycles = 2;
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next_is_delay = 1;
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end_block = 1;
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end_block = !(op_flags[i+1+next_is_delay] & OF_BTARGET);
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break;
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case 1: // SLEEP 0000000000011011
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opd->op = OP_SLEEP;
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@ -3603,10 +3629,10 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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case 2: // RTE 0000000000101011
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opd->op = OP_RTE;
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opd->source = BITMASK1(SHR_SP);
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opd->dest = BITMASK2(SHR_SR, SHR_PC);
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opd->dest = BITMASK3(SHR_SP, SHR_SR, SHR_PC);
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opd->cycles = 4;
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next_is_delay = 1;
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end_block = 1;
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end_block = !(op_flags[i+1+next_is_delay] & OF_BTARGET);
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break;
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default:
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goto undefined;
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@ -3615,11 +3641,11 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
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case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
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case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
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opd->source = BITMASK2(GET_Rm(), SHR_R0);
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opd->source = BITMASK3(GET_Rm(), SHR_R0, SHR_MEM);
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opd->dest = BITMASK1(GET_Rn());
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break;
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case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
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opd->source = BITMASK5(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH);
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opd->source = BITMASK6(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH, SHR_MEM);
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opd->dest = BITMASK4(GET_Rm(), GET_Rn(), SHR_MACL, SHR_MACH);
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opd->cycles = 3;
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break;
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@ -3631,8 +3657,8 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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/////////////////////////////////////////////
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case 0x01:
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// MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
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opd->source = BITMASK1(GET_Rm());
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opd->source = BITMASK1(GET_Rn());
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opd->source = BITMASK2(GET_Rm(), GET_Rn());
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opd->dest = BITMASK1(SHR_MEM);
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opd->imm = (op & 0x0f) * 4;
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break;
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@ -3643,14 +3669,14 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
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case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
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case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
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opd->source = BITMASK1(GET_Rm());
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opd->source = BITMASK1(GET_Rn());
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opd->source = BITMASK2(GET_Rm(), GET_Rn());
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opd->dest = BITMASK1(SHR_MEM);
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break;
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case 0x04: // MOV.B Rm,@-Rn 0010nnnnmmmm0100
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case 0x05: // MOV.W Rm,@-Rn 0010nnnnmmmm0101
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case 0x06: // MOV.L Rm,@-Rn 0010nnnnmmmm0110
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opd->source = BITMASK2(GET_Rm(), GET_Rn());
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opd->dest = BITMASK1(GET_Rn());
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opd->dest = BITMASK2(GET_Rn(), SHR_MEM);
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break;
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case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
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opd->source = BITMASK2(GET_Rm(), GET_Rn());
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@ -3791,7 +3817,7 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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goto undefined;
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}
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opd->source = BITMASK2(GET_Rn(), tmp);
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opd->dest = BITMASK1(GET_Rn());
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opd->dest = BITMASK2(GET_Rn(), SHR_MEM);
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break;
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case 0x04:
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case 0x05:
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@ -3843,7 +3869,7 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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default:
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goto undefined;
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}
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opd->source = BITMASK1(GET_Rn());
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opd->source = BITMASK2(GET_Rn(), SHR_MEM);
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opd->dest = BITMASK2(GET_Rn(), tmp);
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break;
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case 0x08:
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@ -3899,11 +3925,14 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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opd->dest |= BITMASK1(SHR_PC);
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opd->cycles = 2;
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next_is_delay = 1;
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end_block = 1;
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if (!(opd->dest & BITMASK1(SHR_PR)))
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end_block = !(op_flags[i+1+next_is_delay] & OF_BTARGET);
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else
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op_flags[i+1+next_is_delay] |= OF_BTARGET;
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break;
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case 1: // TAS.B @Rn 0100nnnn00011011
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opd->source = BITMASK1(GET_Rn());
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opd->dest = BITMASK1(SHR_T);
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opd->source = BITMASK2(GET_Rn(), SHR_MEM);
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opd->dest = BITMASK2(SHR_T, SHR_MEM);
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opd->cycles = 4;
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break;
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default:
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@ -3931,7 +3960,7 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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break;
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case 0x0f:
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// MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
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opd->source = BITMASK5(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH);
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opd->source = BITMASK6(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH, SHR_MEM);
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opd->dest = BITMASK4(GET_Rm(), GET_Rn(), SHR_MACL, SHR_MACH);
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opd->cycles = 3;
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break;
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@ -3943,7 +3972,7 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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/////////////////////////////////////////////
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case 0x05:
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// MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
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opd->source = BITMASK1(GET_Rm());
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opd->source = BITMASK2(GET_Rm(), SHR_MEM);
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opd->dest = BITMASK1(GET_Rn());
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opd->imm = (op & 0x0f) * 4;
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break;
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@ -3955,12 +3984,14 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
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case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
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case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
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opd->dest = BITMASK1(GET_Rm());
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opd->dest = BITMASK2(GET_Rm(), GET_Rn());
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opd->source = BITMASK2(GET_Rm(), SHR_MEM);
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break;
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case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
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case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
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case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
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opd->source = BITMASK1(GET_Rm());
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opd->dest |= BITMASK1(GET_Rn());
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opd->dest = BITMASK1(GET_Rn());
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opd->source = BITMASK2(GET_Rm(), SHR_MEM);
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break;
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case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
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opd->source = BITMASK2(GET_Rm(), SHR_T);
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@ -3997,19 +4028,21 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
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{
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case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
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opd->source = BITMASK2(GET_Rm(), SHR_R0);
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opd->dest = BITMASK1(SHR_MEM);
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opd->imm = (op & 0x0f);
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break;
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case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
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opd->source = BITMASK2(GET_Rm(), SHR_R0);
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opd->dest = BITMASK1(SHR_MEM);
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opd->imm = (op & 0x0f) * 2;
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break;
|
||||
case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
|
||||
opd->source = BITMASK1(GET_Rm());
|
||||
opd->source = BITMASK2(GET_Rm(), SHR_MEM);
|
||||
opd->dest = BITMASK1(SHR_R0);
|
||||
opd->imm = (op & 0x0f);
|
||||
break;
|
||||
case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
|
||||
opd->source = BITMASK1(GET_Rm());
|
||||
opd->source = BITMASK2(GET_Rm(), SHR_MEM);
|
||||
opd->dest = BITMASK1(SHR_R0);
|
||||
opd->imm = (op & 0x0f) * 2;
|
||||
break;
|
||||
|
|
@ -4025,7 +4058,7 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
case 0x0900: // BT label 10001001dddddddd
|
||||
case 0x0b00: // BF label 10001011dddddddd
|
||||
opd->op = (op & 0x0200) ? OP_BRANCH_CF : OP_BRANCH_CT;
|
||||
opd->source = BITMASK1(SHR_T);
|
||||
opd->source = BITMASK2(SHR_PC, SHR_T);
|
||||
opd->dest = BITMASK1(SHR_PC);
|
||||
opd->imm = ((signed int)(op << 24) >> 23);
|
||||
opd->imm += pc + 4;
|
||||
|
|
@ -4045,13 +4078,16 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
if (op_flags[i] & OF_DELAY_OP) {
|
||||
if (ops[i-1].op == OP_BRANCH)
|
||||
tmp = ops[i-1].imm;
|
||||
else
|
||||
else if (ops[i-1].op != OP_BRANCH_N)
|
||||
tmp = 0;
|
||||
}
|
||||
opd->source = BITMASK1(SHR_PC);
|
||||
opd->source = BITMASK2(SHR_PC, SHR_MEM);
|
||||
opd->dest = BITMASK1(GET_Rn());
|
||||
if (tmp)
|
||||
if (tmp) {
|
||||
opd->imm = tmp + 2 + (op & 0xff) * 2;
|
||||
if (lowest_literal == 0 || opd->imm < lowest_literal)
|
||||
lowest_literal = opd->imm;
|
||||
}
|
||||
opd->size = 1;
|
||||
break;
|
||||
|
||||
|
|
@ -4062,14 +4098,21 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
case 0x0a:
|
||||
// BRA label 1010dddddddddddd
|
||||
opd->op = OP_BRANCH;
|
||||
opd->source = BITMASK1(SHR_PC);
|
||||
opd->dest |= BITMASK1(SHR_PC);
|
||||
opd->imm = ((signed int)(op << 20) >> 19);
|
||||
opd->imm += pc + 4;
|
||||
opd->cycles = 2;
|
||||
next_is_delay = 1;
|
||||
end_block = 1;
|
||||
if (base_pc <= opd->imm && opd->imm < base_pc + BLOCK_INSN_LIMIT * 2)
|
||||
op_flags[(opd->imm - base_pc) / 2] |= OF_BTARGET;
|
||||
if (!(opd->dest & BITMASK1(SHR_PR))) {
|
||||
if (base_pc <= opd->imm && opd->imm < base_pc + BLOCK_INSN_LIMIT * 2) {
|
||||
op_flags[(opd->imm - base_pc) / 2] |= OF_BTARGET;
|
||||
if (opd->imm <= pc)
|
||||
end_block = !(op_flags[i+1+next_is_delay] & OF_BTARGET);
|
||||
} else
|
||||
end_block = !(op_flags[i+1+next_is_delay] & OF_BTARGET);
|
||||
} else
|
||||
op_flags[i+1+next_is_delay] |= OF_BTARGET;
|
||||
break;
|
||||
|
||||
/////////////////////////////////////////////
|
||||
|
|
@ -4080,23 +4123,25 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
|
||||
case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
|
||||
opd->source = BITMASK2(SHR_GBR, SHR_R0);
|
||||
opd->dest = BITMASK1(SHR_MEM);
|
||||
opd->size = (op & 0x300) >> 8;
|
||||
opd->imm = (op & 0xff) << opd->size;
|
||||
break;
|
||||
case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
|
||||
case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
|
||||
case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
|
||||
opd->source = BITMASK1(SHR_GBR);
|
||||
opd->source = BITMASK2(SHR_GBR, SHR_MEM);
|
||||
opd->dest = BITMASK1(SHR_R0);
|
||||
opd->size = (op & 0x300) >> 8;
|
||||
opd->imm = (op & 0xff) << opd->size;
|
||||
break;
|
||||
case 0x0300: // TRAPA #imm 11000011iiiiiiii
|
||||
opd->source = BITMASK2(SHR_PC, SHR_SR);
|
||||
opd->dest = BITMASK1(SHR_PC);
|
||||
opd->imm = (op & 0xff) * 4;
|
||||
opd->op = OP_TRAPA;
|
||||
opd->source = BITMASK3(SHR_SP, SHR_PC, SHR_SR);
|
||||
opd->dest = BITMASK2(SHR_SP, SHR_PC);
|
||||
opd->imm = (op & 0xff);
|
||||
opd->cycles = 8;
|
||||
end_block = 1; // FIXME
|
||||
op_flags[i+1] |= OF_BTARGET;
|
||||
break;
|
||||
case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
|
||||
opd->op = OP_MOVA;
|
||||
|
|
@ -4104,7 +4149,7 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
if (op_flags[i] & OF_DELAY_OP) {
|
||||
if (ops[i-1].op == OP_BRANCH)
|
||||
tmp = ops[i-1].imm;
|
||||
else
|
||||
else if (ops[i-1].op != OP_BRANCH_N)
|
||||
tmp = 0;
|
||||
}
|
||||
opd->dest = BITMASK1(SHR_R0);
|
||||
|
|
@ -4134,7 +4179,7 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
opd->imm = op & 0xff;
|
||||
break;
|
||||
case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
|
||||
opd->source = BITMASK2(SHR_GBR, SHR_R0);
|
||||
opd->source = BITMASK3(SHR_GBR, SHR_R0, SHR_MEM);
|
||||
opd->dest = BITMASK1(SHR_T);
|
||||
opd->imm = op & 0xff;
|
||||
opd->cycles = 3;
|
||||
|
|
@ -4142,7 +4187,8 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
|
||||
case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
|
||||
case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
|
||||
opd->source = BITMASK2(SHR_GBR, SHR_R0);
|
||||
opd->source = BITMASK3(SHR_GBR, SHR_R0, SHR_MEM);
|
||||
opd->dest = BITMASK1(SHR_MEM);
|
||||
opd->imm = op & 0xff;
|
||||
opd->cycles = 3;
|
||||
break;
|
||||
|
|
@ -4159,13 +4205,16 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
if (op_flags[i] & OF_DELAY_OP) {
|
||||
if (ops[i-1].op == OP_BRANCH)
|
||||
tmp = ops[i-1].imm;
|
||||
else
|
||||
else if (ops[i-1].op != OP_BRANCH_N)
|
||||
tmp = 0;
|
||||
}
|
||||
opd->source = BITMASK1(SHR_PC);
|
||||
opd->source = BITMASK2(SHR_PC, SHR_MEM);
|
||||
opd->dest = BITMASK1(GET_Rn());
|
||||
if (tmp)
|
||||
if (tmp) {
|
||||
opd->imm = (tmp + 2 + (op & 0xff) * 4) & ~3;
|
||||
if (lowest_literal == 0 || opd->imm < lowest_literal)
|
||||
lowest_literal = opd->imm;
|
||||
}
|
||||
opd->size = 2;
|
||||
break;
|
||||
|
||||
|
|
@ -4180,6 +4229,10 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
undefined:
|
||||
elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
|
||||
is_slave ? 's' : 'm', op, pc);
|
||||
opd->op = OP_UNDEFINED;
|
||||
// an unhandled instruction is probably not code if it's not the 1st insn
|
||||
if (!(op_flags[i] & OF_DELAY_OP) && pc != base_pc)
|
||||
goto end;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -4199,10 +4252,12 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
}
|
||||
}
|
||||
}
|
||||
end:
|
||||
i_end = i;
|
||||
end_pc = pc;
|
||||
|
||||
// 2nd pass: some analysis
|
||||
lowest_literal = end_literals = lowest_mova = 0;
|
||||
for (i = 0; i < i_end; i++) {
|
||||
opd = &ops[i];
|
||||
|
||||
|
|
@ -4217,22 +4272,39 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
else
|
||||
op_flags[i + 1] |= op_flags[i] & (OF_T_SET | OF_T_CLEAR);
|
||||
|
||||
if ((opd->op == OP_BRANCH_CT && (op_flags[i] & OF_T_SET))
|
||||
|| (opd->op == OP_BRANCH_CF && (op_flags[i] & OF_T_CLEAR)))
|
||||
{
|
||||
if ((opd->op == OP_BRANCH_CT && (op_flags[i] & OF_T_CLEAR)) ||
|
||||
(opd->op == OP_BRANCH_CF && (op_flags[i] & OF_T_SET)))
|
||||
opd->op = OP_BRANCH_N;
|
||||
else if ((opd->op == OP_BRANCH_CT && (op_flags[i] & OF_T_SET)) ||
|
||||
(opd->op == OP_BRANCH_CF && (op_flags[i] & OF_T_CLEAR))) {
|
||||
opd->op = OP_BRANCH;
|
||||
opd->cycles = 3;
|
||||
i_end = i + 1;
|
||||
if (op_flags[i + 1] & OF_DELAY_OP) {
|
||||
if (op_flags[i + 1] & OF_DELAY_OP)
|
||||
opd->cycles = 2;
|
||||
i_end++;
|
||||
else
|
||||
opd->cycles = 3;
|
||||
}
|
||||
// "overscan" detection: unreachable code after unconditional branch
|
||||
// this can happen if the insn after a forward branch isn't a local target
|
||||
if (opd->op == OP_BRANCH || opd->op == OP_BRANCH_R || opd->op == OP_BRANCH_RF) {
|
||||
if (op_flags[i + 1] & OF_DELAY_OP) {
|
||||
if (i_end > i + 2 && !(op_flags[i + 2] & OF_BTARGET))
|
||||
i_end = i + 2;
|
||||
} else {
|
||||
if (i_end > i + 1 && !(op_flags[i + 1] & OF_BTARGET))
|
||||
i_end = i + 1;
|
||||
}
|
||||
}
|
||||
else if (opd->op == OP_LOAD_POOL)
|
||||
{
|
||||
if (opd->imm < end_pc + MAX_LITERAL_OFFSET) {
|
||||
|
||||
// literal pool size detection
|
||||
if (opd->op == OP_MOVA && opd->imm >= base_pc)
|
||||
if (lowest_mova == 0 || opd->imm < lowest_mova)
|
||||
lowest_mova = opd->imm;
|
||||
if (opd->op == OP_LOAD_POOL) {
|
||||
if (opd->imm >= base_pc && opd->imm < end_pc + MAX_LITERAL_OFFSET) {
|
||||
if (end_literals < opd->imm + opd->size * 2)
|
||||
end_literals = opd->imm + opd->size * 2;
|
||||
if (lowest_literal == 0 || lowest_literal > opd->imm)
|
||||
lowest_literal = opd->imm;
|
||||
if (opd->size == 2) {
|
||||
// tweak for NFL: treat a 32bit literal as an address and check if it
|
||||
// points to the literal space. In that case handle it like MOVA.
|
||||
|
|
@ -4245,26 +4317,31 @@ void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
|
|||
}
|
||||
}
|
||||
end_pc = base_pc + i_end * 2;
|
||||
if (end_literals < end_pc)
|
||||
end_literals = end_pc;
|
||||
|
||||
// end_literals is used to decide to inline a literal or not
|
||||
// XXX: need better detection if this actually is used in write
|
||||
if (lowest_literal >= base_pc) {
|
||||
if (lowest_literal < end_pc) {
|
||||
dbg(1, "warning: lowest_literal=%08x < end_pc=%08x", lowest_literal, end_pc);
|
||||
// TODO: does this always mean end_pc covers data?
|
||||
}
|
||||
}
|
||||
if (lowest_mova >= base_pc) {
|
||||
if (lowest_mova < end_literals) {
|
||||
dbg(1, "mova for %08x, block %08x", lowest_mova, base_pc);
|
||||
end_literals = end_pc;
|
||||
dbg(1, "warning: mova=%08x < end_literals=%08x", lowest_mova, end_literals);
|
||||
end_literals = lowest_mova;
|
||||
}
|
||||
if (lowest_mova < end_pc) {
|
||||
dbg(1, "warning: mova inside of blk for %08x, block %08x",
|
||||
lowest_mova, base_pc);
|
||||
dbg(1, "warning: mova=%08x < end_pc=%08x", lowest_mova, end_pc);
|
||||
end_literals = end_pc;
|
||||
}
|
||||
}
|
||||
if (lowest_literal >= end_literals)
|
||||
lowest_literal = end_literals;
|
||||
|
||||
*end_pc_out = end_pc;
|
||||
if (end_literals_out != NULL)
|
||||
*end_literals_out = end_literals;
|
||||
*end_literals_out = (end_literals ?: end_pc);
|
||||
}
|
||||
|
||||
// vim:shiftwidth=2:ts=2:expandtab
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue