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vdp fifo speed optimization
This commit is contained in:
kub
parent
20fafa7127
commit
c55a44a88c
5 changed files with 210 additions and 125 deletions
129
pico/misc.c
129
pico/misc.c
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@ -48,6 +48,135 @@ const unsigned char hcounts_32[] = {
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0x82,0x83,0x83,0x84,0x85,0x85,0x86,0x87,0x87,0x88,0x89,0x8a,0x8a,0x8b,0x8c,0x8c,
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};
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// VDP transfer slots for blanked and active display in 32col and 40col mode.
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// 1 slot is 488/171 = 2.8538 68k cycles in h32, and 488/210 = 2.3238 in h40
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// In blanked display, all slots but 5(h32) / 6(h40) are usable for transfers,
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// in active display only 16(h32) / 18(h40) slots can be used.
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// XXX inactive tables by slot#=cycles*maxslot#/488. should be through hv tables
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// VDP transfer slots in inactive (blanked) display 32col mode.
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// refresh slots: 250, 26, 58, 90, 122 -> 32, 64, 96, 128, 160
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const unsigned char vdpcyc2sl_32_bl[] = { // 68k cycles/2 to slot #
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// 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
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0, 0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10,
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10, 11, 12, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 19, 20, 21,
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21, 22, 23, 23, 24, 25, 25, 26, 27, 27, 28, 29, 29, 30, 31, 31,
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32, 33, 34, 34, 35, 36, 36, 37, 38, 38, 39, 40, 40, 41, 42, 42,
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43, 44, 44, 45, 46, 46, 47, 48, 48, 49, 50, 51, 51, 52, 53, 53,
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54, 55, 55, 56, 57, 57, 58, 59, 59, 60, 61, 61, 62, 63, 63, 64,
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65, 65, 66, 67, 68, 68, 69, 70, 70, 71, 72, 72, 73, 74, 74, 75,
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76, 76, 77, 78, 78, 79, 80, 80, 81, 82, 83, 83, 84, 85, 85, 86,
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87, 87, 88, 89, 89, 90, 91, 91, 92, 93, 93, 94, 95, 95, 96, 97,
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97, 98, 99,100,100,101,102,102,103,104,104,105,106,106,107,108,
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108,109,110,110,111,112,112,113,114,114,115,116,117,117,118,119,
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119,120,121,121,122,123,123,124,125,125,126,127,127,128,129,129,
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130,131,131,132,133,134,134,135,136,136,137,138,138,139,140,140,
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141,142,142,143,144,144,145,146,146,147,148,148,149,150,151,151,
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152,153,153,154,155,155,156,157,157,158,159,159,160,161,161,162,
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163,163,164,165,166,166,167,168,168,169,170,170,171,172,172,173,
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};
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// VDP transfer slots in inactive (blanked) display 40col mode.
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// refresh slots: 250, 26, 58, 90, 122, 154 -> 40, 72, 104, 136, 168, 200
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const unsigned char vdpcyc2sl_40_bl[] = { // 68k cycles/2 to slot #
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// 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
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0, 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 10, 10, 11, 12,
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13, 14, 15, 15, 16, 17, 18, 19, 20, 20, 21, 22, 23, 24, 25, 25,
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26, 27, 28, 29, 30, 30, 31, 32, 33, 34, 35, 35, 36, 37, 38, 39,
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40, 40, 41, 42, 43, 44, 45, 45, 46, 47, 48, 49, 50, 51, 51, 52,
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53, 54, 55, 56, 56, 57, 58, 59, 60, 61, 61, 62, 63, 64, 65, 66,
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66, 67, 68, 69, 70, 71, 71, 72, 73, 74, 75, 76, 76, 77, 78, 79,
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80, 81, 81, 82, 83, 84, 85, 86, 86, 87, 88, 89, 90, 91, 91, 92,
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93, 94, 95, 96, 96, 97, 98, 99,100,101,102,102,103,104,105,106,
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107,107,108,109,110,111,112,112,113,114,115,116,117,117,118,119,
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120,121,122,122,123,124,125,126,127,127,128,129,130,131,132,132,
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133,134,135,136,137,137,138,139,140,141,142,142,143,144,145,146,
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147,147,148,149,150,151,152,153,153,154,155,156,157,158,158,159,
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160,161,162,163,163,164,165,166,167,168,168,169,170,171,172,173,
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173,174,175,176,177,178,178,179,180,181,182,183,183,184,185,186,
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187,188,188,189,190,191,192,193,193,194,195,196,197,198,198,199,
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200,201,202,203,204,204,205,206,207,208,209,209,210,211,212,213,
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};
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// VDP transfer slots in active display 32col mode. Transfer slots (Hint=0):
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// 11,25,40,48,56,72,80,88,104,112,120,136,144,152,167,168
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const unsigned char vdpcyc2sl_32[] = { // 68k cycles/2 to slot #
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// 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
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6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 8, 8, 8,
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8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
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8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 10,
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10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11,
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11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,
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11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 13, 13, 13,
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13, 13, 13, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14,
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14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 15,
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16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
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};
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// VDP transfer slots in active display 40col mode. Transfer slots (Hint=0):
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// 21,47,55,63,79,87,95,111,119,127,143,151,159,175,183,191,206,207
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const unsigned char vdpcyc2sl_40[] = { // 68k cycles/2 to slot #
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// 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0
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0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, // 32
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 64
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1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, // 96
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3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, // 128
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4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, // 160
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5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 7, 7, // 192
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, // 224
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7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, // 256
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9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, // 288
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10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 12, // 320
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12, 12, 12, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, // 352
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13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, // 384
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14, 14, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 16, 16, 16, // 416
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16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 17, // 448
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18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, // 480
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};
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// XXX inactive tables by cyc=slot#*488/maxslot#. should be through hv tables
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const unsigned short vdpsl2cyc_32_bl[] = { // slot # to 68k cycles/2
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0, 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18, 20, 21, 23,
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24, 25, 27, 28, 30, 31, 33, 34, 36, 37, 39, 40, 42, 43, 45, 46,
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48, 49, 50, 52, 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70,
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71, 73, 74, 75, 77, 78, 80, 81, 83, 84, 86, 87, 89, 90, 92, 93,
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95, 96, 98, 99,100,102,103,105,106,108,109,111,112,114,115,117,
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118,120,121,122,124,125,127,128,130,131,133,134,136,137,139,140,
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142,143,145,146,147,149,150,152,153,155,156,158,159,161,162,164,
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165,167,168,170,171,172,174,175,177,178,180,181,183,184,186,187,
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189,190,192,193,195,196,197,199,200,202,203,205,206,208,209,211,
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212,214,215,217,218,220,221,222,224,225,227,228,230,231,233,234,
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236,237,239,240,242,243,244,246,
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};
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const unsigned short vdpsl2cyc_40_bl[] = { // slot # to 68k cycles/2
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0, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18,
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20, 21, 22, 23, 24, 26, 27, 28, 29, 30, 32, 33, 34, 35, 36, 38,
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39, 40, 41, 42, 44, 45, 46, 47, 48, 50, 51, 52, 53, 54, 56, 57,
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58, 59, 60, 61, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 75, 76,
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77, 78, 79, 81, 82, 83, 84, 85, 87, 88, 89, 90, 91, 93, 94, 95,
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96, 97, 99,100,101,102,103,105,106,107,108,109,111,112,113,114,
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115,117,118,119,120,121,122,124,125,126,127,128,130,131,132,133,
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134,136,137,138,139,140,142,143,144,145,146,148,149,150,151,152,
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154,155,156,157,158,160,161,162,163,164,166,167,168,169,170,172,
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173,174,175,176,178,179,180,181,182,183,185,186,187,188,189,191,
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192,193,194,195,197,198,199,200,201,203,204,205,206,207,209,210,
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211,212,213,215,216,217,218,219,221,222,223,224,225,227,228,229,
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230,231,233,234,235,236,237,239,240,241,242,243,244,246,
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};
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const unsigned short vdpsl2cyc_32[] = { // slot # to 68k cycles/2
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0, 16, 36, 56, 67, 79,102,113,125,148,159,171,194,205,217,239,
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240,260
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};
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const unsigned short vdpsl2cyc_40[] = { // slot # to 68k cycles/2
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0, 24, 55, 64, 73, 92,101,110,129,138,147,166,175,184,203,212,
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221,239,240,268
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};
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#ifndef _ASM_MISC_C
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PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count)
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{
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@ -79,6 +79,7 @@ void PicoPower(void)
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Pico.video.reg[0] = Pico.video.reg[1] = 0x04;
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Pico.video.reg[0xc] = 0x81;
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Pico.video.reg[0xf] = 0x02;
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PicoVideoFIFOMode(0, 1);
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if (PicoIn.AHW & PAHW_MCD)
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PicoPowerMCD();
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@ -179,6 +179,7 @@ static int PicoFrameHints(void)
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}
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pv->status |= SR_VB | PVS_VB2; // go into vblank
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PicoVideoFIFOMode(pv->reg[1]&0x40, pv->reg[12]&1);
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// the following SekRun is there for several reasons:
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// there must be a delay after vblank bit is set and irq is asserted (Mazin Saga)
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@ -270,6 +271,7 @@ static int PicoFrameHints(void)
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pv->status &= ~(SR_VB | PVS_VB2);
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pv->status |= ((pv->reg[1] >> 3) ^ SR_VB) & SR_VB; // forced blanking
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PicoVideoFIFOMode(pv->reg[1]&0x40, pv->reg[12]&1);
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// last scanline
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Pico.m.scanline = y++;
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@ -299,6 +299,8 @@ extern SH2 sh2s[2];
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#define PVS_CPUWR (1 << 18) // CPU write blocked by FIFO full
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#define PVS_CPURD (1 << 19) // CPU read blocked by FIFO not empty
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#define PVS_DMAFILL (1 << 20) // DMA fill is waiting for fill data
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#define PVS_DMABG (1 << 21) // background DMA operation is running
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#define PVS_FIFORUN (1 << 22) // FIFO is processing
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struct PicoVideo
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{
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@ -858,6 +860,7 @@ unsigned char PicoVideoRead8HV_L(void);
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extern int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned int *mask);
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void PicoVideoFIFOSync(int cycles);
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int PicoVideoFIFOHint(void);
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void PicoVideoFIFOMode(int active, int h40);
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int PicoVideoFIFOWrite(int count, int byte_p, unsigned sr_mask, unsigned sr_flags);
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void PicoVideoSave(void);
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void PicoVideoLoad(void);
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200
pico/videoport.c
200
pico/videoport.c
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@ -12,8 +12,11 @@
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#define NEED_DMA_SOURCE
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#include "memory.h"
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extern const unsigned char hcounts_32[];
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extern const unsigned char hcounts_40[];
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extern const unsigned char hcounts_32[], hcounts_40[];
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extern const unsigned char vdpcyc2sl_32_bl[], vdpcyc2sl_40_bl[];
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extern const unsigned char vdpcyc2sl_32[], vdpcyc2sl_40[];
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extern const unsigned short vdpsl2cyc_32_bl[], vdpsl2cyc_40_bl[];
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extern const unsigned short vdpsl2cyc_32[], vdpsl2cyc_40[];
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static int blankline; // display disabled for this line
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static unsigned sat; // VRAM addr of sprite attribute table
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@ -53,48 +56,6 @@ int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned
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* FIFORead executes a 68k read. 68k is blocked until the next transfer slot.
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*/
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// FIFO transfer slots per line: [active][h40]
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static const short vdpslots[2][2] = {{ 166, 204 },{ 16, 18 }};
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// mapping between slot# and 68k cycles in a blanked scanline [H32, H40]
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static const int vdpcyc2sl_bl[] = { (166<<16)/488, (204<<16)/488 };
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static const int vdpsl2cyc_bl[] = { (488<<16)/166, (488<<16)/204 };
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// VDP transfer slots in active display 32col mode. 1 slot is 488/171 = 2.8538
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// 68k cycles. Only 16 of the 171 slots in a scanline can be used by CPU/DMA:
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// (HINT=slot 0): 11,25,40,48,56,72,80,88,104,112,120,136,144,152,167,168
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static const unsigned char vdpcyc2sl_32[] = { // 68k cycles/4 to slot #
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// 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
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0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3,
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3, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 8, 8,
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8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9,10,
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10,10,10,10,10,11,11,11,11,11,11,11,11,11,11,11,
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11,12,12,12,12,12,13,13,13,13,13,13,14,14,14,14,
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14,14,14,14,14,14,14,15,16,16,16,16,16,16,16,16,
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};
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static const unsigned char vdpsl2cyc_32[] = { // slot # to 68k cycles/4
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0, 8, 18, 28, 33, 39, 51, 56, 62, 74, 79, 85, 97,102,108,119,120,130
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};
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// VDP transfer slots in active display 40col mode. 1 slot is 488/210 = 2.3238
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// 68k cycles. Only 18 of the 210 slots in a scanline can be used by CPU/DMA:
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// (HINT=0): 21,47,55,63,79,87,95,111,119,127,143,151,159,175,183,191,206,207,
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static const unsigned char vdpcyc2sl_40[] = { // 68k cycles/4 to slot #
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// 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2,
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3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5,
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5, 5, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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8, 8, 8, 8, 8, 9, 9, 9, 9,10,10,10,10,10,10,10,
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10,10,10,11,11,11,11,12,12,12,12,12,13,13,13,13,
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13,13,13,13,13,14,14,14,14,14,15,15,15,15,15,16,
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16,16,16,16,16,16,16,17,18,18,18,18,18,18,18,18,
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};
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static const unsigned char vdpsl2cyc_40[] = { // slot # to 68k cycles/4
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0, 12, 27, 32, 36, 46, 50, 55, 64, 69, 73, 83, 87, 92,101,106,111,119,120,134
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};
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// NB code assumes fifo_* arrays have size 2^n
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// last transferred FIFO data, ...x = index XXX currently only CPU
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static short fifo_data[4], fifo_dx; // XXX must go into save?
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@ -106,34 +67,10 @@ enum { FQ_BYTE = 1, FQ_BGDMA = 2, FQ_FGDMA = 4 }; // queue flags, NB: BYTE = 1!
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static unsigned int fifo_total; // total# of pending FIFO entries (w/o BGDMA)
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static unsigned short fifo_slot; // last executed slot in current scanline
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static unsigned short fifo_maxslot;// #slots in scanline
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// map cycles to FIFO slot
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static __inline int GetFIFOSlot(struct PicoVideo *pv, int cycles)
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{
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int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);
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int h40 = pv->reg[12] & 1;
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if (active) return (h40 ? vdpcyc2sl_40 : vdpcyc2sl_32)[cycles/4];
|
||||
else return (cycles * vdpcyc2sl_bl[h40] + cycles) >> 16;
|
||||
}
|
||||
|
||||
static __inline int GetMaxFIFOSlot(struct PicoVideo *pv)
|
||||
{
|
||||
int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);
|
||||
int h40 = pv->reg[12] & 1;
|
||||
|
||||
return vdpslots[active][h40];
|
||||
}
|
||||
|
||||
// map FIFO slot to cycles
|
||||
static __inline int GetFIFOCycles(struct PicoVideo *pv, int slot)
|
||||
{
|
||||
int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);
|
||||
int h40 = pv->reg[12] & 1;
|
||||
|
||||
if (active) return (h40 ? vdpsl2cyc_40 : vdpsl2cyc_32)[slot]*4;
|
||||
else return ((slot * vdpsl2cyc_bl[h40] + slot) >> 16);
|
||||
}
|
||||
static const unsigned char *fifo_cyc2sl;
|
||||
static const unsigned short *fifo_sl2cyc;
|
||||
|
||||
// do the FIFO math
|
||||
static __inline int AdvanceFIFOEntry(struct PicoVideo *pv, int slots)
|
||||
|
|
@ -149,20 +86,16 @@ static __inline int AdvanceFIFOEntry(struct PicoVideo *pv, int slots)
|
|||
|
||||
// if entry has been processed...
|
||||
if (pv->fifo_cnt == 0) {
|
||||
if (fifo_ql) {
|
||||
// terminate DMA if applicable
|
||||
if ((pv->status & SR_DMA) && (fifo_queue[fifo_qx] & FQ_BGDMA)) {
|
||||
pv->status &= ~SR_DMA;
|
||||
pv->command &= ~0x80;
|
||||
}
|
||||
// remove entry from FIFO
|
||||
// remove entry from FIFO
|
||||
if (fifo_ql)
|
||||
fifo_qx ++, fifo_qx &= 7, fifo_ql --;
|
||||
}
|
||||
// start processing for next entry if there is one
|
||||
if (fifo_ql)
|
||||
pv->fifo_cnt = (fifo_queue[fifo_qx] >> 3) << (fifo_queue[fifo_qx] & FQ_BYTE);
|
||||
else
|
||||
else { // FIFO empty
|
||||
pv->status &= ~PVS_FIFORUN;
|
||||
fifo_total = 0;
|
||||
}
|
||||
}
|
||||
return l;
|
||||
}
|
||||
|
|
@ -170,16 +103,20 @@ static __inline int AdvanceFIFOEntry(struct PicoVideo *pv, int slots)
|
|||
static __inline void SetFIFOState(struct PicoVideo *pv)
|
||||
{
|
||||
// release CPU and terminate DMA if FIFO isn't blocking the 68k anymore
|
||||
if (fifo_total == 0)
|
||||
pv->status &= ~PVS_CPURD;
|
||||
if (fifo_total <= 4) {
|
||||
int x = (fifo_qx + fifo_ql - 1) & 7;
|
||||
if ((pv->status & SR_DMA) && !(pv->status & PVS_DMAFILL) &&
|
||||
(!fifo_ql || !(fifo_queue[x] & FQ_BGDMA))) {
|
||||
pv->status &= ~PVS_CPUWR;
|
||||
if (!(pv->status & (PVS_DMABG|PVS_DMAFILL))) {
|
||||
pv->status &= ~SR_DMA;
|
||||
pv->command &= ~0x80;
|
||||
}
|
||||
pv->status &= ~PVS_CPUWR;
|
||||
}
|
||||
if (fifo_total == 0) {
|
||||
pv->status &= ~PVS_CPURD;
|
||||
// terminate DMA if applicable
|
||||
if (!(pv->status & (PVS_FIFORUN|PVS_DMAFILL))) {
|
||||
pv->status &= ~(SR_DMA|PVS_DMABG);
|
||||
pv->command &= ~0x80;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -190,7 +127,7 @@ void PicoVideoFIFOSync(int cycles)
|
|||
int slots, done;
|
||||
|
||||
// calculate #slots since last executed slot
|
||||
slots = GetFIFOSlot(pv, cycles) - fifo_slot;
|
||||
slots = fifo_cyc2sl[cycles>>1] - fifo_slot;
|
||||
|
||||
// advance FIFO queue by #done slots
|
||||
done = slots;
|
||||
|
|
@ -208,31 +145,28 @@ void PicoVideoFIFOSync(int cycles)
|
|||
int PicoVideoFIFODrain(int level, int cycles, int bgdma)
|
||||
{
|
||||
struct PicoVideo *pv = &Pico.video;
|
||||
int maxsl = GetMaxFIFOSlot(pv); // max xfer slots in this scanline
|
||||
unsigned ocyc = cycles;
|
||||
int burn = 0;
|
||||
|
||||
// process FIFO entries until low level is reached
|
||||
while (fifo_total > level && fifo_slot < maxsl &&
|
||||
while (fifo_total > level && fifo_slot < fifo_maxslot &&
|
||||
(!(fifo_queue[fifo_qx] & FQ_BGDMA) || bgdma)) {
|
||||
int b = fifo_queue[fifo_qx] & FQ_BYTE;
|
||||
int cnt = ((fifo_total-level) << b) - (pv->fifo_cnt & b);
|
||||
int last = fifo_slot;
|
||||
int slot = (pv->fifo_cnt < cnt ? pv->fifo_cnt : cnt) + last; // target slot
|
||||
unsigned ocyc = cycles;
|
||||
int slot = (pv->fifo_cnt<cnt ? pv->fifo_cnt:cnt) + fifo_slot; // target slot
|
||||
|
||||
if (slot > maxsl) {
|
||||
if (slot > fifo_maxslot) {
|
||||
// target in later scanline, advance to eol
|
||||
slot = maxsl;
|
||||
slot = fifo_maxslot;
|
||||
cycles = 488;
|
||||
} else {
|
||||
// advance FIFO to target slot and CPU to cycles at that slot
|
||||
cycles = GetFIFOCycles(pv, slot);
|
||||
cycles = fifo_sl2cyc[slot]<<1;
|
||||
}
|
||||
AdvanceFIFOEntry(pv, slot - fifo_slot);
|
||||
fifo_slot = slot;
|
||||
burn += cycles - ocyc;
|
||||
|
||||
AdvanceFIFOEntry(pv, slot - last);
|
||||
}
|
||||
burn = cycles - ocyc;
|
||||
|
||||
SetFIFOState(pv);
|
||||
|
||||
|
|
@ -246,17 +180,19 @@ int PicoVideoFIFORead(void)
|
|||
int lc = SekCyclesDone()-Pico.t.m68c_line_start;
|
||||
int burn = 0;
|
||||
|
||||
PicoVideoFIFOSync(lc);
|
||||
if (pv->fifo_cnt) {
|
||||
PicoVideoFIFOSync(lc);
|
||||
// advance FIFO and CPU until FIFO is empty
|
||||
burn = PicoVideoFIFODrain(0, lc, 1);
|
||||
lc += burn;
|
||||
}
|
||||
|
||||
// advance FIFO and CPU until FIFO is empty
|
||||
burn = PicoVideoFIFODrain(0, lc, 1);
|
||||
lc += burn;
|
||||
if (fifo_total > 0)
|
||||
pv->status |= PVS_CPURD; // target slot is in later scanline
|
||||
else {
|
||||
// use next VDP access slot for reading, block 68k until then
|
||||
fifo_slot = GetFIFOSlot(pv, lc) + 1;
|
||||
burn += GetFIFOCycles(pv, fifo_slot) - lc;
|
||||
fifo_slot = fifo_cyc2sl[lc>>1] + 1;
|
||||
burn += (fifo_sl2cyc[fifo_slot]<<1) - lc;
|
||||
}
|
||||
|
||||
return burn;
|
||||
|
|
@ -267,35 +203,41 @@ int PicoVideoFIFOWrite(int count, int flags, unsigned sr_mask,unsigned sr_flags)
|
|||
{
|
||||
struct PicoVideo *pv = &Pico.video;
|
||||
int lc = SekCyclesDone()-Pico.t.m68c_line_start;
|
||||
int burn = 0, x;
|
||||
int burn = 0, x, head = 0;
|
||||
|
||||
PicoVideoFIFOSync(lc);
|
||||
if (pv->fifo_cnt)
|
||||
PicoVideoFIFOSync(lc);
|
||||
pv->status = (pv->status & ~sr_mask) | sr_flags;
|
||||
|
||||
if (count && fifo_ql < 8) {
|
||||
// update FIFO state if it was empty
|
||||
if (fifo_ql == 0) {
|
||||
fifo_slot = GetFIFOSlot(pv, lc+9); // FIFO latency ~3 vdp slots
|
||||
fifo_slot = fifo_cyc2sl[(lc+8)>>1]; // FIFO latency ~3 vdp slots
|
||||
pv->fifo_cnt = count << (flags & FQ_BYTE);
|
||||
pv->status |= PVS_FIFORUN;
|
||||
}
|
||||
|
||||
// create xfer queue entry
|
||||
// determine queue position for entry
|
||||
x = (fifo_qx + fifo_ql - 1) & 7;
|
||||
if (fifo_ql && (fifo_queue[x] & FQ_BGDMA)) {
|
||||
// CPU FIFO writes have priority over a background DMA Fill/Copy
|
||||
fifo_queue[(x+1) & 7] = fifo_queue[x];
|
||||
if (fifo_ql == 1) {
|
||||
if (x == fifo_qx) { // overtaking to queue head?
|
||||
// XXX if interrupting a DMA fill, fill data changes
|
||||
int f = fifo_queue[x] & 7;
|
||||
fifo_queue[(x+1) & 7] = (pv->fifo_cnt >> (f & FQ_BYTE) << 3) | f;
|
||||
pv->fifo_cnt = count << (flags & FQ_BYTE);
|
||||
head = 1;
|
||||
}
|
||||
x = (x-1) & 7;
|
||||
}
|
||||
if (fifo_ql && (fifo_queue[x] & 7) == flags) {
|
||||
|
||||
// create xfer queue entry
|
||||
if (fifo_ql && !head && (fifo_queue[x] & 7) == flags) {
|
||||
// amalgamate entries if of same type
|
||||
fifo_queue[x] += (count << 3);
|
||||
if (fifo_ql == 1) pv->fifo_cnt += count << (flags & FQ_BYTE);
|
||||
if (x == fifo_qx) // modifiying fifo head, adjust count
|
||||
pv->fifo_cnt += count << (flags & FQ_BYTE);
|
||||
} else {
|
||||
fifo_ql ++;
|
||||
x = (x+1) & 7;
|
||||
|
|
@ -331,20 +273,25 @@ int PicoVideoFIFOHint(void)
|
|||
}
|
||||
|
||||
// switch FIFO mode between active/inactive display
|
||||
static void PicoVideoFIFOMode(int active)
|
||||
void PicoVideoFIFOMode(int active, int h40)
|
||||
{
|
||||
static const unsigned char *vdpcyc2sl[2][2] =
|
||||
{ {vdpcyc2sl_32_bl, vdpcyc2sl_40_bl} , {vdpcyc2sl_32, vdpcyc2sl_40} };
|
||||
static const unsigned short *vdpsl2cyc[2][2] =
|
||||
{ {vdpsl2cyc_32_bl, vdpsl2cyc_40_bl} , {vdpsl2cyc_32, vdpsl2cyc_40} };
|
||||
|
||||
struct PicoVideo *pv = &Pico.video;
|
||||
int h40 = pv->reg[12] & 1;
|
||||
int lc = SekCyclesDone() - Pico.t.m68c_line_start;
|
||||
active = active && !(pv->status & PVS_VB2);
|
||||
|
||||
PicoVideoFIFOSync(lc);
|
||||
if (fifo_maxslot)
|
||||
PicoVideoFIFOSync(lc);
|
||||
|
||||
if (fifo_ql) {
|
||||
// recalculate FIFO slot for new mode
|
||||
if (!(pv->status & SR_VB) && active)
|
||||
fifo_slot = (pv->reg[12]&1 ? vdpcyc2sl_40 : vdpcyc2sl_32)[lc/4];
|
||||
else fifo_slot = ((lc * vdpcyc2sl_bl[h40] + lc) >> 16);
|
||||
}
|
||||
fifo_cyc2sl = vdpcyc2sl[active][h40];
|
||||
fifo_sl2cyc = vdpsl2cyc[active][h40];
|
||||
// recalculate FIFO slot for new mode
|
||||
fifo_slot = fifo_cyc2sl[lc>>1]-1;
|
||||
fifo_maxslot = fifo_cyc2sl[488>>1];
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -459,7 +406,7 @@ static void DmaSlow(int len, unsigned int source)
|
|||
SekCyclesDone(), SekPc);
|
||||
|
||||
SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_FGDMA | (Pico.video.type == 1),
|
||||
0, SR_DMA| PVS_CPUWR));
|
||||
PVS_DMABG, SR_DMA | PVS_CPUWR));
|
||||
|
||||
if ((source & 0xe00000) == 0xe00000) { // Ram
|
||||
base = (u16 *)PicoMem.ram;
|
||||
|
|
@ -583,13 +530,13 @@ static void DmaCopy(int len)
|
|||
int source;
|
||||
elprintf(EL_VDPDMA, "DmaCopy len %i [%u]", len, SekCyclesDone());
|
||||
|
||||
// XXX implement VRAM 128k? Is this even working? xfer/count still FQ_BYTE?
|
||||
SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA | FQ_BYTE,
|
||||
PVS_CPUWR, SR_DMA));
|
||||
PVS_CPUWR, SR_DMA | PVS_DMABG));
|
||||
|
||||
source =Pico.video.reg[0x15];
|
||||
source|=Pico.video.reg[0x16]<<8;
|
||||
|
||||
// XXX implement VRAM 128k? Is this even working? count still in bytes?
|
||||
for (; len; len--)
|
||||
{
|
||||
vr[(u16)a] = vr[(u16)(source++)];
|
||||
|
|
@ -616,7 +563,7 @@ static NOINLINE void DmaFill(int data)
|
|||
elprintf(EL_VDPDMA, "DmaFill len %i inc %i [%u]", len, inc, SekCyclesDone());
|
||||
|
||||
SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA | (Pico.video.type == 1),
|
||||
PVS_CPUWR | PVS_DMAFILL, SR_DMA));
|
||||
PVS_CPUWR | PVS_DMAFILL, SR_DMA | PVS_DMABG));
|
||||
|
||||
switch (Pico.video.type)
|
||||
{
|
||||
|
|
@ -823,11 +770,13 @@ PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d)
|
|||
if (num == 0 && !(pvid->reg[0]&2) && (d&2))
|
||||
pvid->hv_latch = PicoVideoRead(0x08);
|
||||
if (num == 1 && ((pvid->reg[1]^d)&0x40)) {
|
||||
PicoVideoFIFOMode(d & 0x40);
|
||||
PicoVideoFIFOMode(d & 0x40, pvid->reg[12]&1);
|
||||
// handle line blanking before line rendering
|
||||
if (SekCyclesDone() - Pico.t.m68c_line_start <= 488-390)
|
||||
blankline = d&0x40 ? -1 : Pico.m.scanline;
|
||||
}
|
||||
if (num == 12 && ((pvid->reg[12]^d)&0x01))
|
||||
PicoVideoFIFOMode(pvid->reg[1]&0x40, d & 1);
|
||||
DrawSync(SekCyclesDone() - Pico.t.m68c_line_start <= 488-390);
|
||||
pvid->reg[num]=(unsigned char)d;
|
||||
switch (num)
|
||||
|
|
@ -1058,6 +1007,7 @@ void PicoVideoLoad(void)
|
|||
|
||||
// convert former dma_xfers (why was this in PicoMisc anyway?)
|
||||
if (Pico.m.dma_xfers) {
|
||||
pv->status = SR_DMA|PVS_FIFORUN;
|
||||
pv->fifo_cnt = Pico.m.dma_xfers * (pv->type == 1 ? 2 : 1);
|
||||
fifo_total = Pico.m.dma_xfers;
|
||||
Pico.m.dma_xfers = 0;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue