mirror of
https://github.com/RaySollium99/picodrive.git
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vdp fifo speed optimization
This commit is contained in:
kub
parent
20fafa7127
commit
c55a44a88c
5 changed files with 210 additions and 125 deletions
200
pico/videoport.c
200
pico/videoport.c
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@ -12,8 +12,11 @@
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#define NEED_DMA_SOURCE
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#include "memory.h"
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extern const unsigned char hcounts_32[];
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extern const unsigned char hcounts_40[];
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extern const unsigned char hcounts_32[], hcounts_40[];
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extern const unsigned char vdpcyc2sl_32_bl[], vdpcyc2sl_40_bl[];
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extern const unsigned char vdpcyc2sl_32[], vdpcyc2sl_40[];
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extern const unsigned short vdpsl2cyc_32_bl[], vdpsl2cyc_40_bl[];
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extern const unsigned short vdpsl2cyc_32[], vdpsl2cyc_40[];
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static int blankline; // display disabled for this line
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static unsigned sat; // VRAM addr of sprite attribute table
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@ -53,48 +56,6 @@ int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned
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* FIFORead executes a 68k read. 68k is blocked until the next transfer slot.
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*/
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// FIFO transfer slots per line: [active][h40]
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static const short vdpslots[2][2] = {{ 166, 204 },{ 16, 18 }};
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// mapping between slot# and 68k cycles in a blanked scanline [H32, H40]
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static const int vdpcyc2sl_bl[] = { (166<<16)/488, (204<<16)/488 };
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static const int vdpsl2cyc_bl[] = { (488<<16)/166, (488<<16)/204 };
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// VDP transfer slots in active display 32col mode. 1 slot is 488/171 = 2.8538
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// 68k cycles. Only 16 of the 171 slots in a scanline can be used by CPU/DMA:
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// (HINT=slot 0): 11,25,40,48,56,72,80,88,104,112,120,136,144,152,167,168
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static const unsigned char vdpcyc2sl_32[] = { // 68k cycles/4 to slot #
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// 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
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0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3,
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3, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 8, 8,
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8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9,10,
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10,10,10,10,10,11,11,11,11,11,11,11,11,11,11,11,
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11,12,12,12,12,12,13,13,13,13,13,13,14,14,14,14,
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14,14,14,14,14,14,14,15,16,16,16,16,16,16,16,16,
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};
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static const unsigned char vdpsl2cyc_32[] = { // slot # to 68k cycles/4
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0, 8, 18, 28, 33, 39, 51, 56, 62, 74, 79, 85, 97,102,108,119,120,130
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};
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// VDP transfer slots in active display 40col mode. 1 slot is 488/210 = 2.3238
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// 68k cycles. Only 18 of the 210 slots in a scanline can be used by CPU/DMA:
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// (HINT=0): 21,47,55,63,79,87,95,111,119,127,143,151,159,175,183,191,206,207,
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static const unsigned char vdpcyc2sl_40[] = { // 68k cycles/4 to slot #
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// 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2,
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3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5,
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5, 5, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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8, 8, 8, 8, 8, 9, 9, 9, 9,10,10,10,10,10,10,10,
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10,10,10,11,11,11,11,12,12,12,12,12,13,13,13,13,
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13,13,13,13,13,14,14,14,14,14,15,15,15,15,15,16,
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16,16,16,16,16,16,16,17,18,18,18,18,18,18,18,18,
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};
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static const unsigned char vdpsl2cyc_40[] = { // slot # to 68k cycles/4
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0, 12, 27, 32, 36, 46, 50, 55, 64, 69, 73, 83, 87, 92,101,106,111,119,120,134
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};
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// NB code assumes fifo_* arrays have size 2^n
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// last transferred FIFO data, ...x = index XXX currently only CPU
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static short fifo_data[4], fifo_dx; // XXX must go into save?
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@ -106,34 +67,10 @@ enum { FQ_BYTE = 1, FQ_BGDMA = 2, FQ_FGDMA = 4 }; // queue flags, NB: BYTE = 1!
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static unsigned int fifo_total; // total# of pending FIFO entries (w/o BGDMA)
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static unsigned short fifo_slot; // last executed slot in current scanline
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static unsigned short fifo_maxslot;// #slots in scanline
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// map cycles to FIFO slot
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static __inline int GetFIFOSlot(struct PicoVideo *pv, int cycles)
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{
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int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);
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int h40 = pv->reg[12] & 1;
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if (active) return (h40 ? vdpcyc2sl_40 : vdpcyc2sl_32)[cycles/4];
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else return (cycles * vdpcyc2sl_bl[h40] + cycles) >> 16;
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}
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static __inline int GetMaxFIFOSlot(struct PicoVideo *pv)
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{
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int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);
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int h40 = pv->reg[12] & 1;
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return vdpslots[active][h40];
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}
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// map FIFO slot to cycles
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static __inline int GetFIFOCycles(struct PicoVideo *pv, int slot)
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{
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int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);
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int h40 = pv->reg[12] & 1;
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if (active) return (h40 ? vdpsl2cyc_40 : vdpsl2cyc_32)[slot]*4;
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else return ((slot * vdpsl2cyc_bl[h40] + slot) >> 16);
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}
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static const unsigned char *fifo_cyc2sl;
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static const unsigned short *fifo_sl2cyc;
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// do the FIFO math
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static __inline int AdvanceFIFOEntry(struct PicoVideo *pv, int slots)
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@ -149,20 +86,16 @@ static __inline int AdvanceFIFOEntry(struct PicoVideo *pv, int slots)
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// if entry has been processed...
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if (pv->fifo_cnt == 0) {
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if (fifo_ql) {
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// terminate DMA if applicable
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if ((pv->status & SR_DMA) && (fifo_queue[fifo_qx] & FQ_BGDMA)) {
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pv->status &= ~SR_DMA;
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pv->command &= ~0x80;
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}
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// remove entry from FIFO
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// remove entry from FIFO
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if (fifo_ql)
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fifo_qx ++, fifo_qx &= 7, fifo_ql --;
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}
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// start processing for next entry if there is one
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if (fifo_ql)
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pv->fifo_cnt = (fifo_queue[fifo_qx] >> 3) << (fifo_queue[fifo_qx] & FQ_BYTE);
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else
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else { // FIFO empty
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pv->status &= ~PVS_FIFORUN;
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fifo_total = 0;
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}
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}
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return l;
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}
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@ -170,16 +103,20 @@ static __inline int AdvanceFIFOEntry(struct PicoVideo *pv, int slots)
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static __inline void SetFIFOState(struct PicoVideo *pv)
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{
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// release CPU and terminate DMA if FIFO isn't blocking the 68k anymore
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if (fifo_total == 0)
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pv->status &= ~PVS_CPURD;
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if (fifo_total <= 4) {
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int x = (fifo_qx + fifo_ql - 1) & 7;
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if ((pv->status & SR_DMA) && !(pv->status & PVS_DMAFILL) &&
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(!fifo_ql || !(fifo_queue[x] & FQ_BGDMA))) {
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pv->status &= ~PVS_CPUWR;
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if (!(pv->status & (PVS_DMABG|PVS_DMAFILL))) {
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pv->status &= ~SR_DMA;
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pv->command &= ~0x80;
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}
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pv->status &= ~PVS_CPUWR;
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}
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if (fifo_total == 0) {
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pv->status &= ~PVS_CPURD;
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// terminate DMA if applicable
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if (!(pv->status & (PVS_FIFORUN|PVS_DMAFILL))) {
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pv->status &= ~(SR_DMA|PVS_DMABG);
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pv->command &= ~0x80;
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}
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}
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}
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@ -190,7 +127,7 @@ void PicoVideoFIFOSync(int cycles)
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int slots, done;
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// calculate #slots since last executed slot
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slots = GetFIFOSlot(pv, cycles) - fifo_slot;
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slots = fifo_cyc2sl[cycles>>1] - fifo_slot;
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// advance FIFO queue by #done slots
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done = slots;
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@ -208,31 +145,28 @@ void PicoVideoFIFOSync(int cycles)
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int PicoVideoFIFODrain(int level, int cycles, int bgdma)
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{
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struct PicoVideo *pv = &Pico.video;
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int maxsl = GetMaxFIFOSlot(pv); // max xfer slots in this scanline
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unsigned ocyc = cycles;
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int burn = 0;
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// process FIFO entries until low level is reached
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while (fifo_total > level && fifo_slot < maxsl &&
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while (fifo_total > level && fifo_slot < fifo_maxslot &&
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(!(fifo_queue[fifo_qx] & FQ_BGDMA) || bgdma)) {
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int b = fifo_queue[fifo_qx] & FQ_BYTE;
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int cnt = ((fifo_total-level) << b) - (pv->fifo_cnt & b);
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int last = fifo_slot;
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int slot = (pv->fifo_cnt < cnt ? pv->fifo_cnt : cnt) + last; // target slot
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unsigned ocyc = cycles;
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int slot = (pv->fifo_cnt<cnt ? pv->fifo_cnt:cnt) + fifo_slot; // target slot
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if (slot > maxsl) {
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if (slot > fifo_maxslot) {
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// target in later scanline, advance to eol
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slot = maxsl;
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slot = fifo_maxslot;
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cycles = 488;
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} else {
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// advance FIFO to target slot and CPU to cycles at that slot
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cycles = GetFIFOCycles(pv, slot);
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cycles = fifo_sl2cyc[slot]<<1;
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}
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AdvanceFIFOEntry(pv, slot - fifo_slot);
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fifo_slot = slot;
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burn += cycles - ocyc;
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AdvanceFIFOEntry(pv, slot - last);
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}
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burn = cycles - ocyc;
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SetFIFOState(pv);
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@ -246,17 +180,19 @@ int PicoVideoFIFORead(void)
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int lc = SekCyclesDone()-Pico.t.m68c_line_start;
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int burn = 0;
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PicoVideoFIFOSync(lc);
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if (pv->fifo_cnt) {
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PicoVideoFIFOSync(lc);
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// advance FIFO and CPU until FIFO is empty
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burn = PicoVideoFIFODrain(0, lc, 1);
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lc += burn;
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}
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// advance FIFO and CPU until FIFO is empty
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burn = PicoVideoFIFODrain(0, lc, 1);
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lc += burn;
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if (fifo_total > 0)
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pv->status |= PVS_CPURD; // target slot is in later scanline
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else {
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// use next VDP access slot for reading, block 68k until then
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fifo_slot = GetFIFOSlot(pv, lc) + 1;
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burn += GetFIFOCycles(pv, fifo_slot) - lc;
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fifo_slot = fifo_cyc2sl[lc>>1] + 1;
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burn += (fifo_sl2cyc[fifo_slot]<<1) - lc;
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}
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return burn;
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@ -267,35 +203,41 @@ int PicoVideoFIFOWrite(int count, int flags, unsigned sr_mask,unsigned sr_flags)
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{
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struct PicoVideo *pv = &Pico.video;
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int lc = SekCyclesDone()-Pico.t.m68c_line_start;
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int burn = 0, x;
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int burn = 0, x, head = 0;
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PicoVideoFIFOSync(lc);
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if (pv->fifo_cnt)
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PicoVideoFIFOSync(lc);
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pv->status = (pv->status & ~sr_mask) | sr_flags;
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if (count && fifo_ql < 8) {
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// update FIFO state if it was empty
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if (fifo_ql == 0) {
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fifo_slot = GetFIFOSlot(pv, lc+9); // FIFO latency ~3 vdp slots
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fifo_slot = fifo_cyc2sl[(lc+8)>>1]; // FIFO latency ~3 vdp slots
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pv->fifo_cnt = count << (flags & FQ_BYTE);
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pv->status |= PVS_FIFORUN;
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}
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// create xfer queue entry
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// determine queue position for entry
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x = (fifo_qx + fifo_ql - 1) & 7;
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if (fifo_ql && (fifo_queue[x] & FQ_BGDMA)) {
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// CPU FIFO writes have priority over a background DMA Fill/Copy
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fifo_queue[(x+1) & 7] = fifo_queue[x];
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if (fifo_ql == 1) {
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if (x == fifo_qx) { // overtaking to queue head?
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// XXX if interrupting a DMA fill, fill data changes
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int f = fifo_queue[x] & 7;
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fifo_queue[(x+1) & 7] = (pv->fifo_cnt >> (f & FQ_BYTE) << 3) | f;
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pv->fifo_cnt = count << (flags & FQ_BYTE);
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head = 1;
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}
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x = (x-1) & 7;
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}
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if (fifo_ql && (fifo_queue[x] & 7) == flags) {
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// create xfer queue entry
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if (fifo_ql && !head && (fifo_queue[x] & 7) == flags) {
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// amalgamate entries if of same type
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fifo_queue[x] += (count << 3);
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if (fifo_ql == 1) pv->fifo_cnt += count << (flags & FQ_BYTE);
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if (x == fifo_qx) // modifiying fifo head, adjust count
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pv->fifo_cnt += count << (flags & FQ_BYTE);
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} else {
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fifo_ql ++;
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x = (x+1) & 7;
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@ -331,20 +273,25 @@ int PicoVideoFIFOHint(void)
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}
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// switch FIFO mode between active/inactive display
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static void PicoVideoFIFOMode(int active)
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void PicoVideoFIFOMode(int active, int h40)
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{
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static const unsigned char *vdpcyc2sl[2][2] =
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{ {vdpcyc2sl_32_bl, vdpcyc2sl_40_bl} , {vdpcyc2sl_32, vdpcyc2sl_40} };
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static const unsigned short *vdpsl2cyc[2][2] =
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{ {vdpsl2cyc_32_bl, vdpsl2cyc_40_bl} , {vdpsl2cyc_32, vdpsl2cyc_40} };
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struct PicoVideo *pv = &Pico.video;
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int h40 = pv->reg[12] & 1;
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int lc = SekCyclesDone() - Pico.t.m68c_line_start;
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active = active && !(pv->status & PVS_VB2);
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PicoVideoFIFOSync(lc);
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if (fifo_maxslot)
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PicoVideoFIFOSync(lc);
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if (fifo_ql) {
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// recalculate FIFO slot for new mode
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if (!(pv->status & SR_VB) && active)
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fifo_slot = (pv->reg[12]&1 ? vdpcyc2sl_40 : vdpcyc2sl_32)[lc/4];
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else fifo_slot = ((lc * vdpcyc2sl_bl[h40] + lc) >> 16);
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}
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fifo_cyc2sl = vdpcyc2sl[active][h40];
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fifo_sl2cyc = vdpsl2cyc[active][h40];
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// recalculate FIFO slot for new mode
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fifo_slot = fifo_cyc2sl[lc>>1]-1;
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fifo_maxslot = fifo_cyc2sl[488>>1];
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}
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@ -459,7 +406,7 @@ static void DmaSlow(int len, unsigned int source)
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SekCyclesDone(), SekPc);
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SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_FGDMA | (Pico.video.type == 1),
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0, SR_DMA| PVS_CPUWR));
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PVS_DMABG, SR_DMA | PVS_CPUWR));
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if ((source & 0xe00000) == 0xe00000) { // Ram
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base = (u16 *)PicoMem.ram;
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@ -583,13 +530,13 @@ static void DmaCopy(int len)
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int source;
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elprintf(EL_VDPDMA, "DmaCopy len %i [%u]", len, SekCyclesDone());
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// XXX implement VRAM 128k? Is this even working? xfer/count still FQ_BYTE?
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SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA | FQ_BYTE,
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PVS_CPUWR, SR_DMA));
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PVS_CPUWR, SR_DMA | PVS_DMABG));
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source =Pico.video.reg[0x15];
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source|=Pico.video.reg[0x16]<<8;
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// XXX implement VRAM 128k? Is this even working? count still in bytes?
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for (; len; len--)
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{
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vr[(u16)a] = vr[(u16)(source++)];
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@ -616,7 +563,7 @@ static NOINLINE void DmaFill(int data)
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elprintf(EL_VDPDMA, "DmaFill len %i inc %i [%u]", len, inc, SekCyclesDone());
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SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA | (Pico.video.type == 1),
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PVS_CPUWR | PVS_DMAFILL, SR_DMA));
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PVS_CPUWR | PVS_DMAFILL, SR_DMA | PVS_DMABG));
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switch (Pico.video.type)
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{
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@ -823,11 +770,13 @@ PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d)
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if (num == 0 && !(pvid->reg[0]&2) && (d&2))
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pvid->hv_latch = PicoVideoRead(0x08);
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if (num == 1 && ((pvid->reg[1]^d)&0x40)) {
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PicoVideoFIFOMode(d & 0x40);
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PicoVideoFIFOMode(d & 0x40, pvid->reg[12]&1);
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// handle line blanking before line rendering
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if (SekCyclesDone() - Pico.t.m68c_line_start <= 488-390)
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blankline = d&0x40 ? -1 : Pico.m.scanline;
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}
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if (num == 12 && ((pvid->reg[12]^d)&0x01))
|
||||
PicoVideoFIFOMode(pvid->reg[1]&0x40, d & 1);
|
||||
DrawSync(SekCyclesDone() - Pico.t.m68c_line_start <= 488-390);
|
||||
pvid->reg[num]=(unsigned char)d;
|
||||
switch (num)
|
||||
|
|
@ -1058,6 +1007,7 @@ void PicoVideoLoad(void)
|
|||
|
||||
// convert former dma_xfers (why was this in PicoMisc anyway?)
|
||||
if (Pico.m.dma_xfers) {
|
||||
pv->status = SR_DMA|PVS_FIFORUN;
|
||||
pv->fifo_cnt = Pico.m.dma_xfers * (pv->type == 1 ? 2 : 1);
|
||||
fifo_total = Pico.m.dma_xfers;
|
||||
Pico.m.dma_xfers = 0;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue