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ym2612 ARM optimisations
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kub
parent
b061bc166c
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c918379137
1 changed files with 83 additions and 117 deletions
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@ -15,8 +15,8 @@
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#include "../arm_features.h"
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@ very simple adaption YM2612 output rate to sample rate (~1M cycles @44100)
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//#define INTERPOL
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@ very simple YM2612 output rate to sample rate adaption (~500k cycles @44100)
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#define INTERPOL
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.equiv SLOT1, 0
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.equiv SLOT2, 2
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@ -44,7 +44,7 @@
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@ r5=slot, r1=eg_cnt, trashes: r0,r2,r3
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@ writes output to routp, but only if vol_out changes
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.macro update_eg_phase_slot slot
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.macro update_eg_phase_slot
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#if defined(INTERPOL)
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ldrh r0, [r5,#0x34] @ vol_out
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#endif
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@ -190,21 +190,6 @@
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ldrh r3, [r5,#0x18] @ tl
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add r0, r0, r3 @ volume += tl
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strh r0, [r5,#0x34] @ vol_out
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.if \slot == SLOT1
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mov r6, r6, lsr #16
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orr r6, r0, r6, lsl #16
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.elseif \slot == SLOT2
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mov r6, r6, lsl #16
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mov r0, r0, lsl #16
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orr r6, r0, r6, lsr #16
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.elseif \slot == SLOT3
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mov r7, r7, lsr #16
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orr r7, r0, r7, lsl #16
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.elseif \slot == SLOT4
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mov r7, r7, lsl #16
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mov r0, r0, lsl #16
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orr r7, r0, r7, lsr #16
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.endif
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0: @ EG_OFF
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.endm
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@ -672,24 +657,16 @@ chan_render_loop:
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mov r11, r1
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and r0, r0, #7
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orr r4, r4, r0 @ (length<<8)|algo
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add r0, lr, #0x44
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ldmia r0, {r8,r9} @ eg_timer, eg_timer_add
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ldr r8, [lr, #0x44] @ eg_timer
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ldr r9, [lr, #0x48] @ eg_timer_add
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ldr r10, [lr, #0x54] @ op1_out
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@ ldmia lr, {r6,r7} @ load volumes
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ldr r5, [lr, #0x40] @ CH
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ldrh r6, [r5, #0x34] @ vol_out values for all slots
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ldrh r2, [r5, #0x34+SLOT_STRUCT_SIZE*2]
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ldrh r7, [r5, #0x34+SLOT_STRUCT_SIZE]
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ldrh r3, [r5, #0x34+SLOT_STRUCT_SIZE*3]
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orr r6, r6, r2, lsl #16
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orr r7, r7, r3, lsl #16
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tst r12, #8 @ lfo?
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beq crl_loop
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crl_loop_lfo:
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add r0, lr, #0x30
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ldmia r0, {r1,r2} @ lfo_cnt, lfo_inc
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ldr r1, [lr, #0x30] @ lfo_cnt
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ldr r2, [lr, #0x34] @ lfo_inc
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subs r4, r4, #0x100
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bmi crl_loop_end
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@ -707,37 +684,48 @@ crl_loop:
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bmi crl_loop_end
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@ -- SSG --
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add r0, lr, #0x3c
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ldmia r0, {r1,r5} @ eg_cnt, CH
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ldr r5, [lr, #0x40] @ CH
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@ r5=slot, trashes: r0,r2,r3
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mov r6, #4
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ssg_upd_loop:
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update_ssg_eg
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add r5, r5, #SLOT_STRUCT_SIZE*2 @ SLOT2 (2)
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update_ssg_eg
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sub r5, r5, #SLOT_STRUCT_SIZE @ SLOT3 (1)
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update_ssg_eg
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add r5, r5, #SLOT_STRUCT_SIZE*2 @ SLOT4 (3)
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#if 0
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subs r6, r6, #1
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addne r5, r5, #SLOT_STRUCT_SIZE
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#else
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add r5, r5, #SLOT_STRUCT_SIZE*2
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update_ssg_eg
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subs r6, r6, #2
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subne r5, r5, #SLOT_STRUCT_SIZE
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#endif
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bne ssg_upd_loop
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sub r5, r5, #SLOT_STRUCT_SIZE*3
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@ -- EG --
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add r8, r8, r9
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cmp r8, #EG_TIMER_OVERFLOW
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bcc eg_done
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ldr r1, [lr, #0x3c] @ eg_cnt
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eg_loop:
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sub r8, r8, #EG_TIMER_OVERFLOW
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add r1, r1, #1
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cmp r1, #4096
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movge r1, #1
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@ SLOT1 (0)
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@ r5=slot, r1=eg_cnt, trashes: r0,r2,r3
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update_eg_phase_slot SLOT1
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add r5, r5, #SLOT_STRUCT_SIZE*2 @ SLOT2 (2)
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update_eg_phase_slot SLOT2
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sub r5, r5, #SLOT_STRUCT_SIZE @ SLOT3 (1)
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update_eg_phase_slot SLOT3
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add r5, r5, #SLOT_STRUCT_SIZE*2 @ SLOT4 (3)
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update_eg_phase_slot SLOT4
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mov r6, #4
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eg_upd_loop:
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update_eg_phase_slot
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#if 1
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subs r6, r6, #1
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addne r5, r5, #SLOT_STRUCT_SIZE
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#else
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add r5, r5, #SLOT_STRUCT_SIZE*2
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update_eg_phase_slot
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subs r6, r6, #2
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subne r5, r5, #SLOT_STRUCT_SIZE
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#endif
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bne eg_upd_loop
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cmp r8, #EG_TIMER_OVERFLOW
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sub r5, r5, #SLOT_STRUCT_SIZE*3
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@ -754,64 +742,49 @@ eg_done:
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beq crl_loop
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@ output interpolation
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#if 0 // too expensive on slow platforms
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#if defined(INTERPOL)
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#if 1 // possibly too expensive for slow platforms?
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@ basic interpolator, interpolate in middle region, else use closer value
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mov r3, r8, lsr #EG_SH @ eg_timer, [0..3<<EG_SH) after loop
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cmp r3, #(EG_TIMER_OVERFLOW>>EG_SH)/2
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bgt 0f @ mix is vol_out
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bne 0f @ mix is vol_out
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ldrh r0, [r5,#0x36] @ SLOT1 vol_ipol
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lsleq r2, r6, #16
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addeq r0, r0, r2, lsr #16
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lsreq r0, r0, #1
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mov r6, r6, lsr #16
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orr r6, r0, r6, lsl #16
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ldrh r0, [r5,#0x36+SLOT_STRUCT_SIZE*2] @ SLOT2 vol_ipol
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addeq r0, r0, r6, lsr #16
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lsreq r0, r0, #1
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mov r6, r6, lsl #16
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orr r6, r6, r0
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ror r6, r6, #16
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ldrh r0, [r5,#0x36+SLOT_STRUCT_SIZE] @ SLOT3 vol_ipol
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lsleq r2, r7, #16
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addeq r0, r0, r2, lsr #16
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lsreq r0, r0, #1
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mov r7, r7, lsr #16
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orr r7, r0, r7, lsl #16
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ldrh r0, [r5,#0x36+SLOT_STRUCT_SIZE*3] @ SLOT4 vol_ipol
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addeq r0, r0, r7, lsr #16
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lsreq r0, r0, #1
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mov r7, r7, lsl #16
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orr r7, r7, r0
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ror r7, r7, #16
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#elif defined(INTERPOL)
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ldr r6, [r5, #0x34] @ vol_out, vol_ipol for all slots
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ldr r2, [r5, #0x34+SLOT_STRUCT_SIZE*2]
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ldr r7, [r5, #0x34+SLOT_STRUCT_SIZE]
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ldr r3, [r5, #0x34+SLOT_STRUCT_SIZE*3]
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add r6, r6, r6, lsl #16
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lsr r6, r6, #17
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add r2, r2, r2, lsl #16
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lsr r2, r2, #17
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add r7, r7, r7, lsl #16
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lsr r7, r7, #17
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add r3, r3, r3, lsl #16
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lsr r3, r3, #17
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b 1f
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#else
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@ super-basic... just take value closest to sample point
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mov r3, r8, lsr #EG_SH-1 @ eg_timer, [0..3<<EG_SH) after loop
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cmp r3, #(EG_TIMER_OVERFLOW>>EG_SH)
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bge 0f @ mix is vol_out
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ldrh r0, [r5,#0x36] @ SLOT1 vol_ipol
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mov r6, r6, lsr #16
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orr r6, r0, r6, lsl #16
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ldrh r0, [r5,#0x36+SLOT_STRUCT_SIZE*2] @ SLOT2 vol_ipol
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mov r6, r6, lsl #16
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orr r6, r6, r0
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ror r6, r6, #16
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ldrh r0, [r5,#0x36+SLOT_STRUCT_SIZE] @ SLOT3 vol_ipol
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mov r7, r7, lsr #16
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orr r7, r0, r7, lsl #16
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ldrh r0, [r5,#0x36+SLOT_STRUCT_SIZE*3] @ SLOT4 vol_ipol
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mov r7, r7, lsl #16
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orr r7, r7, r0
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ror r7, r7, #16
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#endif
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0:
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0: ldrgeh r6, [r5, #0x34] @ vol_out values for all slots
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ldrlth r6, [r5, #0x36] @ vol_ipol values for all slots
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ldrgeh r2, [r5, #0x34+SLOT_STRUCT_SIZE*2]
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ldrlth r2, [r5, #0x36+SLOT_STRUCT_SIZE*2]
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ldrgeh r7, [r5, #0x34+SLOT_STRUCT_SIZE]
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ldrlth r7, [r5, #0x36+SLOT_STRUCT_SIZE]
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ldrgeh r3, [r5, #0x34+SLOT_STRUCT_SIZE*3]
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ldrlth r3, [r5, #0x36+SLOT_STRUCT_SIZE*3]
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#else
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ldrh r6, [r5, #0x34] @ vol_out values for all slots
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ldrh r2, [r5, #0x34+SLOT_STRUCT_SIZE*2]
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ldrh r7, [r5, #0x34+SLOT_STRUCT_SIZE]
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ldrh r3, [r5, #0x34+SLOT_STRUCT_SIZE*3]
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#endif
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1: orr r6, r6, r2, lsl #16
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orr r7, r7, r3, lsl #16
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@ -- SLOT1 --
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PIC_LDR(r3, r2, ym_tl_tab)
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@ -893,34 +866,28 @@ crl_algo_done:
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strne r1, [r11], #4
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b crl_do_phase
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ctl_sample_skip:
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and r1, r12, #1
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add r1, r1, #1
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add r11,r11, r1, lsl #2
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b crl_do_phase
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ctl_sample_mono:
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ldr r1, [r11]
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add r1, r0, r1
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str r1, [r11], #4
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b crl_do_phase
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ctl_sample_skip:
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and r1, r12, #1
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add r1, r1, #1
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add r11,r11, r1, lsl #2
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crl_do_phase:
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@ -- PHASE UPDATE --
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add r5, lr, #0x10
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ldmia r5, {r0-r1}
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add r5, lr, #0x20
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ldmia r5, {r2-r3}
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add r5, lr, #0x10
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add r0, r0, r2
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add r1, r1, r3
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stmia r5!,{r0-r1}
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ldmia r5, {r0-r1}
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add r5, lr, #0x28
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ldmia r5, {r2-r3}
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add r5, lr, #0x18
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add r0, r0, r2
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add r1, r1, r3
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stmia r5, {r0-r1}
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ldmia r5, {r0-r3,r6-r7}
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add r0, r0, r6
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add r1, r1, r7
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ldr r6, [r5, #0x18]
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ldr r7, [r5, #0x1c]
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add r2, r2, r6
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add r3, r3, r7
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stmia r5, {r0-r3}
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tst r12, #8
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bne crl_loop_lfo
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@ -928,7 +895,6 @@ crl_do_phase:
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crl_loop_end:
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@ stmia lr, {r6,r7} @ save volumes (for debug)
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str r8, [lr, #0x44] @ eg_timer
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str r12, [lr, #0x4c] @ pack (for lfo_ampm)
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str r4, [lr, #0x50] @ was_update
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