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https://github.com/RaySollium99/picodrive.git
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drc: rm write irq check
does more bad than good
This commit is contained in:
notaz
parent
00a725a87c
commit
d056bef851
1 changed files with 19 additions and 76 deletions
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@ -283,9 +283,7 @@ static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2);
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static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
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static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
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static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
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static void REGPARM(2) (*sh2_drc_write8_slot)(u32 a, u32 d);
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static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
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static void REGPARM(2) (*sh2_drc_write16_slot)(u32 a, u32 d);
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static int REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
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// address space stuff
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@ -1149,7 +1147,7 @@ static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int siz
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return hr2;
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}
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static void emit_memhandler_write(int size, u32 pc, int delay)
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static void emit_memhandler_write(int size, u32 pc)
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{
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int ctxr;
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host_arg2reg(ctxr, 2);
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@ -1159,22 +1157,12 @@ static void emit_memhandler_write(int size, u32 pc, int delay)
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switch (size) {
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case 0: // 8
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// XXX: consider inlining sh2_drc_write8
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if (delay) {
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emith_call(sh2_drc_write8_slot);
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} else {
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emit_move_r_imm32(SHR_PC, pc);
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rcache_clean();
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emith_call(sh2_drc_write8);
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}
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rcache_clean();
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emith_call(sh2_drc_write8);
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break;
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case 1: // 16
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if (delay) {
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emith_call(sh2_drc_write16_slot);
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} else {
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emit_move_r_imm32(SHR_PC, pc);
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rcache_clean();
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emith_call(sh2_drc_write16);
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}
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rcache_clean();
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emith_call(sh2_drc_write16);
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break;
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case 2: // 32
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emith_move_r_r(ctxr, CONTEXT_REG);
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@ -1182,9 +1170,9 @@ static void emit_memhandler_write(int size, u32 pc, int delay)
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break;
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}
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rcache_invalidate();
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if (reg_map_g2h[SHR_SR] != -1)
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emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
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rcache_invalidate();
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}
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// @(Rx,Ry)
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@ -1541,7 +1529,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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tmp2 = rcache_get_reg_arg(0, SHR_R0);
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tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
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emith_add_r_r(tmp2, tmp3);
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emit_memhandler_write(op & 3, pc, drcf.delayed_op);
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emit_memhandler_write(op & 3, pc);
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goto end_op;
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case 0x07:
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// MUL.L Rm,Rn 0000nnnnmmmm0111
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@ -1708,7 +1696,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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tmp2 = rcache_get_reg_arg(1, GET_Rm());
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if (op & 0x0f)
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emith_add_r_imm(tmp, (op & 0x0f) * 4);
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emit_memhandler_write(2, pc, drcf.delayed_op);
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emit_memhandler_write(2, pc);
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goto end_op;
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case 0x02:
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@ -1720,7 +1708,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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rcache_clean();
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rcache_get_reg_arg(0, GET_Rn());
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rcache_get_reg_arg(1, GET_Rm());
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emit_memhandler_write(op & 3, pc, drcf.delayed_op);
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emit_memhandler_write(op & 3, pc);
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goto end_op;
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case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100
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case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101
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@ -1730,7 +1718,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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rcache_clean();
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rcache_get_reg_arg(0, GET_Rn());
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rcache_get_reg_arg(1, GET_Rm());
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emit_memhandler_write(op & 3, pc, drcf.delayed_op);
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emit_memhandler_write(op & 3, pc);
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goto end_op;
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case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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@ -2066,7 +2054,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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tmp3 = rcache_get_reg_arg(1, tmp);
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if (tmp == SHR_SR)
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emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
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emit_memhandler_write(2, pc, drcf.delayed_op);
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emit_memhandler_write(2, pc);
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goto end_op;
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case 0x04:
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case 0x05:
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@ -2228,8 +2216,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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emith_move_r_r(tmp2, tmp);
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rcache_free_tmp(tmp);
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rcache_get_reg_arg(0, GET_Rn());
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emit_memhandler_write(0, pc, drcf.delayed_op);
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cycles += 3;
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emit_memhandler_write(0, pc);
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break;
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default:
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goto default_;
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@ -2394,7 +2381,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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tmp3 = (op & 0x100) >> 8;
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if (op & 0x0f)
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emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
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emit_memhandler_write(tmp3, pc, drcf.delayed_op);
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emit_memhandler_write(tmp3, pc);
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goto end_op;
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case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
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case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
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@ -2483,7 +2470,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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tmp2 = rcache_get_reg_arg(1, SHR_R0);
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tmp3 = (op & 0x300) >> 8;
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emith_add_r_imm(tmp, (op & 0xff) << tmp3);
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emit_memhandler_write(tmp3, pc, drcf.delayed_op);
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emit_memhandler_write(tmp3, pc);
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goto end_op;
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case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
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case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
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@ -2499,12 +2486,12 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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emith_add_r_imm(tmp, 4);
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tmp = rcache_get_reg_arg(1, SHR_SR);
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emith_clear_msb(tmp, tmp, 22);
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emit_memhandler_write(2, pc, drcf.delayed_op);
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emit_memhandler_write(2, pc);
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// push PC
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rcache_get_reg_arg(0, SHR_SP);
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tmp = rcache_get_tmp_arg(1);
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emith_move_r_imm(tmp, pc);
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emit_memhandler_write(2, pc, drcf.delayed_op);
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emit_memhandler_write(2, pc);
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// obtain new PC
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emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2);
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out_pc = (u32)-1;
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@ -2563,8 +2550,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
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tmp3 = rcache_get_reg_arg(0, SHR_GBR);
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tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
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emith_add_r_r(tmp3, tmp4);
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emit_memhandler_write(0, pc, drcf.delayed_op);
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cycles += 2;
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emit_memhandler_write(0, pc);
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goto end_op;
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}
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goto default_;
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@ -2779,7 +2765,6 @@ end_op:
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static void sh2_generate_utils(void)
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{
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int arg0, arg1, arg2, sr, tmp;
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void *sh2_drc_write_end, *sh2_drc_write_slot_end;
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sh2_drc_write32 = p32x_sh2_write32;
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sh2_drc_read8 = p32x_sh2_read8;
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@ -2880,51 +2865,15 @@ static void sh2_generate_utils(void)
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emith_call(sh2_drc_test_irq);
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emith_jump(sh2_drc_dispatcher);
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// write-caused irq detection
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sh2_drc_write_end = tcache_ptr;
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emith_tst_r_r(arg0, arg0);
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EMITH_SJMP_START(DCOND_NE);
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emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp)); // return
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EMITH_SJMP_END(DCOND_NE);
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emith_call(sh2_drc_test_irq);
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emith_jump_ctx(offsetof(SH2, drc_tmp));
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// write-caused irq detection for writes in delay slot
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sh2_drc_write_slot_end = tcache_ptr;
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emith_tst_r_r(arg0, arg0);
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EMITH_SJMP_START(DCOND_NE);
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emith_jump_ctx_c(DCOND_EQ, offsetof(SH2, drc_tmp));
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EMITH_SJMP_END(DCOND_NE);
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// just burn cycles to get back to dispatcher after branch is handled
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sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
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emith_ctx_write(sr, offsetof(SH2, irq_cycles));
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emith_clear_msb(sr, sr, 20); // clear cycles
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rcache_flush();
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emith_jump_ctx(offsetof(SH2, drc_tmp));
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// sh2_drc_write8(u32 a, u32 d)
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sh2_drc_write8 = (void *)tcache_ptr;
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emith_ret_to_ctx(offsetof(SH2, drc_tmp));
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emith_ctx_read(arg2, offsetof(SH2, write8_tab));
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emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
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emith_sh2_wcall(arg0, arg2);
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// sh2_drc_write16(u32 a, u32 d)
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sh2_drc_write16 = (void *)tcache_ptr;
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emith_ret_to_ctx(offsetof(SH2, drc_tmp));
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emith_ctx_read(arg2, offsetof(SH2, write16_tab));
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emith_sh2_wcall(arg0, arg2, sh2_drc_write_end);
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// sh2_drc_write8_slot(u32 a, u32 d)
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sh2_drc_write8_slot = (void *)tcache_ptr;
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emith_ret_to_ctx(offsetof(SH2, drc_tmp));
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emith_ctx_read(arg2, offsetof(SH2, write8_tab));
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emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
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// sh2_drc_write16_slot(u32 a, u32 d)
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sh2_drc_write16_slot = (void *)tcache_ptr;
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emith_ret_to_ctx(offsetof(SH2, drc_tmp));
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emith_ctx_read(arg2, offsetof(SH2, write16_tab));
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emith_sh2_wcall(arg0, arg2, sh2_drc_write_slot_end);
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emith_sh2_wcall(arg0, arg2);
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#ifdef PDB_NET
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// debug
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@ -2958,9 +2907,7 @@ static void sh2_generate_utils(void)
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MAKE_READ_WRAPPER(sh2_drc_read16);
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MAKE_READ_WRAPPER(sh2_drc_read32);
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MAKE_WRITE_WRAPPER(sh2_drc_write8);
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MAKE_WRITE_WRAPPER(sh2_drc_write8_slot);
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MAKE_WRITE_WRAPPER(sh2_drc_write16);
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MAKE_WRITE_WRAPPER(sh2_drc_write16_slot);
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MAKE_WRITE_WRAPPER(sh2_drc_write32);
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#if (DRC_DEBUG & 4)
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host_dasm_new_symbol(sh2_drc_read8);
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@ -2976,12 +2923,8 @@ static void sh2_generate_utils(void)
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host_dasm_new_symbol(sh2_drc_dispatcher);
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host_dasm_new_symbol(sh2_drc_exit);
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host_dasm_new_symbol(sh2_drc_test_irq);
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host_dasm_new_symbol(sh2_drc_write_end);
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host_dasm_new_symbol(sh2_drc_write_slot_end);
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host_dasm_new_symbol(sh2_drc_write8);
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host_dasm_new_symbol(sh2_drc_write8_slot);
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host_dasm_new_symbol(sh2_drc_write16);
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host_dasm_new_symbol(sh2_drc_write16_slot);
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#endif
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}
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