mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
sound, improve ym2612 accuracy (NB noticeably slower for low bitrates)
This commit is contained in:
kub
parent
c3fcdf3f8d
commit
d127b3f3d5
3 changed files with 361 additions and 438 deletions
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@ -16,7 +16,6 @@
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#include <pico/arm_features.h>
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@ very simple YM2612 output rate to sample rate adaption (~500k cycles @44100)
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#define INTERPOL
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#define SSG_EG
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.equiv SLOT1, 0
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@ -34,7 +33,6 @@
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.equiv EG_OFF, 0
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.equiv EG_SH, 16 @ 16.16 fixed point (envelope generator timing)
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.equiv EG_TIMER_OVERFLOW, (3*(1<<EG_SH)) @ envelope generator timer overflows every 3 samples (on real chip)
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.equiv LFO_SH, 24 /* 8.24 fixed point (LFO calculations) */
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.equiv ENV_QUIET, (2*13*256/8)
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@ -46,14 +44,8 @@
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@ r5=slot, r1=eg_cnt, trashes: r0,r2,r3
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@ writes output to routp, but only if vol_out changes
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.macro update_eg_phase_slot
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#if defined(INTERPOL)
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ldrh r0, [r5,#0x34] @ vol_out
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#endif
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ldrb r2, [r5,#0x17] @ state
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add r3, r5, #0x1c
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#if defined(INTERPOL)
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strh r0, [r5,#0x36] @ vol_ipol
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#endif
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tst r2, r2
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beq 0f @ EG_OFF
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@ -211,7 +203,6 @@
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cmp r2, #EG_REL+1 @ state > EG_REL &&
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cmpge r3, #0x200 @ volume >= 0x200?
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blt 9f
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orr r4, r4, #0x10 @ ssg_update
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tst r0, #0x01
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beq 1f
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@ -259,14 +250,8 @@
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@ r5=slot, trashes: r0,r2,r3
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.macro recalc_volout
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#if defined(INTERPOL)
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ldrh r0, [r5,#0x34] @ vol_out
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#endif
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ldrb r2, [r5,#0x30] @ ssg
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ldrb r3, [r5,#0x17] @ state
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#if defined(INTERPOL)
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strh r0, [r5,#0x36] @ vol_ipol
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#endif
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ldrh r0, [r5,#0x1a] @ volume
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@ and r2, r2, #0x0c
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@ -342,6 +327,9 @@
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@ r0-r2=scratch, r3=sin_tab, r5=scratch, r6-r7=vol_out[4], r10=op1_out
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.macro upd_algo0_m
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cmp r8, #(1<<EG_SH)
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bge 1f
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@ SLOT3
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make_eg_out SLOT3
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cmp r1, #ENV_QUIET
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@ -383,6 +371,9 @@
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.macro upd_algo1_m
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cmp r8, #(1<<EG_SH)
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bge 1f
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@ SLOT3
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make_eg_out SLOT3
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cmp r1, #ENV_QUIET
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@ -423,6 +414,9 @@
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.macro upd_algo2_m
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cmp r8, #(1<<EG_SH)
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bge 1f
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@ SLOT3
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make_eg_out SLOT3
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cmp r1, #ENV_QUIET
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@ -464,6 +458,9 @@
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.macro upd_algo3_m
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cmp r8, #(1<<EG_SH)
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bge 1f
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@ SLOT3
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make_eg_out SLOT3
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cmp r1, #ENV_QUIET
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@ -505,6 +502,9 @@
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.macro upd_algo4_m
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cmp r8, #(1<<EG_SH)
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bge 2f
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@ SLOT3
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make_eg_out SLOT3
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cmp r1, #ENV_QUIET
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@ -542,6 +542,9 @@
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.macro upd_algo5_m
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cmp r8, #(1<<EG_SH)
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bge 2f
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@ SLOT3
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make_eg_out SLOT3
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cmp r1, #ENV_QUIET
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@ -582,6 +585,9 @@
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.macro upd_algo6_m
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cmp r8, #(1<<EG_SH)
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bge 2f
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@ SLOT3
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make_eg_out SLOT3
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cmp r1, #ENV_QUIET
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@ -617,6 +623,9 @@
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.macro upd_algo7_m
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cmp r8, #(1<<EG_SH)
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bge 2f
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@ SLOT3
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make_eg_out SLOT3
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cmp r1, #ENV_QUIET
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@ -677,7 +686,7 @@
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@ lr=context, r12=pack (stereo, ssg_enabled, disabled, lfo_enabled | pan_r, pan_l, ams[2] | AMmasks[4] | FB[4] | lfo_ampm[16])
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@ r0-r2=scratch, r3=sin_tab/scratch, r4=(length<<8)|dac,unused[2],ssg_update,was_update,algo[3], r5=tl_tab/slot,
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@ r0-r2=scratch, r3=sin_tab/scratch, r4=(length<<8)|dac,upd_cnt[3],was_update,algo[3], r5=tl_tab/slot,
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@ r6-r7=vol_out[4], r8=eg_timer, r9=eg_timer_add[31:16], r10=op1_out, r11=buffer
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.global chan_render_loop @ chan_rend_context *ct, int *buffer, int length
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@ -688,47 +697,48 @@ chan_render_loop:
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ldr r12, [lr, #0x4c]
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ldr r0, [lr, #0x50]
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mov r11, r1
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and r0, r0, #0x87
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orr r4, r4, r0 @ (length<<8)|dac,unused[4],algo[3]
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and r0, r0, #0xf7
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orr r4, r4, r0 @ (length<<8)|dac,upd_cnt[2],unused,algo[3]
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ldr r8, [lr, #0x44] @ eg_timer
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ldr r9, [lr, #0x48] @ eg_timer_add
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ldr r10, [lr, #0x54] @ op1_out
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tst r12, #8 @ lfo?
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beq crl_loop
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crl_loop_lfo:
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ldr r1, [lr, #0x30] @ lfo_cnt
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ldr r2, [lr, #0x34] @ lfo_inc
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crl_loop:
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subs r4, r4, #0x100
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bmi crl_loop_end
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mov r0, #0
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add r8, r8, r9
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subs r8, r8, #(1<<EG_SH)
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blt crl_smp_loop_end
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@ r12=lfo_ampm[31:16], r1=lfo_cnt_old, r2=lfo_cnt
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advance_lfo_m
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crl_smp_loop:
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tst r12, #8 @ lfo?
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beq lfo_done
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ldr r2, [lr, #0x34] @ lfo_inc
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ldr r1, [lr, #0x30] @ lfo_cnt
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add r2, r2, r1
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str r2, [lr, #0x30]
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@ r12=lfo_ampm[31:16], r1=lfo_cnt_old, r2=lfo_cnt
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advance_lfo_m
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add r4, r4, #0x100
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crl_loop:
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subs r4, r4, #0x100
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bmi crl_loop_end
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lfo_done:
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ldr r5, [lr, #0x40] @ CH
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#if defined(SSG_EG)
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tst r12, #0x02 @ ssg_enabled?
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beq ssg_done
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@ -- SSG --
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lsl r7, r8, #EG_SH
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add r7, r9, r7, lsr #EG_SH
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subs r7, r7, #1<<EG_SH
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blt ssg_done
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@ -- SSG --
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ssg_loop:
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mov r6, #4
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bic r4, r4, #0x10 @ ssg_update
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ssg_upd_loop:
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@ use lr as a pointer to the slot phases stored in the context
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update_ssg_eg
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@ -748,26 +758,25 @@ ssg_upd_loop:
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sub lr, lr, #4*3
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sub r5, r5, #SLOT_STRUCT_SIZE*3
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subs r7, r7, #1<<EG_SH
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bge ssg_loop
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ssg_done:
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#endif
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@ -- EG --
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add r8, r8, r9
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cmp r8, #EG_TIMER_OVERFLOW
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blo volout_upd
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ldr r1, [lr, #0x3c] @ eg_cnt
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eg_loop:
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sub r8, r8, #EG_TIMER_OVERFLOW
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tst r4, #0x30
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subnes r4, r4, #0x10
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bne eg_done
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orr r4, r4, #0x30
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ldr r1, [lr, #0x3c] @ eg_cnt
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add r1, r1, #1
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cmp r1, #4096
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movge r1, #1
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str r1, [lr, #0x3c]
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mov r6, #4
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eg_upd_loop:
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update_eg_phase_slot
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#if 1
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#if 0
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subs r6, r6, #1
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addne r5, r5, #SLOT_STRUCT_SIZE
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#else
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@ -777,96 +786,38 @@ eg_upd_loop:
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subne r5, r5, #SLOT_STRUCT_SIZE
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#endif
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bne eg_upd_loop
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cmp r8, #EG_TIMER_OVERFLOW
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sub r5, r5, #SLOT_STRUCT_SIZE*3
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bhs eg_loop
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str r1, [lr, #0x3c]
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b eg_done
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volout_upd:
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#if defined(SSG_EG)
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tst r4, #0x10 @ ssg_update?
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beq eg_done
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@ recalc vol_out
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mov r6, #4
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volout_loop:
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recalc_volout
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#if 0
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subs r6, r6, #1
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addne r5, r5, #SLOT_STRUCT_SIZE
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#else
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add r5, r5, #SLOT_STRUCT_SIZE*2
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recalc_volout
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subs r6, r6, #2
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subne r5, r5, #SLOT_STRUCT_SIZE
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#endif
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bne volout_loop
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sub r5, r5, #SLOT_STRUCT_SIZE*3
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#endif
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eg_done:
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@ -- disabled? --
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and r0, r12, #0xC
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cmp r0, #0xC
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beq crl_loop_lfo
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cmp r0, #0x4
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beq crl_loop
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tst r12, #0x4
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mov r0, #0
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bne crl_algo_done
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@ output interpolation
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#if defined(INTERPOL)
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#if 1 // possibly too expensive for slow platforms?
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@ basic interpolator, interpolate in middle region, else use closer value
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mov r3, r8, lsr #EG_SH @ eg_timer, [0..3<<EG_SH) after loop
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cmp r3, #(EG_TIMER_OVERFLOW>>EG_SH)/2
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bne 0f @ mix is vol_out
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cmp r8, #(2<<EG_SH) @ calculate only for operator memory, sample,
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tstge r12, #0xf000 @ ...feedback
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beq crl_algo_done
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ldr r6, [r5, #0x34] @ vol_out, vol_ipol for all slots
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ldr r2, [r5, #0x34+SLOT_STRUCT_SIZE*2]
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ldr r7, [r5, #0x34+SLOT_STRUCT_SIZE]
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ldr r3, [r5, #0x34+SLOT_STRUCT_SIZE*3]
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add r6, r6, r6, lsl #16
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lsr r6, r6, #17
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add r2, r2, r2, lsl #16
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lsr r2, r2, #17
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add r7, r7, r7, lsl #16
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lsr r7, r7, #17
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add r3, r3, r3, lsl #16
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lsr r3, r3, #17
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b 1f
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#else
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@ super-basic... just take value closest to sample point
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mov r3, r8, lsr #EG_SH-1 @ eg_timer, [0..3<<EG_SH) after loop
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cmp r3, #(EG_TIMER_OVERFLOW>>EG_SH)
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#endif
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0: ldrgeh r6, [r5, #0x34] @ vol_out values for all slots
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ldrlth r6, [r5, #0x36] @ vol_ipol values for all slots
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ldrgeh r2, [r5, #0x34+SLOT_STRUCT_SIZE*2]
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ldrlth r2, [r5, #0x36+SLOT_STRUCT_SIZE*2]
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ldrgeh r7, [r5, #0x34+SLOT_STRUCT_SIZE]
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ldrlth r7, [r5, #0x36+SLOT_STRUCT_SIZE]
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ldrgeh r3, [r5, #0x34+SLOT_STRUCT_SIZE*3]
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ldrlth r3, [r5, #0x36+SLOT_STRUCT_SIZE*3]
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#else
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ldrh r6, [r5, #0x34] @ vol_out values for all slots
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ldrh r2, [r5, #0x34+SLOT_STRUCT_SIZE*2]
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ldrh r7, [r5, #0x34+SLOT_STRUCT_SIZE]
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ldrh r3, [r5, #0x34+SLOT_STRUCT_SIZE*3]
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#endif
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1: orr r6, r6, r2, lsl #16
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orr r6, r6, r2, lsl #16
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orr r7, r7, r3, lsl #16
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@ -- SLOT1 --
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PIC_LDR(r3, r2, ym_tl_tab)
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@ lr=context, r12=pack (stereo, ssg_enabled, disabled, lfo_enabled | pan_r, pan_l, ams[2] | AMmasks[4] | FB[4] | lfo_ampm[16])
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@ r0-r2=scratch, r3=tl_tab, r5=scratch, r6-r7=vol_out[4], r10=op1_out
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@ -- SLOT1 --
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upd_slot1_m
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@ -- SLOT2+ --
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cmp r8, #(2<<EG_SH) @ op mem or sample?
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bge crl_algo_done
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and r0, r4, #7
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PIC_XB(,r0, lsl #2)
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nop
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@ -920,6 +871,23 @@ crl_algo7:
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crl_algo_done:
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@ -- PHASE UPDATE --
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add lr, lr, #0x10
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ldmia lr, {r1-r3,r5-r7}
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add r1, r1, r6
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add r2, r2, r7
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ldr r6, [lr, #0x18]
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ldr r7, [lr, #0x1c]
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add r3, r3, r6
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add r5, r5, r7
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stmia lr, {r1-r3,r5}
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sub lr, lr, #0x10
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subs r8, r8, #(1<<EG_SH)
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bge crl_smp_loop
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crl_smp_loop_end:
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add r8, r8, #(1<<EG_SH)
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@ -- WRITE SAMPLE --
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tst r0, r0
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beq ctl_sample_skip
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@ -944,36 +912,20 @@ crl_algo_done:
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addeq r11, r11, #4
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addne r1, r0, r1
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strne r1, [r11], #4
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b crl_do_phase
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b crl_loop
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ctl_sample_mono:
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ldr r1, [r11]
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add r1, r0, r1
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str r1, [r11], #4
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b crl_do_phase
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b crl_loop
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ctl_sample_skip:
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and r1, r12, #1
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add r1, r1, #1
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add r11,r11, r1, lsl #2
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crl_do_phase:
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@ -- PHASE UPDATE --
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add r5, lr, #0x10
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ldmia r5, {r0-r3,r6-r7}
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add r0, r0, r6
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add r1, r1, r7
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ldr r6, [r5, #0x18]
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ldr r7, [r5, #0x1c]
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add r2, r2, r6
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add r3, r3, r7
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stmia r5, {r0-r3}
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tst r12, #8
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bne crl_loop_lfo
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b crl_loop
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crl_loop_end:
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str r8, [lr, #0x44] @ eg_timer
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str r12, [lr, #0x4c] @ pack (for lfo_ampm)
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