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sh2 drc: revised ARM A32 backend optimizer
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kub
parent
a002255e35
commit
d39eb595bb
1 changed files with 61 additions and 80 deletions
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@ -36,8 +36,7 @@
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#define SR 16 // CPSR, status register
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#define MEM 17 // memory access (src=LDR, dst=STR)
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#define CYC1 20 // 1 cycle interlock (LDR, reg-cntrld shift)
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#define CYC2 21 // 2+ cycles interlock (LDR[BH], MUL/MLA etc)
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#define SWAP 31 // swapped
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#define CYC2 (CYC1+1)// 2+ cycles interlock (LDR[BH], MUL/MLA etc)
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#define NO 32 // token for "no register"
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// bitmask builders
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@ -46,6 +45,7 @@
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#define M3(x,y,z) (M2(x,y)|M1(z))
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#define M4(x,y,z,a) (M3(x,y,z)|M1(a))
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#define M5(x,y,z,a,b) (M4(x,y,z,a)|M1(b))
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#define M6(x,y,z,a,b,c) (M5(x,y,z,a,b)|M1(c))
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#define M10(a,b,c,d,e,f,g,h,i,j) (M5(a,b,c,d,e)|M5(f,g,h,i,j))
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// sys_cacheflush always flushes whole pages, and it's rather expensive on ARMs
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@ -90,94 +90,81 @@ static inline void emith_update_add(void *base, void *end)
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}
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// peephole optimizer. ATM only tries to reduce interlock
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#define EMIT_CACHE_SIZE 3
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#define EMIT_CACHE_SIZE 6
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struct emit_op {
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u32 op;
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u32 src, dst;
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};
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// peephole cache, last commited insn + cache + next insn + empty insn = size+3
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static struct emit_op emit_cache[EMIT_CACHE_SIZE+3];
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// peephole cache, last commited insn + cache + next insn = size+2
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static struct emit_op emit_cache[EMIT_CACHE_SIZE+2];
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static int emit_index;
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#define emith_insn_ptr() (u8 *)((u32 *)tcache_ptr-emit_index)
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static inline int emith_pool_index(int tcache_offs);
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static inline void emith_pool_adjust(int pool_index, int move_offs);
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static inline void emith_pool_adjust(int tcache_offs, int move_offs);
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static NOINLINE void EMIT(u32 op, u32 dst, u32 src)
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{
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void *emit_ptr = (u32 *)tcache_ptr - emit_index;
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int i;
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void * emit_ptr = (u32 *)tcache_ptr - emit_index;
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struct emit_op *const ptr = emit_cache;
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const int n = emit_index+1;
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int i, bi, bd = 0;
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EMIT_PTR(tcache_ptr, op); // emit to keep tcache_ptr current
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// account for new insn in tcache
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tcache_ptr = (void *)((u32 *)tcache_ptr + 1);
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COUNT_OP;
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// for conditional execution SR is always source
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if (op < 0xe0000000 /*A_COND_AL << 28*/)
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src |= M1(SR);
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// put insn on back of queue
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emit_cache[emit_index+1].op = op;
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emit_cache[emit_index+1].src = src & ~M1(NO); // mask away the NO token
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emit_cache[emit_index+1].dst = dst & ~M1(NO);
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// move insn down in the queue as long as permitted by dependencies
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for (i = emit_index-1; i > 0; i--) {
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struct emit_op *ptr = &emit_cache[i];
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// put insn on back of queue // mask away the NO token
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emit_cache[n] = (struct emit_op)
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{ .op=op, .src=src & ~M1(NO), .dst=dst & ~M1(NO) };
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// check insns down the queue as long as permitted by dependencies
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for (bd = bi = 0, i = emit_index; i > 1 && !(dst & M1(PC)); i--) {
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int deps = 0;
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// never swap branch insns (changes semantics)
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if ((ptr[0].dst | ptr[1].dst) & M1(PC))
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continue;
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// dst deps between 0 and 1 must not be swapped, since any deps
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// but [0].src & [1].src lead to changed semantics if swapped.
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if ((ptr[0].dst & ptr[1].src) || (ptr[1].dst & ptr[0].src) ||
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(ptr[0].dst & ptr[1].dst))
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continue;
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#if 1
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// just move loads as far up as possible
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deps -= !!(ptr[1].src & M1(MEM));
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deps += !!(ptr[0].src & M1(MEM));
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#elif 0
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// treat all dest->src deps as a potential interlock
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#define DEP_INSN(x,y) !!(ptr[x].dst & ptr[y].src)
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// insn sequence: -1, 0, 1, 2
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deps -= DEP_INSN(1,2) + DEP_INSN(-1,0);
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deps -= !!(ptr[1].src & M1(MEM)); // favour moving LDR's down
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// insn sequence: -1, 1, 0, 2
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deps += DEP_INSN(0,2) + DEP_INSN(-1,1);
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deps += !!(ptr[0].src & M1(SWAP)); // penalise if swapped
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#else
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// calculate ARM920T interlock cycles
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#define DEP_CYC1(x,y) ((ptr[x].dst & ptr[y].src)&&(ptr[x].src & M1(CYC1)))
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#define DEP_CYC2(x,y) ((ptr[x].dst & ptr[y].src)&&(ptr[x].src & M1(CYC2)))
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#define DEP_INSN(x,y,z) DEP_CYC1(x,y)+DEP_CYC1(y,z)+2*DEP_CYC2(x,y)+DEP_CYC2(x,z)
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// insn sequence: -1, 0, 1, 2
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deps -= DEP_INSN(0,1,2) + DEP_INSN(-1,0,1);
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deps -= !!(ptr[1].src & M1(MEM)); // favour moving LDR's down
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// insn sequence: -1, 1, 0, 2
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deps += DEP_INSN(0,2,1) + DEP_INSN(-1,1,0);
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deps += !!(ptr[0].src & M1(SWAP)); // penalise multiple swaps
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#endif
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// dst deps between i and n must not be swapped, since any deps
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// but [i].src & [n].src lead to changed semantics if swapped.
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if ((ptr[i].dst & ptr[n].src) || (ptr[n].dst & ptr[i].src) ||
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(ptr[i].dst & ptr[n].dst))
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break;
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// don't swap insns reading PC if it's not a word pool load
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// (ptr[i].op&0xf700000) != EOP_C_AM2_IMM(0,0,0,1,0,0,0))
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if ((ptr[i].src & M1(PC)) && (ptr[i].op&0xf700000) != 0x5100000)
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break;
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// calculate ARM920T interlock cycles (differences only)
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#define D2(x,y) ((ptr[x].dst & ptr[y].src)?((ptr[x].src >> CYC2) & 1):0)
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#define D1(x,y) ((ptr[x].dst & ptr[y].src)?((ptr[x].src >> CYC1) & 3):0)
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// insn sequence: [..., i-2, i-1, i, i+1, ..., n-2, n-1, n]
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deps -= D2(i-2,i)+D2(i-1,i+1)+D2(n-2,n ) + D1(i-1,i)+D1(n-1,n);
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deps -= !!(ptr[n].src & M2(CYC1,CYC2));// favour moving LDR down
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// insn sequence: [..., i-2, i-1, n, i, i+1, ..., n-2, n-1]
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deps += D2(i-2,n)+D2(i-1,i )+D2(n ,i+1) + D1(i-1,n)+D1(n ,i);
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deps += !!(ptr[i].src & M2(CYC1,CYC2));// penalize moving LDR up
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// remember best match found
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if (bd > deps)
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bd = deps, bi = i;
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}
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// swap if fewer depencies
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if (deps < 0) {
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// swap insn reading PC only if uncomitted pool load
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struct emit_op tmp;
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int i0 = -1, i1 = -1;
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if ((!(ptr[0].src & M1(PC)) ||
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(i0 = emith_pool_index(emit_index+2 - i)) >= 0) &&
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(!(ptr[1].src & M1(PC)) ||
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(i1 = emith_pool_index(emit_index+1 - i)) >= 0)) {
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// not using PC, or pool load
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emith_pool_adjust(i0, 1);
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emith_pool_adjust(i1, -1);
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tmp = ptr[0], ptr[0] = ptr[1], ptr[1] = tmp;
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ptr[0].src |= M1(SWAP);
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}
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if (bd < 0) {
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// make room for new insn at bi
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struct emit_op tmp = ptr[n];
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for (i = n-1; i >= bi; i--) {
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ptr[i+1] = ptr[i];
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if (ptr[i].src & M1(PC))
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emith_pool_adjust(n-i+1, 1);
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}
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// insert new insn at bi
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ptr[bi] = tmp;
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if (ptr[bi].src & M1(PC))
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emith_pool_adjust(1, bi-n);
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}
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if (dst & M1(PC)) {
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// commit everything if a branch insn is emitted
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for (i = 1; i <= emit_index+1; i++)
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EMIT_PTR(emit_ptr, emit_cache[i].op);
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emit_index = 0;
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} else if (emit_index <= EMIT_CACHE_SIZE) {
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} else if (emit_index < EMIT_CACHE_SIZE) {
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// queue not yet full
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emit_index++;
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} else {
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@ -412,13 +399,13 @@ static void emith_flush(void)
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EMIT(((cond)<<28) | ((s)<<20) | ((rd)<<16) | ((rs)<<8) | 0x90 | (rm), M2(rd,s?SR:NO), M3(rs,rm,CYC2))
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#define EOP_C_UMULL(cond,s,rdhi,rdlo,rs,rm) \
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EMIT(((cond)<<28) | 0x00800000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm), M3(rdhi,rdlo,s?SR:NO), M3(rs,rm,CYC2))
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EMIT(((cond)<<28) | 0x00800000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm), M3(rdhi,rdlo,s?SR:NO), M4(rs,rm,CYC1,CYC2))
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#define EOP_C_SMULL(cond,s,rdhi,rdlo,rs,rm) \
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EMIT(((cond)<<28) | 0x00c00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm), M3(rdhi,rdlo,s?SR:NO), M3(rs,rm,CYC2))
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EMIT(((cond)<<28) | 0x00c00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm), M3(rdhi,rdlo,s?SR:NO), M4(rs,rm,CYC1,CYC2))
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#define EOP_C_SMLAL(cond,s,rdhi,rdlo,rs,rm) \
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EMIT(((cond)<<28) | 0x00e00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm), M3(rdhi,rdlo,s?SR:NO), M5(rs,rm,rdlo,rdhi,CYC2))
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EMIT(((cond)<<28) | 0x00e00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm), M3(rdhi,rdlo,s?SR:NO), M6(rs,rm,rdlo,rdhi,CYC1,CYC2))
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#define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm
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@ -502,10 +489,10 @@ static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int
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return;
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}
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#else
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for (i = 3, u = v; i > 0; i--, u >>= 8)
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for (i = 2, u = v; i > 0; i--, u >>= 8)
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while (u > 0xff && !(u & 3))
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u >>= 2;
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if (u) { // 4 insns needed...
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if (u) { // 3+ insns needed...
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if (op == A_OP_MVN)
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imm = ~imm;
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// ...emit literal load
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@ -660,21 +647,14 @@ static inline void emith_pool_check(void)
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emith_pool_commit(1);
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}
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static inline int emith_pool_index(int tcache_offs)
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static inline void emith_pool_adjust(int tcache_offs, int move_offs)
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{
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u32 *ptr = (u32 *)tcache_ptr - tcache_offs;
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int i;
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for (i = literal_iindex-1; i >= 0 && literal_insn[i] >= ptr; i--)
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if (literal_insn[i] == ptr)
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return i;
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return -1;
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}
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static inline void emith_pool_adjust(int pool_index, int move_offs)
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{
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if (pool_index >= 0)
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literal_insn[pool_index] += move_offs;
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literal_insn[i] += move_offs;
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}
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#define EMITH_HINT_COND(cond) /**/
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@ -938,6 +918,7 @@ static inline void emith_pool_adjust(int pool_index, int move_offs)
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emith_top_imm(cond, A_OP_TST, r, imm)
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#define emith_move_r_imm_s8_patchable(r, imm) do { \
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emith_flush(); /* pin insn at current tcache_ptr for patching */ \
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if ((s8)(imm) < 0) \
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EOP_MVN_IMM(r, 0, (u8)~(imm)); \
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else \
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