mirror of
https://github.com/RaySollium99/picodrive.git
synced 2025-09-05 07:17:45 -04:00
various small improvements and fixes
This commit is contained in:
kub
parent
f133766faa
commit
d40a5af495
32 changed files with 372 additions and 241 deletions
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@ -14,6 +14,7 @@
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#include "cz80.h"
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#if PICODRIVE_HACKS
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#include <pico/pico_int.h>
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#include <pico/memory.h>
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#endif
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@ -1,9 +1,3 @@
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typedef unsigned char u8;
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typedef signed char s8;
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typedef unsigned short u16;
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typedef signed short s16;
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typedef unsigned int u32;
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typedef signed int s32;
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#define DRC_TCACHE_SIZE (4*1024*1024)
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@ -177,26 +177,25 @@
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#define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm) EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
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/* ldr and str */
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#define EOP_LDR_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,0,1,rn,rd,offset_12)
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#define EOP_LDRB_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,1,1,rn,rd,offset_12)
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#define EOP_LDR_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,(offset_12) >= 0,0,1,rn,rd,abs(offset_12))
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#define EOP_LDRB_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,(offset_12) >= 0,1,1,rn,rd,abs(offset_12))
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#define EOP_STR_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,(offset_12) >= 0,0,0,rn,rd,abs(offset_12))
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#define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
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#define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
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#define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,(offset_12) >= 0,0,1,rn,rd,abs(offset_12))
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#define EOP_LDR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
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#define EOP_STR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
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#define EOP_STR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,(offset_12) >= 0,0,0,rn,rd,abs(offset_12))
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#define EOP_STR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
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#define EOP_LDR_REG_LSL(cond,rd,rn,rm,shift_imm) EOP_C_AM2_REG(cond,1,0,1,rn,rd,shift_imm,A_AM1_LSL,rm)
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#define EOP_LDRB_REG_LSL(cond,rd,rn,rm,shift_imm) EOP_C_AM2_REG(cond,1,1,1,rn,rd,shift_imm,A_AM1_LSL,rm);
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#define EOP_LDRH_IMM2(cond,rd,rn,offset_8) EOP_C_AM3_IMM(cond,1,1,rn,rd,0,1,offset_8)
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#define EOP_LDRH_IMM2(cond,rd,rn,offset_8) EOP_C_AM3_IMM(cond,(offset_8) >= 0,1,rn,rd,0,1,abs(offset_8))
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#define EOP_LDRH_REG2(cond,rd,rn,rm) EOP_C_AM3_REG(cond,1,1,rn,rd,0,1,rm)
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#define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
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#define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,(offset_8) >= 0,1,rn,rd,0,1,abs(offset_8))
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#define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
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#define EOP_LDRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
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#define EOP_STRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
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#define EOP_STRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,(offset_8) >= 0,0,rn,rd,0,1,abs(offset_8))
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#define EOP_STRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
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#define EOP_STRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,0,rn,rd,0,1,rm)
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@ -285,11 +284,29 @@ static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int
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imm = ~imm;
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op = A_OP_MVN;
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}
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#ifdef HAVE_ARMV7
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for (v = imm, ror2 = 0; v && !(v & 3); v >>= 2)
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ror2--;
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if (v >> 8) {
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/* 2+ insns needed - prefer movw/movt */
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if (op == A_OP_MVN)
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imm = ~imm;
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EOP_MOVW(rd, imm);
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if (imm & 0xffff0000)
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EOP_MOVT(rd, imm);
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return;
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}
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#endif
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break;
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case A_OP_EOR:
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case A_OP_SUB:
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case A_OP_ADD:
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// count bits in imm and swap ADD and SUB if more bits 1 than 0
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if (s == 0 && count_bits(imm) > 16) {
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imm = -imm;
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op ^= (A_OP_ADD^A_OP_SUB);
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}
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case A_OP_EOR:
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case A_OP_ORR:
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case A_OP_BIC:
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if (s == 0 && imm == 0 && rd == rn)
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@ -412,6 +429,8 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_add_r_r_r_lsl(d, s1, s2, lslimm) \
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EOP_ADD_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
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#define emith_add_r_r_r_lsl_ptr(d, s1, s2, lslimm) \
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emith_add_r_r_r_lsl(d, s1, s2, lslimm)
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#define emith_addf_r_r_r_lsl(d, s1, s2, lslimm) \
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EOP_ADD_REG(A_COND_AL,1,d,s1,s2,A_AM1_LSL,lslimm)
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@ -483,7 +502,7 @@ static int emith_xbranch(int cond, void *target, int is_call)
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emith_add_r_r_r(d, d, s)
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#define emith_sub_r_r(d, s) \
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EOP_SUB_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
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emith_sub_r_r_r(d, d, s)
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#define emith_adc_r_r(d, s) \
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EOP_ADC_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
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@ -529,6 +548,9 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_move_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_MOV, r, imm)
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#define emith_move_r_ptr_imm(r, imm) \
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emith_move_r_imm(r, (u32)(imm))
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#define emith_add_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_ADD, r, imm)
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@ -536,7 +558,7 @@ static int emith_xbranch(int cond, void *target, int is_call)
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emith_op_imm(A_COND_AL, 0, A_OP_ADC, r, imm)
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#define emith_adcf_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 1, A_OP_ADC, r, (imm))
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emith_op_imm(A_COND_AL, 1, A_OP_ADC, r, imm)
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#define emith_sub_r_imm(r, imm) \
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emith_op_imm(A_COND_AL, 0, A_OP_SUB, r, imm)
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@ -610,13 +632,13 @@ static int emith_xbranch(int cond, void *target, int is_call)
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emith_op_imm2(A_COND_AL, 0, A_OP_SUB, d, s, imm)
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#define emith_subf_r_r_imm(d, s, imm) \
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emith_op_imm2(A_COND_AL, 1, A_OP_SUB, d, s, (imm))
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emith_op_imm2(A_COND_AL, 1, A_OP_SUB, d, s, imm)
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#define emith_or_r_r_imm(d, s, imm) \
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emith_op_imm2(A_COND_AL, 0, A_OP_ORR, d, s, (imm))
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emith_op_imm2(A_COND_AL, 0, A_OP_ORR, d, s, imm)
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#define emith_eor_r_r_imm(d, s, imm) \
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emith_op_imm2(A_COND_AL, 0, A_OP_EOR, d, s, (imm))
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emith_op_imm2(A_COND_AL, 0, A_OP_EOR, d, s, imm)
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#define emith_neg_r_r(d, s) \
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EOP_RSB_IMM(d, s, 0, 0)
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@ -758,7 +780,7 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_clear_msb_c(cond, d, s, count) { \
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u32 t; \
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if ((count) <= 8) { \
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t = (count) - 8; \
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t = 8 - (count); \
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t = (0xff << t) & 0xff; \
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EOP_C_DOP_IMM(cond,A_OP_BIC,0,s,d,8/2,t); \
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} else if ((count) >= 24) { \
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@ -880,7 +902,9 @@ static int emith_xbranch(int cond, void *target, int is_call)
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#define emith_sh2_rcall(a, tab, func, mask) { \
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emith_lsr(mask, a, SH2_READ_SHIFT); \
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EOP_ADD_REG_LSL(tab, tab, mask, 3); \
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EOP_LDMIA(tab, (1<<func)|(1<<mask)); \
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if (func < mask) EOP_LDMIA(tab, (1<<func)|(1<<mask)); /* ldm if possible */ \
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else { emith_read_r_r_offs(func, tab, 0); \
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emith_read_r_r_offs(mask, tab, 4); } \
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emith_addf_r_r_r(func,func,func); \
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}
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@ -194,6 +194,17 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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} \
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} while (0)
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#define emith_add_r_r_r_ptr(d, s1, s2) do { \
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if (d == s1) { \
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emith_add_r_r_ptr(d, s2); \
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} else if (d == s2) { \
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emith_add_r_r_ptr(d, s1); \
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} else { \
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emith_move_r_r_ptr(d, s1); \
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emith_add_r_r_ptr(d, s2); \
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} \
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} while (0)
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#define emith_sub_r_r_r(d, s1, s2) do { \
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if (d == s1) { \
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emith_sub_r_r(d, s2); \
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@ -268,9 +279,16 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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rcache_free_tmp(tmp_); \
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} while (0)
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#define emith_add_r_r_r_lsr(d, s1, s2, lslimm) do { \
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#define emith_add_r_r_r_lsl_ptr(d, s1, s2, lslimm) do { \
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int tmp_ = rcache_get_tmp(); \
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emith_lsr(tmp_, s2, lslimm); \
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emith_lsl(tmp_, s2, lslimm); \
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emith_add_r_r_r_ptr(d, s1, tmp_); \
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rcache_free_tmp(tmp_); \
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} while (0)
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#define emith_add_r_r_r_lsr(d, s1, s2, lsrimm) do { \
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int tmp_ = rcache_get_tmp(); \
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emith_lsr(tmp_, s2, lsrimm); \
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emith_add_r_r_r(d, s1, tmp_); \
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rcache_free_tmp(tmp_); \
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} while (0)
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@ -297,6 +315,16 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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EMIT(imm, u32); \
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} while (0)
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#define emith_move_r_ptr_imm(r, imm) do { \
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if ((uint64_t)(imm) <= UINT32_MAX) \
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emith_move_r_imm(r, (uintptr_t)(imm)); \
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else { \
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EMIT_REX_IF(1, 0, r); \
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EMIT_OP(0xb8 + (r)); \
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EMIT((uint64_t)(imm), uint64_t); \
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} \
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} while (0)
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#define emith_move_r_imm_s8(r, imm) \
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emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))
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@ -421,27 +449,28 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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#define emith_sub_r_r_imm(d, s, imm) do { \
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if (d != s) \
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emith_move_r_r(d, s); \
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if (imm) \
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if ((s32)(imm) != 0) \
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emith_sub_r_imm(d, imm); \
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} while (0)
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#define emith_and_r_r_imm(d, s, imm) do { \
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if (d != s) \
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emith_move_r_r(d, s); \
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emith_and_r_imm(d, imm); \
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if ((s32)(imm) != -1) \
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emith_and_r_imm(d, imm); \
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} while (0)
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#define emith_or_r_r_imm(d, s, imm) do { \
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if (d != s) \
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emith_move_r_r(d, s); \
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if ((s32)imm != 0) \
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if ((s32)(imm) != 0) \
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emith_or_r_imm(d, imm); \
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} while (0)
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#define emith_eor_r_r_imm(d, s, imm) do { \
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if (d != s) \
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emith_move_r_r(d, s); \
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if ((s32)imm != 0) \
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if ((s32)(imm) != 0) \
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emith_eor_r_imm(d, imm); \
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} while (0)
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@ -612,31 +641,17 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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EMIT_REX_IF(1, r, rs); \
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emith_deref_op(0x89, r, rs, offs)
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// note: don't use prefixes on this
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#define emith_read8_r_r_offs(r, rs, offs) do { \
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int r_ = r; \
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if (!is_abcdx(r)) \
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r_ = rcache_get_tmp(); \
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EMIT(0x0f, u8); \
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emith_deref_op(0xb6, r_, rs, offs); \
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if ((r) != r_) { \
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emith_move_r_r(r, r_); \
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rcache_free_tmp(r_); \
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} \
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emith_deref_op(0xb6, r, rs, offs); \
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} while (0)
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#define emith_read8s_r_r_offs(r, rs, offs) do { \
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int r_ = r; \
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if (!is_abcdx(r)) \
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r_ = rcache_get_tmp(); \
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EMIT(0x0f, u8); \
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emith_deref_op(0xbe, r_, rs, offs); \
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if ((r) != r_) { \
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emith_move_r_r(r, r_); \
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rcache_free_tmp(r_); \
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} \
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emith_deref_op(0xbe, r, rs, offs); \
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} while (0)
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// note: don't use prefixes on this
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#define emith_write8_r_r_offs(r, rs, offs) do {\
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int r_ = r; \
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if (!is_abcdx(r)) { \
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@ -664,16 +679,9 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
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} while (0)
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#define emith_read8_r_r_r(r, rs, rm) do { \
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int r_ = r; \
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if (!is_abcdx(r)) \
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r_ = rcache_get_tmp(); \
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EMIT(0x0f, u8); \
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EMIT_OP_MODRM(0xb6, 0, r, 4); \
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EMIT_SIB(0, rs, rm); /* mov r, [rm + rs * 1] */ \
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if ((r) != r_) { \
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emith_move_r_r(r, r_); \
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rcache_free_tmp(r_); \
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} \
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} while (0)
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#define emith_read16_r_r_r(r, rs, rm) do { \
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@ -56,9 +56,10 @@
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// 04 - asm
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// 08 - runtime block entry log
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// 10 - smc self-check
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// 20 - runtime block entry counter
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// 100 - write trace
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// 200 - compare trace
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// 400 - block entry backtraceA on exit
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// 400 - block entry backtrace on exit
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// 800 - state dump on exit
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// {
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#ifndef DRC_DEBUG
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@ -178,7 +179,7 @@ static char sh2dasm_buff[64];
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}
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#if (DRC_DEBUG & (8|256|512|1024)) || defined(PDB)
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static SH2 csh2[2][4];
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static SH2 csh2[2][8];
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static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr)
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{
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if (block != NULL) {
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@ -190,7 +191,6 @@ static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr)
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{
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static FILE *trace[2];
|
||||
int idx = sh2->is_slave;
|
||||
if (sh2 != &sh2s[0] && sh2 != &sh2s[1]) printf("sh2 %p?\n",sh2);
|
||||
if (!trace[0]) {
|
||||
truncate("pico.trace", 0);
|
||||
trace[0] = fopen("pico.trace0", "wb");
|
||||
|
|
@ -199,7 +199,8 @@ if (sh2 != &sh2s[0] && sh2 != &sh2s[1]) printf("sh2 %p?\n",sh2);
|
|||
if (csh2[idx][0].pc != sh2->pc) {
|
||||
fwrite(sh2, offsetof(SH2, read8_map), 1, trace[idx]);
|
||||
fwrite(&sh2->pdb_io_csum, sizeof(sh2->pdb_io_csum), 1, trace[idx]);
|
||||
memcpy(&csh2[idx][0], sh2, offsetof(SH2, icount));
|
||||
memcpy(&csh2[idx][0], sh2, offsetof(SH2, poll_cnt)+4);
|
||||
csh2[idx][0].is_slave = idx;
|
||||
}
|
||||
}
|
||||
#elif (DRC_DEBUG & 512)
|
||||
|
|
@ -234,9 +235,10 @@ if (sh2 != &sh2s[0] && sh2 != &sh2s[1]) printf("sh2 %p?\n",sh2);
|
|||
#elif (DRC_DEBUG & 1024)
|
||||
{
|
||||
int x = sh2->is_slave, i;
|
||||
for (i = 0; i < ARRAY_SIZE(csh2[x]); i++)
|
||||
memcpy(&csh2[x][i], &csh2[x][i+1], offsetof(SH2, icount));
|
||||
memcpy(&csh2[x][3], sh2, offsetof(SH2, icount));
|
||||
for (i = 0; i < ARRAY_SIZE(csh2[x])-1; i++)
|
||||
memcpy(&csh2[x][i], &csh2[x][i+1], offsetof(SH2, poll_cnt)+4);
|
||||
memcpy(&csh2[x][ARRAY_SIZE(csh2[x])-1], sh2, offsetof(SH2, poll_cnt)+4);
|
||||
csh2[x][0].is_slave = x;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
@ -252,9 +254,9 @@ if (sh2 != &sh2s[0] && sh2 != &sh2s[1]) printf("sh2 %p?\n",sh2);
|
|||
// and can be discarded early
|
||||
// XXX: need to tune sizes
|
||||
static const int tcache_sizes[TCACHE_BUFFERS] = {
|
||||
DRC_TCACHE_SIZE * 6 / 8, // ROM (rarely used), DRAM
|
||||
DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
|
||||
DRC_TCACHE_SIZE / 8, // ... slave
|
||||
DRC_TCACHE_SIZE * 14 / 16, // ROM (rarely used), DRAM
|
||||
DRC_TCACHE_SIZE / 16, // BIOS, data array in master sh2
|
||||
DRC_TCACHE_SIZE / 16, // ... slave
|
||||
};
|
||||
|
||||
static u8 *tcache_bases[TCACHE_BUFFERS];
|
||||
|
|
@ -287,6 +289,9 @@ struct block_entry {
|
|||
#if (DRC_DEBUG & 2)
|
||||
struct block_desc *block;
|
||||
#endif
|
||||
#if (DRC_DEBUG & 32)
|
||||
int entry_count;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct block_desc {
|
||||
|
|
@ -698,6 +703,14 @@ static void add_to_hashlist(struct block_entry *be, int tcache_id)
|
|||
(*head)->prev = be;
|
||||
be->next = *head;
|
||||
*head = be;
|
||||
|
||||
#if (DRC_DEBUG & 2)
|
||||
if (be->next != NULL) {
|
||||
printf(" %08x: entry hash collision with %08x\n",
|
||||
be->pc, be->next->pc);
|
||||
hash_collisions++;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static void rm_from_hashlist(struct block_entry *be, int tcache_id)
|
||||
|
|
@ -727,6 +740,14 @@ static void add_to_hashlist_unresolved(struct block_link *bl, int tcache_id)
|
|||
u32 tcmask = hash_table_sizes[tcache_id] - 1;
|
||||
struct block_link **head = &HASH_FUNC(unresolved_links[tcache_id], bl->target_pc, tcmask);
|
||||
|
||||
#if DRC_DEBUG & 1
|
||||
struct block_link *current = *head;
|
||||
while (current != NULL && current != bl)
|
||||
current = current->next;
|
||||
if (current == bl)
|
||||
dbg(1, "add_to_hashlist_unresolved @%p: bl %p %p %08x already in?", head, bl, bl->target, bl->target_pc);
|
||||
#endif
|
||||
|
||||
bl->target = NULL; // marker for not resolved
|
||||
bl->prev = NULL;
|
||||
if (*head)
|
||||
|
|
@ -745,7 +766,7 @@ static void rm_from_hashlist_unresolved(struct block_link *bl, int tcache_id)
|
|||
while (current->prev != NULL)
|
||||
current = current->prev;
|
||||
if (current != *head)
|
||||
dbg(1, "rm_from_hashlist unresolved @%p: bl %p %p %08x missing?", head, bl, bl->target, bl->target_pc);
|
||||
dbg(1, "rm_from_hashlist_unresolved @%p: bl %p %p %08x missing?", head, bl, bl->target, bl->target_pc);
|
||||
#endif
|
||||
|
||||
if (bl->prev != NULL)
|
||||
|
|
@ -980,10 +1001,12 @@ static void *dr_prepare_ext_branch(struct block_entry *owner, u32 pc, int is_sla
|
|||
struct block_entry *be = NULL;
|
||||
int target_tcache_id;
|
||||
|
||||
// get the target block entry
|
||||
be = dr_get_entry(pc, is_slave, &target_tcache_id);
|
||||
if (target_tcache_id && target_tcache_id != tcache_id)
|
||||
return sh2_drc_dispatcher;
|
||||
|
||||
// get a block link
|
||||
if (blink_free[tcache_id] != NULL) {
|
||||
bl = blink_free[tcache_id];
|
||||
blink_free[tcache_id] = bl->next;
|
||||
|
|
@ -995,6 +1018,7 @@ static void *dr_prepare_ext_branch(struct block_entry *owner, u32 pc, int is_sla
|
|||
block_link_pool_counts[tcache_id] = cnt+1;
|
||||
}
|
||||
|
||||
// prepare link and add to ougoing list of owner
|
||||
bl->tcache_id = tcache_id;
|
||||
bl->target_pc = pc;
|
||||
bl->jump = tcache_ptr;
|
||||
|
|
@ -1940,6 +1964,7 @@ static void rcache_invalidate(void)
|
|||
cache_regs[i].type = HR_FREE;
|
||||
cache_regs[i].gregs = 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(guest_regs); i++) {
|
||||
guest_regs[i].flags &= GRF_STATIC;
|
||||
if (!(guest_regs[i].flags & GRF_STATIC))
|
||||
|
|
@ -1953,7 +1978,8 @@ static void rcache_invalidate(void)
|
|||
cache_regs[guest_regs[i].sreg].gregs = 1 << i;
|
||||
guest_regs[i].vreg = guest_regs[i].sreg;
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
rcache_counter = 0;
|
||||
rcache_hint_soon = rcache_hint_late = 0;
|
||||
|
||||
|
|
@ -2005,6 +2031,7 @@ static int emit_get_rbase_and_offs(SH2 *sh2, u32 a, u32 *offs)
|
|||
u32 mask = 0;
|
||||
int poffs;
|
||||
int hr;
|
||||
unsigned long la;
|
||||
|
||||
poffs = dr_ctx_get_mem_ptr(a, &mask);
|
||||
if (poffs == -1)
|
||||
|
|
@ -2014,15 +2041,16 @@ static int emit_get_rbase_and_offs(SH2 *sh2, u32 a, u32 *offs)
|
|||
if (mask < 0x1000) {
|
||||
// can't access data array or BIOS directly from ROM or SDRAM,
|
||||
// since code may run on both SH2s (tcache_id of translation block needed))
|
||||
emith_ctx_read(hr, poffs);
|
||||
emith_ctx_read_ptr(hr, poffs);
|
||||
if (a & mask & ~omask)
|
||||
emith_add_r_imm(hr, a & mask & ~omask);
|
||||
emith_add_r_r_ptr_imm(hr, hr, a & mask & ~omask);
|
||||
*offs = a & omask;
|
||||
} else {
|
||||
// known fixed host address
|
||||
a = (a & mask) + *(u32 *)((char *)sh2 + poffs);
|
||||
emith_move_r_imm(hr, (a & ~omask));
|
||||
la = (unsigned long)*(void **)((char *)sh2 + poffs) + (a & mask);
|
||||
*offs = la & omask;
|
||||
emith_move_r_ptr_imm(hr, la & ~omask);
|
||||
}
|
||||
*offs = a & omask;
|
||||
return hr;
|
||||
}
|
||||
|
||||
|
|
@ -2392,8 +2420,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
|
|||
void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
|
||||
u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
|
||||
int branch_patch_count = 0;
|
||||
u32 literal_addr[MAX_LITERALS];
|
||||
int literal_addr_count = 0;
|
||||
u8 op_flags[BLOCK_INSN_LIMIT];
|
||||
struct {
|
||||
u32 test_irq:1;
|
||||
|
|
@ -2473,7 +2499,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
|
|||
{
|
||||
u32 delay_dep_fw = 0, delay_dep_bk = 0;
|
||||
int tmp3, tmp4;
|
||||
u32 sr;
|
||||
int sr;
|
||||
|
||||
opd = &ops[i];
|
||||
op = FETCH_OP(pc);
|
||||
|
|
@ -2487,7 +2513,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
|
|||
pc, op, sh2dasm_buff);
|
||||
#endif
|
||||
|
||||
if ((op_flags[i] & OF_BTARGET) || pc == base_pc)
|
||||
if (op_flags[i] & OF_BTARGET)
|
||||
{
|
||||
if (pc != base_pc)
|
||||
{
|
||||
|
|
@ -2517,6 +2543,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
|
|||
else {
|
||||
dbg(1, "too many entryp for block #%d,%d pc=%08x",
|
||||
tcache_id, blkid_main, pc);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
entry = block->entryp;
|
||||
|
|
@ -2537,10 +2564,10 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
|
|||
|
||||
#if (DRC_DEBUG & 0x10)
|
||||
rcache_get_reg_arg(0, SHR_PC, NULL);
|
||||
tmp = emit_memhandler_read(2);
|
||||
tmp = emit_memhandler_read(1);
|
||||
tmp2 = rcache_get_tmp();
|
||||
tmp3 = rcache_get_tmp();
|
||||
emith_move_r_imm(tmp2, FETCH32(pc));
|
||||
emith_move_r_imm(tmp2, (s16)FETCH_OP(pc));
|
||||
emith_move_r_imm(tmp3, 0);
|
||||
emith_cmp_r_r(tmp, tmp2);
|
||||
EMITH_SJMP_START(DCOND_EQ);
|
||||
|
|
@ -2556,9 +2583,20 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
|
|||
emith_cmp_r_imm(sr, 0);
|
||||
emith_jump_cond(DCOND_LE, sh2_drc_exit);
|
||||
|
||||
#if (DRC_DEBUG & 32)
|
||||
// block hit counter
|
||||
tmp = rcache_get_tmp_arg(0);
|
||||
tmp2 = rcache_get_tmp_arg(1);
|
||||
emith_move_r_ptr_imm(tmp, (uptr)entry);
|
||||
emith_read_r_r_offs(tmp2, tmp, offsetof(struct block_entry, entry_count));
|
||||
emith_add_r_imm(tmp2, 1);
|
||||
emith_write_r_r_offs(tmp2, tmp, offsetof(struct block_entry, entry_count));
|
||||
rcache_free_tmp(tmp);
|
||||
rcache_free_tmp(tmp2);
|
||||
#endif
|
||||
|
||||
#if (DRC_DEBUG & (8|256|512|1024))
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_RMW, NULL);
|
||||
FLUSH_CYCLES(sr);
|
||||
rcache_clean();
|
||||
tmp = rcache_used_hreg_mask();
|
||||
emith_save_caller_regs(tmp);
|
||||
|
|
@ -2566,7 +2604,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
|
|||
rcache_get_reg_arg(2, SHR_SR, NULL);
|
||||
tmp2 = rcache_get_tmp_arg(0);
|
||||
tmp3 = rcache_get_tmp_arg(1);
|
||||
emith_move_r_imm(tmp2, (u32)tcache_ptr);
|
||||
emith_move_r_ptr_imm(tmp2, tcache_ptr);
|
||||
emith_move_r_r_ptr(tmp3,CONTEXT_REG);
|
||||
emith_call(sh2_drc_log_entry);
|
||||
emith_restore_caller_regs(tmp);
|
||||
|
|
@ -2776,7 +2814,6 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
|
|||
if ((opd->imm && opd->imm >= base_pc && opd->imm < end_literals) ||
|
||||
dr_is_rom(opd->imm))
|
||||
{
|
||||
ADD_TO_ARRAY(literal_addr, literal_addr_count, opd->imm,);
|
||||
if (opd->size == 2)
|
||||
u = FETCH32(opd->imm);
|
||||
else
|
||||
|
|
@ -2862,8 +2899,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
|
|||
case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
|
||||
emit_indirect_indexed_write(sh2, GET_Rm(), SHR_R0, GET_Rn(), op & 3);
|
||||
goto end_op;
|
||||
case 0x07:
|
||||
// MUL.L Rm,Rn 0000nnnnmmmm0111
|
||||
case 0x07: // MUL.L Rm,Rn 0000nnnnmmmm0111
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_READ, NULL);
|
||||
tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ, NULL);
|
||||
tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE, NULL);
|
||||
|
|
@ -2941,8 +2977,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
|
|||
goto default_;
|
||||
|
||||
/////////////////////////////////////////////
|
||||
case 0x01:
|
||||
// MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
|
||||
case 0x01: // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
|
||||
emit_memhandler_write_rr(sh2, GET_Rm(), GET_Rn(), (op & 0x0f) * 4, 2);
|
||||
goto end_op;
|
||||
|
||||
|
|
@ -3346,19 +3381,16 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
|
|||
case 0x09:
|
||||
switch (GET_Fx())
|
||||
{
|
||||
case 0:
|
||||
// SHLL2 Rn 0100nnnn00001000
|
||||
// SHLR2 Rn 0100nnnn00001001
|
||||
case 0: // SHLL2 Rn 0100nnnn00001000
|
||||
// SHLR2 Rn 0100nnnn00001001
|
||||
tmp = 2;
|
||||
break;
|
||||
case 1:
|
||||
// SHLL8 Rn 0100nnnn00011000
|
||||
// SHLR8 Rn 0100nnnn00011001
|
||||
case 1: // SHLL8 Rn 0100nnnn00011000
|
||||
// SHLR8 Rn 0100nnnn00011001
|
||||
tmp = 8;
|
||||
break;
|
||||
case 2:
|
||||
// SHLL16 Rn 0100nnnn00101000
|
||||
// SHLR16 Rn 0100nnnn00101001
|
||||
case 2: // SHLL16 Rn 0100nnnn00101000
|
||||
// SHLR16 Rn 0100nnnn00101001
|
||||
tmp = 16;
|
||||
break;
|
||||
default:
|
||||
|
|
@ -3432,8 +3464,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
|
|||
} else
|
||||
emit_move_r_r(tmp2, GET_Rn());
|
||||
goto end_op;
|
||||
case 0x0f:
|
||||
// MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
|
||||
case 0x0f: // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
|
||||
emit_indirect_read_double(sh2, &tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
|
||||
sr = rcache_get_reg(SHR_SR, RC_GR_READ, NULL);
|
||||
tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW, NULL);
|
||||
|
|
@ -3446,8 +3477,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
|
|||
goto default_;
|
||||
|
||||
/////////////////////////////////////////////
|
||||
case 0x05:
|
||||
// MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
|
||||
case 0x05: // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
|
||||
emit_memhandler_read_rr(sh2, GET_Rn(), GET_Rm(), (op & 0x0f) * 4, 2);
|
||||
goto end_op;
|
||||
|
||||
|
|
@ -3519,8 +3549,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
|
|||
goto default_;
|
||||
|
||||
/////////////////////////////////////////////
|
||||
case 0x07:
|
||||
// ADD #imm,Rn 0111nnnniiiiiiii
|
||||
case 0x07: // ADD #imm,Rn 0111nnnniiiiiiii
|
||||
tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW, &tmp2);
|
||||
if (op & 0x80) { // adding negative
|
||||
emith_sub_r_r_imm(tmp, tmp2, -op & 0xff);
|
||||
|
|
@ -3621,8 +3650,7 @@ static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
|
|||
goto default_;
|
||||
|
||||
/////////////////////////////////////////////
|
||||
case 0x0e:
|
||||
// MOV #imm,Rn 1110nnnniiiiiiii
|
||||
case 0x0e: // MOV #imm,Rn 1110nnnniiiiiiii
|
||||
emit_move_r_imm32(GET_Rn(), (s8)op);
|
||||
goto end_op;
|
||||
|
||||
|
|
@ -3886,9 +3914,7 @@ static void sh2_generate_utils(void)
|
|||
#if BRANCH_CACHE
|
||||
// check if PC is in branch target cache
|
||||
emith_and_r_r_imm(arg1, arg0, (ARRAY_SIZE(sh2s->branch_cache)-1)*4);
|
||||
// TODO implement emith_add_r_r_r_lsl_ptr, saves one insn on 32bit ARM
|
||||
emith_lsl(arg1, arg1, sizeof(void *) == 8 ? 2 : 1);
|
||||
emith_add_r_r_ptr(arg1, CONTEXT_REG);
|
||||
emith_add_r_r_r_lsl_ptr(arg1, CONTEXT_REG, arg1, sizeof(void *) == 8 ? 2 : 1);
|
||||
emith_read_r_r_offs(arg2, arg1, offsetof(SH2, branch_cache));
|
||||
emith_cmp_r_r(arg2, arg0);
|
||||
EMITH_SJMP_START(DCOND_NE);
|
||||
|
|
@ -3905,8 +3931,7 @@ static void sh2_generate_utils(void)
|
|||
EMITH_SJMP_START(DCOND_EQ);
|
||||
emith_ctx_read_c(DCOND_NE, arg2, SHR_PC * 4);
|
||||
emith_and_r_r_imm(arg1, arg2, (ARRAY_SIZE(sh2s->branch_cache)-1)*4);
|
||||
emith_lsl(arg1, arg1, sizeof(void *) == 8 ? 2 : 1);
|
||||
emith_add_r_r_ptr(arg1, CONTEXT_REG);
|
||||
emith_add_r_r_r_lsl_ptr(arg1, CONTEXT_REG, arg1, sizeof(void *) == 8 ? 2 : 1);
|
||||
emith_write_r_r_offs_c(DCOND_NE, arg2, arg1, offsetof(SH2, branch_cache));
|
||||
emith_write_r_r_offs_ptr_c(DCOND_NE, RET_REG, arg1, offsetof(SH2, branch_cache) + sizeof(void *));
|
||||
EMITH_SJMP_END(DCOND_EQ);
|
||||
|
|
@ -4174,7 +4199,8 @@ int sh2_execute_drc(SH2 *sh2c, int cycles)
|
|||
static void block_stats(void)
|
||||
{
|
||||
#if (DRC_DEBUG & 2)
|
||||
int c, b, i, total = 0;
|
||||
int c, b, i;
|
||||
long total = 0;
|
||||
|
||||
printf("block stats:\n");
|
||||
for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
|
||||
|
|
@ -4185,8 +4211,9 @@ static void block_stats(void)
|
|||
if (block_tables[b][i].addr != 0)
|
||||
total += block_tables[b][i].refcount;
|
||||
}
|
||||
printf("total: %ld\n",total);
|
||||
|
||||
for (c = 0; c < 10; c++) {
|
||||
for (c = 0; c < 20; c++) {
|
||||
struct block_desc *blk, *maxb = NULL;
|
||||
int max = 0;
|
||||
for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
|
||||
|
|
@ -4221,6 +4248,63 @@ static void block_stats(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
void entry_stats(void)
|
||||
{
|
||||
#if (DRC_DEBUG & 32)
|
||||
int c, b, i, j;
|
||||
long total = 0;
|
||||
|
||||
printf("block entry stats:\n");
|
||||
for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
|
||||
for (i = 0; i < block_counts[b]; i++)
|
||||
for (j = 0; j < block_tables[b][i].entry_count; j++)
|
||||
total += block_tables[b][i].entryp[j].entry_count;
|
||||
for (i = block_limit[b]; i < block_max_counts[b]; i++)
|
||||
for (j = 0; j < block_tables[b][i].entry_count; j++)
|
||||
total += block_tables[b][i].entryp[j].entry_count;
|
||||
}
|
||||
printf("total: %ld\n",total);
|
||||
|
||||
for (c = 0; c < 20; c++) {
|
||||
struct block_desc *blk;
|
||||
struct block_entry *maxb = NULL;
|
||||
int max = 0;
|
||||
for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
|
||||
for (i = 0; i < block_counts[b]; i++) {
|
||||
blk = &block_tables[b][i];
|
||||
for (j = 0; j < blk->entry_count; j++)
|
||||
if (blk->entryp[j].entry_count > max) {
|
||||
max = blk->entryp[j].entry_count;
|
||||
maxb = &blk->entryp[j];
|
||||
}
|
||||
}
|
||||
for (i = block_limit[b]; i < block_max_counts[b]; i++) {
|
||||
blk = &block_tables[b][i];
|
||||
for (j = 0; j < blk->entry_count; j++)
|
||||
if (blk->entryp[j].entry_count > max) {
|
||||
max = blk->entryp[j].entry_count;
|
||||
maxb = &blk->entryp[j];
|
||||
}
|
||||
}
|
||||
}
|
||||
if (maxb == NULL)
|
||||
break;
|
||||
printf("%08x %p %9d %2.3f%%\n", maxb->pc, maxb->tcache_ptr, maxb->entry_count,
|
||||
(double)100 * maxb->entry_count / total);
|
||||
maxb->entry_count = 0;
|
||||
}
|
||||
|
||||
for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
|
||||
for (i = 0; i < block_counts[b]; i++)
|
||||
for (j = 0; j < block_tables[b][i].entry_count; j++)
|
||||
block_tables[b][i].entryp[j].entry_count = 0;
|
||||
for (i = block_limit[b]; i < block_max_counts[b]; i++)
|
||||
for (j = 0; j < block_tables[b][i].entry_count; j++)
|
||||
block_tables[b][i].entryp[j].entry_count = 0;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static void backtrace(void)
|
||||
{
|
||||
#if (DRC_DEBUG & 1024)
|
||||
|
|
@ -4279,6 +4363,7 @@ void sh2_drc_flush_all(void)
|
|||
backtrace();
|
||||
state_dump();
|
||||
block_stats();
|
||||
entry_stats();
|
||||
flush_tcache(0);
|
||||
flush_tcache(1);
|
||||
flush_tcache(2);
|
||||
|
|
@ -4364,6 +4449,7 @@ int sh2_drc_init(SH2 *sh2)
|
|||
hash_collisions = 0;
|
||||
#endif
|
||||
}
|
||||
memset(sh2->branch_cache, -1, sizeof(sh2->branch_cache));
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -214,7 +214,7 @@ int sh2_execute_interpreter(SH2 *sh2, int cycles)
|
|||
if (sh2->pc < *base_pc || sh2->pc >= *end_pc) {
|
||||
*base_pc = sh2->pc;
|
||||
scan_block(*base_pc, sh2->is_slave,
|
||||
op_flags, end_pc, NULL);
|
||||
op_flags, end_pc, NULL, NULL);
|
||||
}
|
||||
if ((op_flags[(sh2->pc - *base_pc) / 2]
|
||||
& OF_BTARGET) || sh2->pc == *base_pc
|
||||
|
|
|
|||
|
|
@ -81,9 +81,9 @@ typedef struct SH2_
|
|||
|
||||
#define CYCLE_MULT_SHIFT 10
|
||||
#define C_M68K_TO_SH2(xsh2, c) \
|
||||
((int)((long long)(c) * (xsh2)->mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)
|
||||
(int)(((unsigned long long)(c) * (xsh2)->mult_m68k_to_sh2) >> CYCLE_MULT_SHIFT)
|
||||
#define C_SH2_TO_M68K(xsh2, c) \
|
||||
((int)((long long)(c+3) * (xsh2)->mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)
|
||||
(int)(((unsigned long long)(c+3U) * (xsh2)->mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)
|
||||
|
||||
int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2);
|
||||
void sh2_finish(SH2 *sh2);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue