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various small improvements and fixes

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This commit is contained in:
kub 2019-04-16 20:37:52 +02:00
parent f133766faa
commit d40a5af495
32 changed files with 372 additions and 241 deletions
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28
pico/32x/32x.c
View file

@ -30,7 +30,7 @@ static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
}
// MUST specify active_sh2 when called from sh2 memhandlers
void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
void p32x_update_irls(SH2 *active_sh2, unsigned int m68k_cycles)
{
int irqs, mlvl = 0, slvl = 0;
int mrun, srun;
@ -50,18 +50,18 @@ void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
slvl++;
slvl *= 2;
mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 == &msh2);
mrun = sh2_irl_irq(&msh2, mlvl, msh2.state & SH2_STATE_RUN);
if (mrun) {
p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
if (active_sh2 == &msh2)
sh2_end_run(active_sh2, 1);
if (msh2.state & SH2_STATE_RUN)
sh2_end_run(&msh2, 1);
}
srun = sh2_irl_irq(&ssh2, slvl, active_sh2 == &ssh2);
srun = sh2_irl_irq(&ssh2, slvl, ssh2.state & SH2_STATE_RUN);
if (srun) {
p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
if (active_sh2 == &ssh2)
sh2_end_run(active_sh2, 1);
if (ssh2.state & SH2_STATE_RUN)
sh2_end_run(&ssh2, 1);
}
elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
@ -70,7 +70,7 @@ void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
// the mask register is inconsistent, CMD is supposed to be a mask,
// while others are actually irq trigger enables?
// TODO: test on hw..
void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask)
void p32x_trigger_irq(SH2 *sh2, unsigned int m68k_cycles, unsigned int mask)
{
Pico32x.sh2irqs |= mask & P32XI_VRES;
Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3);
@ -79,7 +79,7 @@ void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask)
p32x_update_irls(sh2, m68k_cycles);
}
void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles)
void p32x_update_cmd_irq(SH2 *sh2, unsigned int m68k_cycles)
{
if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1))
Pico32x.sh2irqi[0] |= P32XI_CMD;
@ -207,8 +207,8 @@ void PicoReset32x(void)
{
if (PicoIn.AHW & PAHW_32X) {
p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VRES);
p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, SekCyclesDone());
p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, SekCyclesDone());
p32x_pwm_ctl_changed();
p32x_timers_recalc();
}
@ -258,7 +258,7 @@ static void p32x_start_blank(void)
p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, SekCyclesDone());
}
void p32x_schedule_hint(SH2 *sh2, int m68k_cycles)
void p32x_schedule_hint(SH2 *sh2, unsigned int m68k_cycles)
{
// rather rough, 32x hint is useless in practice
int after;
@ -370,9 +370,9 @@ static void p32x_run_events(unsigned int until)
oldest, event_time_next);
}
static void run_sh2(SH2 *sh2, int m68k_cycles)
static void run_sh2(SH2 *sh2, unsigned int m68k_cycles)
{
int cycles, done;
unsigned int cycles, done;
pevt_log_sh2_o(sh2, EVT_RUN_START);
sh2->state |= SH2_STATE_RUN;

20
pico/32x/draw_arm.S
View file

@ -6,7 +6,7 @@
@* See COPYING file in the top-level directory.
@*
#include "pico/pico_int_o32.h"
#include "pico/pico_int_offs.h"
.extern Pico32x
.extern Pico
@ -74,7 +74,7 @@ Pico32xNativePal:
ldr lr,=Pico
ldr r10,=Pico32x
ldr r11, [lr, #OFS_Pico_est+OFS_EST_Draw2FB]
ldr r10,[r10, #0x40] @ Pico32x.vdp_regs[0]
ldrh r10,[r10, #0x40] @ Pico32x.vdp_regs[0]
add r9, lr, #OFS_Pico_est+OFS_EST_HighPal @ palmd
and r4, r2, #0xff
@ -118,6 +118,8 @@ Pico32xNativePal:
mov r7, r7, lsl #1
ldreqh r12,[r9, r7]
streqh r12,[r0], #2 @ *dst++ = palmd[*pmd]
.else
addeq r0, r0, #2
.endif
beq 2b @ loop_inner
@ -182,8 +184,8 @@ Pico32xNativePal:
ldrneb r8, [r5, #2]! @ r7,r8 - pixel 0,1 index
subs r6, r6, #1
blt 0b @ loop_outer
@ cmp r7, r8 @ is this really improving things?
@ beq 5f @ check_fill @ +8
cmp r7, r8 @ is this really improving things?
beq 5f @ check_fill @ +8
3: @ no_fill:
mov r12,r7, lsl #1
@ -242,7 +244,7 @@ Pico32xNativePal:
beq 6b
7: @ count_done
sub r5, r5, #4 @ undo readahead
sub r5, r5, #4 @ undo readahead
@ fix alignment and check type
sub r8, r5, lr
@ -268,14 +270,14 @@ Pico32xNativePal:
b 2b @ loop_inner
9: @ bg_mode:
ldrb r12,[r11],#1 @ MD pixel
ldrb r12,[r11],#1 @ MD pixel 0,1
ldrb lr, [r11],#1
cmp r3, lr, lsl #26 @ MD has bg pixel?
cmp r3, r12,lsl #26 @ MD pixel 0 has bg?
.if \do_md
mov r12,r12,lsl #1
ldrneh r12,[r9, r12] @ t = palmd[*pmd]
moveq r12,r7
cmp r3, lr, lsl #26
cmp r3, lr, lsl #26 @ MD pixel 1 has bg?
mov lr, lr, lsl #1
ldrneh lr, [r9, lr]
moveq lr, r7
@ -283,7 +285,7 @@ Pico32xNativePal:
strh lr, [r0], #2
.else
streqh r7, [r0]
cmp r3, lr, lsl #26
cmp r3, lr, lsl #26 @ MD pixel 1 has bg?
streqh r7, [r0, #2]
add r0, r0, #4
.endif

8
pico/32x/memory.c
View file

@ -398,9 +398,6 @@ static void p32x_reg_write8(u32 a, u32 d)
p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
comreg = 1 << (a & 0x0f) / 2;
Pico32x.comm_dirty |= comreg;
if (cycles - (int)msh2.m68krcycles_done > 120)
p32x_sync_sh2s(cycles);
return;
}
}
@ -453,6 +450,9 @@ static void p32x_reg_write16(u32 a, u32 d)
int cycles = SekCyclesDone();
int comreg;
if (r[a / 2] == d)
return;
p32x_sync_sh2s(cycles);
r[a / 2] = d;
@ -685,7 +685,7 @@ static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
case 0x3f:
return;
pwm_write:
p32x_pwm_write16(a & ~1, d, sh2, 0);
p32x_pwm_write16(a & ~1, d, sh2, sh2_cycles_done_m68k(sh2));
return;
}

76
pico/32x/memory_arm.S
View file

@ -6,7 +6,7 @@
* See COPYING file in the top-level directory.
*/
#include "../pico_int_o32.h"
#include "../pico_int_offs.h"
@ 32X bank sizes... TODO this should somehow come from an include file
.equ SH2_ROM_SHIFT, 10 @ 0x003fffff
@ -46,92 +46,92 @@
sh2_read8_rom:
ldr ip, [r1, #OFS_SH2_p_rom]
eor r0, r0, #1
lsl r0, #SH2_ROM_SHIFT
mov r0, r0, lsl #SH2_ROM_SHIFT
ldrb r0, [ip, r0, lsr #SH2_ROM_SHIFT]
bx lr
sh2_read8_sdram:
ldr ip, [r1, #OFS_SH2_p_sdram]
eor r0, r0, #1
lsl r0, #SH2_RAM_SHIFT
mov r0, r0, lsl #SH2_RAM_SHIFT
ldrb r0, [ip, r0, lsr #SH2_RAM_SHIFT]
bx lr
sh2_read8_da:
ldr ip, [r1, #OFS_SH2_p_da]
eor r0, r0, #1
lsl r0, #SH2_DA_SHIFT
mov r0, r0, lsl #SH2_DA_SHIFT
ldrb r0, [ip, r0, lsr #SH2_DA_SHIFT]
bx lr
sh2_read8_dram:
ldr ip, [r1, #OFS_SH2_p_dram]
eor r0, r0, #1
lsl r0, #SH2_DRAM_SHIFT
mov r0, r0, lsl #SH2_DRAM_SHIFT
ldrb r0, [ip, r0, lsr #SH2_DRAM_SHIFT]
bx lr
sh2_read16_rom:
ldr ip, [r1, #OFS_SH2_p_rom]
lsl r0, #SH2_ROM_SHIFT
lsr r0, #SH2_ROM_SHIFT
mov r0, r0, lsl #SH2_ROM_SHIFT
mov r0, r0, lsr #SH2_ROM_SHIFT
ldrh r0, [ip, r0]
bx lr
sh2_read16_sdram:
ldr ip, [r1, #OFS_SH2_p_sdram]
lsl r0, #SH2_RAM_SHIFT
lsr r0, #SH2_RAM_SHIFT
mov r0, r0, lsl #SH2_RAM_SHIFT
mov r0, r0, lsr #SH2_RAM_SHIFT
ldrh r0, [ip, r0]
bx lr
sh2_read16_da:
ldr ip, [r1, #OFS_SH2_p_da]
lsl r0, #SH2_DA_SHIFT
lsr r0, #SH2_DA_SHIFT
mov r0, r0, lsl #SH2_DA_SHIFT
mov r0, r0, lsr #SH2_DA_SHIFT
ldrh r0, [ip, r0]
bx lr
sh2_read16_dram:
ldr ip, [r1, #OFS_SH2_p_dram]
lsl r0, #SH2_DRAM_SHIFT
lsr r0, #SH2_DRAM_SHIFT
mov r0, r0, lsl #SH2_DRAM_SHIFT
mov r0, r0, lsr #SH2_DRAM_SHIFT
ldrh r0, [ip, r0]
bx lr
sh2_read32_rom:
ldr ip, [r1, #OFS_SH2_p_rom]
lsl r0, #SH2_ROM_SHIFT
mov r0, r0, lsl #SH2_ROM_SHIFT
ldr r0, [ip, r0, lsr #SH2_ROM_SHIFT]
ror r0, r0, #16
mov r0, r0, ror #16
bx lr
sh2_read32_sdram:
ldr ip, [r1, #OFS_SH2_p_sdram]
lsl r0, #SH2_RAM_SHIFT
mov r0, r0, lsl #SH2_RAM_SHIFT
ldr r0, [ip, r0, lsr #SH2_RAM_SHIFT]
ror r0, r0, #16
mov r0, r0, ror #16
bx lr
sh2_read32_da:
ldr ip, [r1, #OFS_SH2_p_da]
lsl r0, #SH2_DA_SHIFT
mov r0, r0, lsl #SH2_DA_SHIFT
ldr r0, [ip, r0, lsr #SH2_DA_SHIFT]
ror r0, r0, #16
mov r0, r0, ror #16
bx lr
sh2_read32_dram:
ldr ip, [r1, #OFS_SH2_p_dram]
lsl r0, #SH2_DRAM_SHIFT
mov r0, r0, lsl #SH2_DRAM_SHIFT
ldr r0, [ip, r0, lsr #SH2_DRAM_SHIFT]
ror r0, r0, #16
mov r0, r0, ror #16
bx lr
sh2_write8_sdram:
@ preserve r0 and r2 for tail call
ldr ip, [r2, #OFS_SH2_p_sdram]
eor r3, r0, #1
lsl r3, #SH2_RAM_SHIFT
mov r3, r3, lsl #SH2_RAM_SHIFT
strb r1, [ip, r3, lsr #SH2_RAM_SHIFT]
#ifdef DRC_SH2
ldr ip, [r2, #OFS_SH2_p_drcblk_ram]
@ -148,7 +148,7 @@ sh2_write8_da:
@ preserve r0 and r2 for tail call
ldr ip, [r2, #OFS_SH2_p_da]
eor r3, r0, #1
lsl r3, #SH2_DA_SHIFT
mov r3, r3, lsl #SH2_DA_SHIFT
strb r1, [ip, r3, lsr #SH2_DA_SHIFT]
#ifdef DRC_SH2
ldr ip, [r2, #OFS_SH2_p_drcblk_da]
@ -165,15 +165,15 @@ sh2_write8_dram:
tst r1, #0xff
ldrne ip, [r2, #OFS_SH2_p_dram]
eorne r3, r0, #1
lslne r3, #SH2_DRAM_SHIFT
movne r3, r3, lsl #SH2_DRAM_SHIFT
strneb r1, [ip, r3, lsr #SH2_DRAM_SHIFT]
bx lr
sh2_write16_sdram:
@ preserve r0 and r2 for tail call
ldr ip, [r2, #OFS_SH2_p_sdram]
lsl r3, r0, #SH2_RAM_SHIFT
lsr r3, r3, #SH2_RAM_SHIFT
mov r3, r0, lsl #SH2_RAM_SHIFT
mov r3, r3, lsr #SH2_RAM_SHIFT
strh r1, [ip, r3]
#ifdef DRC_SH2
ldr ip, [r2, #OFS_SH2_p_drcblk_ram]
@ -188,8 +188,8 @@ sh2_write16_sdram:
sh2_write16_da:
@ preserve r0 and r2 for tail call
ldr ip, [r2, #OFS_SH2_p_da]
lsl r3, r0, #SH2_DA_SHIFT
lsr r3, r3, #SH2_DA_SHIFT
mov r3, r0, lsl #SH2_DA_SHIFT
mov r3, r3, lsr #SH2_DA_SHIFT
strh r1, [ip, r3]
#ifdef DRC_SH2
ldr ip, [r2, #OFS_SH2_p_drcblk_da]
@ -204,23 +204,23 @@ sh2_write16_da:
sh2_write16_dram:
ldr ip, [r2, #OFS_SH2_p_dram]
tst r0, #SH2_DRAM_OW
lsl r3, r0, #SH2_DRAM_SHIFT
lsr r3, r3, #SH2_DRAM_SHIFT
mov r3, r0, lsl #SH2_DRAM_SHIFT
mov r3, r3, lsr #SH2_DRAM_SHIFT
streqh r1, [ip, r3]
bxeq lr
add ip, ip, r3
tst r1, #0xff
strneb r1, [ip, #0]
tst r1, #0xff00
lsrne r1, r1, #8
movne r1, r1, lsr #8
strneb r1, [ip, #1]
bx lr
sh2_write32_sdram:
@ preserve r0 and r2 for tail call
ldr ip, [r2, #OFS_SH2_p_sdram]
ror r1, r1, #16
lsl r3, r0, #SH2_RAM_SHIFT
mov r1, r1, ror #16
mov r3, r0, lsl #SH2_RAM_SHIFT
str r1, [ip, r3, lsr #SH2_RAM_SHIFT]
#ifdef DRC_SH2
ldr ip, [r2, #OFS_SH2_p_drcblk_ram]
@ -242,8 +242,8 @@ sh2_write32_sdram:
sh2_write32_da:
@ preserve r0 and r2 for tail call
ldr ip, [r2, #OFS_SH2_p_da]
ror r1, r1, #16
lsl r3, r0, #SH2_DA_SHIFT
mov r1, r1, ror #16
mov r3, r0, lsl #SH2_DA_SHIFT
str r1, [ip, r3, lsr #SH2_DA_SHIFT]
#ifdef DRC_SH2
ldr ip, [r2, #OFS_SH2_p_drcblk_da]
@ -265,13 +265,13 @@ sh2_write32_da:
sh2_write32_dram:
ldr ip, [r2, #OFS_SH2_p_dram]
tst r0, #SH2_DRAM_OW
lsl r3, r0, #SH2_DRAM_SHIFT
roreq r1, r1, #16
mov r3, r0, lsl #SH2_DRAM_SHIFT
moveq r1, r1, ror #16
streq r1, [ip, r3, lsr #SH2_DRAM_SHIFT]
bxeq lr
#if 1
ldr r0, [ip, r3, lsr #SH2_DRAM_SHIFT]
ror r1, r1, #16
mov r1, r1, ror #16
mov r2, #0
tst r1, #0x00ff0000
orrne r2, r2, #0x00ff0000

4
pico/cd/gfx_dma.c
View file

@ -10,10 +10,6 @@
#include "cell_map.c"
#ifndef UTYPES_DEFINED
typedef unsigned short u16;
#endif
// check: Heart of the alien, jaguar xj 220
PICO_INTERNAL void DmaSlowCell(unsigned int source, unsigned int a, int len, unsigned char inc)
{

2
pico/cd/memory_arm.S
View file

@ -6,7 +6,7 @@
@* See COPYING file in the top-level directory.
@*
#include "../pico_int_o32.h"
#include "../pico_int_offs.h"
.equiv PCM_STEP_SHIFT, 11

2
pico/draw2_arm.S
View file

@ -8,7 +8,7 @@
* this is highly specialized, be careful if changing related C code!
*/
#include "pico_int_o32.h"
#include "pico_int_offs.h"
@ define these constants in your include file:
@ .equiv START_ROW, 1

2
pico/draw_arm.S
View file

@ -8,7 +8,7 @@
* this is highly specialized, be careful if changing related C code!
*/
#include "pico_int_o32.h"
#include "pico_int_offs.h"
.extern DrawStripInterlace

5
pico/memory.h
View file

@ -2,11 +2,6 @@
#include "pico_port.h"
typedef unsigned char u8;
typedef unsigned short u16;
typedef unsigned int u32;
typedef uintptr_t uptr; // unsigned pointer-sized int
#define M68K_MEM_SHIFT 16
// minimum size we can map
#define M68K_BANK_SIZE (1 << M68K_MEM_SHIFT)

2
pico/memory_amips.S
View file

@ -8,7 +8,7 @@
# OUT OF DATE
#include "pico_int_o32.h"
#include "pico_int_offs.h"
.set noreorder
.set noat

2
pico/memory_arm.S
View file

@ -6,7 +6,7 @@
* See COPYING file in the top-level directory.
*/
#include "pico_int_o32.h"
#include "pico_int_offs.h"
.equ SRR_MAPPED, (1 << 0)
.equ SRR_READONLY, (1 << 1)

18
pico/pico_int.h
View file

@ -33,6 +33,14 @@ extern "C" {
#endif
typedef unsigned char u8;
typedef signed char s8;
typedef unsigned short u16;
typedef signed short s16;
typedef unsigned int u32;
typedef signed int s32;
typedef uintptr_t uptr; // unsigned pointer-sized int
// ----------------------- 68000 CPU -----------------------
#ifdef EMU_C68K
#include "../cpu/cyclone/Cyclone.h"
@ -427,7 +435,7 @@ struct PicoSound
short psg_line;
};
// run tools/mkoffsets pico/pico_int_o32.h if you change these
// run tools/mkoffsets pico/pico_int_offs.h if you change these
// careful with savestate compat
struct Pico
{
@ -905,13 +913,13 @@ void PicoFrame32x(void);
void Pico32xStateLoaded(int is_early);
void p32x_sync_sh2s(unsigned int m68k_target);
void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);
void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);
void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);
void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);
void p32x_update_irls(SH2 *active_sh2, unsigned int m68k_cycles);
void p32x_trigger_irq(SH2 *sh2, unsigned int m68k_cycles, unsigned int mask);
void p32x_update_cmd_irq(SH2 *sh2, unsigned int m68k_cycles);
void p32x_reset_sh2s(void);
void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);
void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);
void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);
void p32x_schedule_hint(SH2 *sh2, unsigned int m68k_cycles);
// 32x/memory.c
extern struct Pico32xMem *Pico32xMem;